Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Applicant’s election without traverse of Group I (claims 1-11 and 15) in response/amendment is acknowledged. The requirement is still deemed proper and is therefore made FINAL.
Information Disclosure Statement
The prior art documents submitted by Applicant(s) in the information Disclosure Statement(s) have all been considered and made of record (note the attached copy of form(s) PTO-1449).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-2, 6-8, 11 and 15 are rejected under AIA 35 U.S.C. 103(a) as being unpatentable over Kuo et al., US 20210181545 A1.
Regarding claim 1, Kuo teaches a semiconductor structure (see figs.1-8, abstract) comprising:
a semiconductor wafer and a photonic integrated circuit or an electronic-photonic integrated circuit hereinafter commonly referred to as integrated circuit , on the semiconductor wafer (see at least figs. 1-8; and parag. 0111, 0083, 0100, 0108-0110, 0120…),
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wherein the integrated circuit comprises a front-end-of-line section, hereinafter FEOL section, and comprises a back-end-of-line section, hereinafter BEOL section, with interconnect layer pairs (clearly shown in at least figs. 1-2) each comprising
a metal interconnect layer and an interlevel dielectric layer (see at least fig. 2, 3-4 and parag. 0022, 0032, 0040…), and wherein a wafer-to-wafer bonding interface is formed between a first of the interconnect layer pairs and a second of the interconnect layer pairs (see at least parag. 0011), the second of the interconnect layer pairs is arranged closer to the FEOL section than the first interconnect layer pair (see at least fig. 2, and parag. 0111; noting that the “second/last” layer for example is being bonded to the semiconductor substrate that is closer than upper/ other interconnect layer), or a wafer-to-wafer bonding interface is formed between the first of the interconnect layer pairs and the FEOL section, wherein the first interconnect layer pair comprises at least one SiN waveguide (see at least fig. 2, and parag. 0111; and parag. 0040).
However, Kuo does not explicitly teach that the above “second of the interconnect layer pairs is arranged closer to the FEOL section than the first interconnect layer pair”. Nonetheless, as shown in fig,. 2 and as stated by Kuo, that there is bonding in between the layer wafers as well as with the semiconductor substrate that would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention made that the at least last/”second” of the interconnect layer pairs is/would-be arranged closer to the FEOL section than the upper/”first” interconnect layer pair (see parag. 0111 and fig. 2).
The arguments presented in in rejection of claim 1, including the obviousness and motivation are incorporated in rejection of the following claims as follows:
2. (Original) The semiconductor structure according to claim 1, wherein the first interconnect layer pair is embedded between further interconnect layer pairs of the BEOL section (clearly shown in at least fig. 2). 3-5, 9-10
6. (Original) The semiconductor structure according to claim 1, wherein the at least one SiN waveguide of the first interconnect layer pair is configured to guide electromagnetic radiation at a wavelength of 850 nm or more with a loss of below or no more than 1 db per cm (see at least parag. 0101 that embodies the wavelength range which would include the same loss).
7. (Original) The semiconductor structure according to claim 1, wherein the semiconductor wafer comprises a local backside etch at a position opposite the at least one SiN waveguide of the first interconnect layer pair (see at least figs. 1b, 2, and parag. 0111; and parag. 0040).
. 8. (Original) The semiconductor structure according to claim 1, wherein at least one interconnect layer pair includes a though-backend interlayer coupler that is arranged and configured for coupling electromagnetic radiation out of or into the at least one SiN waveguide of the first interconnect layer pair (see at least figs. 1b, 2, and parag. 0111; and parag. 0040).
11. (Original) The semiconductor structure according to claim 1, comprising a wafer- to-wafer bonding “enhancement” layer that is arranged to form the wafer-to-wafer bonding interface with the first of the interconnect layer pairs (see at least figs. 2, and parag. 0111, 0117, 0113, 0115).
. 15. (Original) A use of the semiconductor structure according to claim 1 in optical networking or in a telecommunication network (see such method limitation para. 0104).
Allowable Subject Matter
Claims 3-5, 9-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Citation of Relevant Prior Art
Prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. In accordance with MPEP 707.05 the following references are pertinent in rejection of this application since they provide substantially the same information disclosure as this patent does. These references are:
US 12392974 B2
US 20250147345 A1
US 11513289 B1
US 20210181545 A1
US 9419041 B2 teaches at least claim 1
US 9362444 B1
US 8532449 B2
US 8184929 B2
US 6690845 B1
US 6684007 B2
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAVEH C KIANNI whose telephone number is (571)272-2417. The examiner can normally be reached on 9-19.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas Hollweg can be reached on571-270-1739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KAVEH C KIANNI/Primary Examiner, Art Unit 2874