Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 01/05/2026 regarding the prior art rejections of Claims 1, 6, and 11
have been fully considered, but they are not persuasive.
The Examiner agrees Chakravarty in view of Skreen fails to teach the increase, decrease, or the incremental increase of a drive strength value.
The Examiner disagrees Sul does provide significance in relation to the amendments of claims 1,6, and 11. (Sul: 0095 & 0096, the amplitude of the same test waveform may be increased by a desired amplification factor. An amplification factor may be determined from the signal detector threshold and the crosstalk threshold. To distinguish the crosstalk from the bridging fault, more detailed analysis may be carried out by reducing the amplitude and/or the number of transitions in the input waveform.) In the present application, [0062] The drive strength is a measure of the current and voltage capabilities of the transmitter macro 218. The drive strength control mechanism 302 is used to increase or decrease the drive strength to balance signal integrity, manage power consumption, and mitigate potential electromagnetic interference. One skilled in the art could conclude drive strength control is the equivalent of amplitude control and in the claimed invention.
Claims 2 – 5 which depend from amended claim 1, have been considered and rejected.
Claims 7 – 10 which depend from amended claim 6, have been considered and rejected.
Claims 12 – 20 which depend from amended claim 11, have been considered and rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chakravarty (US
2024/0027516 A1) in view of Sul (US 2010/0188097 A1).
Regarding claim 1, Chakravarty teaches:
A system comprising: a first chiplet (Fig 9A and [0074], TxDie) connected to a second chiplet (Fig 9A and [0074], RxDie) via a plurality of interconnects (Fig 2A and [0074 & 0075], an interconnect architecture for a cluster), of a test pattern transmitted to and received by the second chiplet ([0086], the received test signals to reach an Rx comparator 1065);
and one or more repair multiplexers (Fig 9A. [0074 & 0075], repair configuration multiplexers) configured to selectively enable a repair path (Fig 2A & 9A. [0074, 0075, & 0046], Tx lane repair logic 910 receives data on an input path) responsive to a short fault between two interconnects of the plurality of interconnects based on the received test pattern (Fig 8 [0068], a periodic signal 800 is applied to the lane under test, e.g., the lane currently selected to be tested for a defect).
Chakravarty fails to teach:
the first chiplet comprising a drive strength controller configured to increase or decrease a drive strength value;
However, Sul teaches:
the first chiplet comprising a drive strength controller configured to control a drive strength value (Sul: 0095 & 0096, the amplitude of the same test waveform may be increased by a desired amplification factor. An amplification factor may be determined from the signal detector threshold and the crosstalk threshold. To distinguish the crosstalk from the bridging fault, more detailed analysis may be carried out by reducing the amplitude and/or the number of transitions in the input waveform.) Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Chakravarty (Chakravarty: [Abstract], to test, repair, and diagnostic solution for chip-to-chip interconnects) and Sul (Sul: [0095] & [0096], reducing the amplitude and/or the number of transitions in the input waveform).
With regards to claim 2, Chakravarty teaches:
The system of claim 1, wherein a test pattern is generated on behalf of the first chiplet, and wherein the test pattern is checked on behalf of the second chiplet ([0074], Tx finite state machine (FSM) which generates the test stimuli; The Rx die also…analyzes the response).
With regards to claim 3, Chakravarty in view of Sul teaches:
The system of claim 2, wherein the second chiplet is configured to indicate a checker fail responsive to the test pattern being different from the test pattern generated on behalf of the first chiplet ([0133], the second finite state machine is to compare a signal detected on the receive lane under test to an expected response, and the signal detected is received on the receive lane under test).
With regards to claim 4, Chakravarty in view of Sul teaches:
The system of claim 3, wherein the checker fail occurs after one repair of an additional short fault between the two interconnects of the plurality of interconnects ([0133], test each receive lane of the set of receive lanes, one receive lane at a time).
With regards to claim 5, Chakravarty in view of Sul teaches:
The system of claim 1, further comprising: an interposer including the plurality of interconnects connecting a plurality of chiplets including the first chiplet and the second chiplet; and a package including the plurality of chiplets, and the interposer. ([01433], an interposer being a silicon board)
Regarding claim 6, Chakravarty teaches:
A chiplet comprising: a transmitter macro circuit ([0074], TxDie) configured to transmit a first test pattern to an additional chiplet during a self-test ([0074], one die is the transmitting die (TxDie), e.g., the die transmitting a signal, and the other die is the receiving die (RxDie), e.g., the die receiving a signal. Generally, the architecture includes built-in self-test (BIST) components at the Tx and Rx dice),
the chiplet configured to be connected to the additional chip via a plurality of interconnects ([0074, 0052, & 0054], an interconnect architecture for a cluster; the interconnects for Die1 and Die2 are micro bumps while the interconnects between Die2 and Die3 are hybrid bonding interconnects (HBI); Similarly, a Tx circuit 540 in Die3 can transmit signals to an Rx circuit 545 in Die1 via an HBI 542, a through-silicon via 543 (TSV) and a pair of micro bumps 544);
a receiver macro circuit ([0074], RxDie) configured to receive a second test pattern from the additional chiplet during the self-test (Fig 2a. & [0074]) ; the transmitter macro circuit (Fig. 6, [0092] & [0095], the Tx die, the programmable clock modifier modules CMM1-CMM3 can be used) during transmission of the first test pattern to the additional chiplet to compensate for an additional load created by a short fault between the chiplet and the additional chiplet (Fig. 6, [0092], & [0095], compensate for discrepancies in silicon in the clock network between the two die.); and a programmable delay mechanism ([0094] & [0095], the clock control circuit 1105 controls the clock burst used for testing the interconnects, where the number of clock cycles is programmable) configured to adjust a sampling window of the receiver macro circuit during reception of the second test pattern from the additional chiplet ([0094] & [0095], clock modifiers), the second test pattern interpreted as received to indicate a viability of using a repair path to bypass the short fault between the chiplet and the additional chiplet ([0064, 0074, & 0133], single line stress tests can be used both for testing and identifying failing lanes. A redundant lane can be used to replace each lane which is found to be defective.).
Chakravarty fails to teach:
a drive strength controller configured to incrementally increase a drive strength value;
However, Sul teaches:
a drive strength controller configured to incrementally increase a drive strength value (Sul: 0095 & 0096, the amplitude of the same test waveform may be increased by a desired amplification factor. An amplification factor may be determined from the signal detector threshold and the crosstalk threshold. To distinguish the crosstalk from the bridging fault, more detailed analysis may be carried out by reducing the amplitude and/or the number of transitions in the input waveform.);
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Chakravarty (Chakravarty: [Abstract], to test, repair, and diagnostic solution for chip-to-chip interconnects) and Sul (Sul: [0095] & [0096], reducing the amplitude and/or the number of transitions in the input waveform).
With regards to claim 7, Chakravarty in view of Sul teaches:
The chiplet of claim 6, further comprising a plurality of interconnects connecting the chiplet to the additional chiplet; and wherein the transmitter macro circuit is connected to a further receiver macro circuit of the additional chiplet via an interconnect of the plurality of interconnects (Fig. 2A).
With regards to claim 8, Chakravarty in view of Sul teaches:
The chiplet of claim 7, wherein the short fault is caused by the interconnect being shorted with an additional interconnect of the plurality of interconnects (Figs. 7A- 7D).
With regards to claim 9, Chakravarty in view of Sul teaches:
The chiplet of claim 8, wherein the transmitter macro circuit is configured to receive an output enable signal responsive to the interconnect being shorted with the additional interconnect of the plurality of interconnects ([0060], the transmitting die but not the receiving die includes the buffers B2 and B3. A common enable signal can be used for each of the tristate buffers in a cluster).
With regards to claim 10, Chakravarty in view of Sul teaches:
The chiplet of claim 9, wherein: responsive to the output enable signal being set to one, the drive strength controller is configured to set the drive strength value to a minimum value; or responsive to the output enable signal being set to zero, the transmitter macro circuit is configured to be tri-stated to disable output from the transmitter macro circuit ([0058], When the enable signal is a low level or 0, the buffer is enabled and the output is the complement or inverse of the input. When the enable signal is a high level or 1, the buffer is disabled and the output is at a high impedance condition. The tristate buffer can therefore act as a switch).
Regarding claim 11, Chakravarty teaches:
A method comprising: responsive to detecting two failing lanes between a first chiplet and a second chiplet of a chip package as a result of a short fault ([0064] and [0074], Single line stress tests can be used both for testing and identifying failing lanes. A redundant lane can be used to replace each lane which is found to be defective), deactivating a transmitter macro circuit of a first failing lane of the two failing lanes ([0060] &[0072], Die2, could also include buffers such as B2 and B3 after the diode 620 to disconnect the transmit lanes ) to isolate a second failing lane of the two failing lanes ([0089], failure analysis using die isolation); of a transmitter macro circuit of the second failing lane ([0058] - [0060], Having an active low buffer is helpful as it reduces the power used for the enable control line), used to transmit a signal including a test pattern to a receiver macro circuit of the second failing lane (Fig. 6, [0058] - [0060]); adjusting a sampling window of the receiver macro circuit of the second failing lane ([0095], the programmable clock modifier modules) , the adjusted sampling window used to receive the transmitted signal ([0095]); and executing a sub-routine to determine whether the test pattern is received correctly in the adjusted sampling window by the receiver macro circuit of the second failing lane ([0121], embodiments of the disclosed subject matter may be implemented as part of an operating system or a specific application, component, program, object, module, routine, or other sequence of instructions), an output of the sub-routine indicating whether or not the chip package is repairable based on a number of times the test pattern is received correctly ([0095], At the Rx die, the clock monitor 1140 counts the number of clock cycles).
Chakravarty fails to teach:
incrementally increasing a drive strength;
However, Sul teaches:
incrementally increasing a drive strength (Sul: 0095 & 0096, the amplitude of the same test waveform may be increased by a desired amplification factor. An amplification factor may be determined from the signal detector threshold and the crosstalk threshold. To distinguish the crosstalk from the bridging fault, more detailed analysis may be carried out by reducing the amplitude and/or the number of transitions in the input waveform.);
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Chakravarty (Chakravarty: [Abstract], to test, repair, and diagnostic solution for chip-to-chip interconnects) and Sul (Sul: [0095] & [0096], reducing the amplitude and/or the number of transitions in the input waveform).
With regards to claim 12, Chakravarty in view of Sul teaches:
The method of claim 11, wherein the short fault is between a first interconnect in the first failing lane and a second interconnect in the second failing lane ([0064] and [0074]).
With regards to claim 13, Chakravarty in view of Sul teaches:
The method of claim 12, wherein the first failing lane and the second failing lane are adjacent to each other ([0025], adjacent dice to allow signals to pass between the two dice).
With regards to claim 14, Chakravarty in view of Sul teaches:
The method of claim 12, wherein the first failing lane and the second failing lane are neighboring a third lane (Fig. 2A & [0046], Each cluster can also include one or more redundant lanes, and a clock lane).
With regards to claim 15, Chakravarty in view of Sul teaches:
The method of claim 11, wherein the chip includes a system-on-a-chip ([0107], described herein to form a System in Package (SiP) or a System on Chip (SoC)).
With regards to claim 16, Chakravarty in view of Sul teaches the method of claim 11. Chakravarty fails to teach:
wherein executing the sub-routine comprises: incrementing the sampling window of the second receiver macro circuit of the second failing lane; incrementing the drive strength of the second transmitter macro circuit of the second failing lane; and transmitting, by the second transmitter macro circuit, for a number of cycles, a pattern generated by the first chiplet to the second chiplet.
Sul teaches:
wherein executing the sub-routine comprises: incrementing the sampling window of the second receiver macro circuit of the second failing lane (Sul: [0095], the amplitude of the same test waveform may be increased by a desired amplification factor; incrementing the drive strength of the second transmitter macro circuit of the second failing lane (Sul: [0095]); and transmitting, by the second transmitter macro circuit, for a number of cycles, a pattern generated by the first chiplet to the second chiplet (Sul: [0072], Each test pattern is transmitted M times by the transmitter).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Chakravarty (Chakravarty: [0095], programmable clock modifier modules) and Sul (Sul: [0095] & [0096], reducing the amplitude and/or the number of transitions in the input waveform) to develop this sub-routine (Sul: [0006]).
With regards to claim 17, Chakravarty in view of Sul teaches the method of claim 16:
wherein executing the sub-routine further comprises ([0121]), responsive to the second chiplet identifying one checker failure, providing the output indicating that the chip package is repairable (Fig. 10, [0083], a comparator comparing the expected response with the observed response; (iv) error register, one per lane; and (v) an error analyzer which calculates the repair signature, if repair is possible).
With regards to claim 18, Chakravarty in view of Sul teaches the method of claim 16:
wherein executing the sub-routine further includes ([0121]), responsive to the second chiplet identifying two checker failures ([0083], Both the TxDie and the RxDie can include… an error analyzer), maximizing the drive strength of the second transmitter macro circuit ([0058], A tristate buffer has three possible output states: high (1), low (0) and floating), and maximizing the sampling window of the second receiver macro circuit ([0095], programmable clock modifier modules): deactivating the second transmitter macro circuit of the second failing lane of the two failing lanes ([0061], the tristate buffer is disabled); minimizing a drive strength value of the first transmitter macro circuit of the first failing lane of the two failing lanes ([0058], active-low inverting tristate buffer…the output is enabled or disabled when a logic level “0” is applied to the enable control line); adjusting a sampling window of a first receiver macro circuit of the first failing lane ([0095]); and re-executing the sub-routine ([0121]), the output of which indicates whether or not the chip package is repairable ([0083]).
With regards to claim 19, Chakravarty in view of Sul teaches the method of claim 16:
The method of claim 18, wherein, responsive to the output of re-executing the sub-routine indicating one checker failure, providing the output indicating that the chip package is repairable ([0083]).
With regards to claim 20, Chakravarty in view of Sul teaches the method of claim 16:
The method of claim 18, wherein, responsive to the output of re-executing the sub-routine ([0121]) identifying two checker failures ([0083], Both the TxDie and the RxDie can include… an error analyzer), maximizing the drive strength value of the first transmitter macro circuit ([0058]), and maximizing the sampling window of the first receiver macro circuit ([0095]), providing the output indicating that the chip package is not repairable ([0083]).
Response to Arguments
Applicant's arguments filed 01/05/2026 regarding the prior art rejections of Claims 1, 6, and 11 have been fully considered, but they are not persuasive.
The Remarks argue that:
Claims 1, 6, and 11 stand rejected under § 103 as unpatentable over the combination of Chakravarty in view of Skreen. In the interest of advancing prosecution and without conceding the propriety of the rejection, claims 1, 6, and 11 are amended as discussed during the interview. Claim 1 is amended to recite a system comprising "a first chiplet connected to a second chiplet via a plurality of interconnects, the first chiplet comprising a drive strength controller configured to increase or decrease a drive strength value of a test pattern transmitted to and received by the second chiplet," and "one or more repair multiplexers configured to selectively enable a repair path responsive to a short fault between two interconnects of the plurality of interconnects based on the received test pattern." Claim 6 is amended to recite "a drive strength controller configured to incrementally increase a drive strength value of the transmitter macro circuit during transmission of the first test pattern to the additional chiplet to compensate for an additional load created by a short fault between the chiplet and the additional chiplet." Claim 11 is amended to recite "incrementally increasing a drive strength of a transmitter macro circuit of the second failing lane, the increased drive strength used to transmit a signal including a test pattern to a receiver macro circuit of the second failing lane." As noted above, support for these amendments can be found throughout Applicant's specification and at least at [0016], [0024], [0060], [0062], [0072], and [0075].
As discussed above, during the interview, the Examiner agreed that the subject matter of these amendments is not described by the asserted references of record. In addition, Applicant submits that the asserted references of record do not disclose, teach, or suggest the subject matter of this amendment.
For example, the Office relies on Chakravarty [0046], [0068], [0074], and [0075] for "a first chiplet connected to a second chiplet via a plurality of interconnects ... of a test pattern transmitted to and received by the second chiplet" and "one or more repair multiplexers configured to selectively enable a repair path responsive to a short fault between two interconnects of the plurality of interconnects based on a checked the received test pattern" (Office Action, p. 2). The Office admits that "Chakravarty fails to teach[] the first chiplet comprising a drive strength controller configured to control a drive strength value" (Office Action, p. 2-3). The Office then asserts Skreen [0009, 0021, and 0022] for "the first chiplet comprising a drive strength controller configured to control a drive strength value"(Office Action, p. 3). However, Skreen does not disclose, teach, or suggest a drive strength controller. For example, "the drive strengths of controller 202a" (emphasis added) of Skreen (e.g., as cited at page 3 of the Office Action) are not a "drive strength controller."
In fact, rather than adjusting or controlling drive strengths, Skreen is directed to measuring drive strengths and disabling devices with uncontrollably large variations of drive strength. For example, Skreen (e.g., at [002 1]-[0023]) describes both mismatched drive strengths seemingly beyond the control of controller 202a (e.g., drive strengths divergent "due to manufacturing variations ... or other potential causes") and "disabling a subset of the memoiy devices 202[] which have drive strengths which diverge by the widest margin." See also, e.g., Skreen at [0006], [0007] (describing "memory devices .., packaged together in a stack or on a module [and having] vastly different drive strengths," e.g., "[d]ue to manufacturing variation," and "in which the drive strengths or other performance characteristics . .. can be measured... and information corresponding to these measured performance characteristics can be [used] such that the subset of memory devices selected for disablement can be those with the most poorly-matched drive strength"). Chakravarty and Skreen are missing the subject matter of the amended claims.
Accordingly, Applicant submits that the combination of Chakravarty and Skreen does not teach or in any way suggest the subject matter of claims 1, 6, and 11, particularly as amended. As such, Applicant requests that the § 103 rejections of claim 1, 6, and 11 be withdrawn.
Applicant further submits that Sul does not provide anything of significance in relation to the amendments of claims 1, 6, and 11.
Claims 2-5, 7-10, and 12-20 depend from one of the allowable base claims 1, 6, or 11, and thus are allowable for at least the reason that they depend from an allowable base claim. These claims are also allowable for their own recited features. Accordingly, Applicant respectfully requests that the § 103 rejections of claims 2-5, 7-10, 12-20 be withdrawn.
Claims 2 – 5 which depend from amended claim 1, have been considered and rejected.
Claims 7 – 10 which depend from amended claim 6, have been considered and rejected.
Claims 12 – 20 which depend from amended claim 11, have been considered and rejected.
Conclusion
Applicant's arguments filed 12/29/2025 regarding the prior art rejections of Claims 1 and 10
have been fully considered, but they are not persuasive.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/V.P./Examiner, Art Unit 2111
/GUERRIER MERANT/Primary Examiner, Art Unit 2111 3/4/2026