DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to Applicant’s Amendment filed on 7/7/2026.
Claims 1-20 are presented for examination. Claims 1, 4, 10, 13 and 19-20 have been amended.
Applicant’s amendments to the specification and claims have overcome claim objections and 101 rejection set forth in the non-Final Office Action mailed 5/7/2026.
Examiner Notes
Examiner cites particular columns, paragraphs, figures and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirely as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 10-11, 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (CN107526622A-publication date: 12/29/2017-English translation provided by Google Patents, hereafter Liu) in view of Deshpande et al. (US 7870541 B1, hereafter Deshpande), Lee et al. (US 20090138625 A1, hereafter Lee) and Chittigala (US 20090013145 A1).
Regarding to claim 1, Liu discloses: A user-mode interrupt request processing method (see [0005]; “In the fast exception handling method and device for Linux provided by the embodiments of the present invention”), comprising:
obtaining, by the processor in the kernel mode, a user-mode interrupt request; executing, by the processor in the kernel mode, the second interrupt exception handler (see [0002]-[0003], [0005], [0014]; “issuing an interrupt request”, “interrupt service routine (ISR)”, “interrupt processing in systems based on embedded mainstream processors (ppc, arm, etc.)”, “In the fast exception handling method and device for Linux provided by the embodiments of the present invention … When executing, the main program and the interrupt handler … exiting from kernel mode to user mode, that is, there is no need to save the context when switching from user mode to kernel mode, so that Reduce the overhead time of interrupt processing”. In order to exist from kernel mode to user mode, a corresponding interrupt, i.e., claimed user-mode interrupt request, should be issued and then received or obtained by embedded mainstream processor in kernel mode, and a corresponding interrupt handler should be executed by embedded mainstream processor in kernel mode. Also see [0018]-[0022]; “There are three ways to switch from user mode to kernel mode: 1: System call; 2: Interrupt; 3: Abnormal”. Note: although [0018]-[0022] are described as “switch from user mode to kernel mode”, it is understood that similar operations are required to switch from kernel mode to user mode.);
switching, by the processor, to a user mode from the kernel mode through first privilege level switching, wherein the first privilege level switching is switching without context recovery, and the first privilege level switching including pointing context associated with the user mode (see [0014]; “In the fast exception handling method and device for Linux provided by the embodiments of the present invention … When executing, the main program and the interrupt handler … exiting from kernel mode to user mode, that is, there is no need to save the context when switching from user mode to kernel mode, so that Reduce the overhead time of interrupt processing”. Note1: if there is no need to save the context during switching between kernel and user modes, the process of context recovery is not necessary performed neither since there is no context to be recovered. Note2: it is understood that the context switch is required to performed via pointing to context of the target context or address of the target context, otherwise the system cannot switch to correct context);
executing, by the processor in the user mode, the user-mode interrupt handler; and switching, by the processor, to the kernel mode from the user mode through second privilege level switching, wherein the second privilege level switching is switching without context storage (see [0014]; “In the fast exception handling method and device for Linux provided by the embodiments of the present invention … When executing, the main program and the interrupt handler … when falling from user mode to kernel mode … that is, there is no need to save the context when switching from user mode to kernel mode, so that Reduce the overhead time of interrupt processing”. Note: it is understood that for the process of failing from user mode to kernel mode, corresponding interrupt handler, i.e., claimed user-mode interrupt handler, is executed in the user mode).
Liu does not disclose:
performing, by a processor in a kernel mode, anonymization processing on a kernel address of a first interrupt exception handler to obtain a second interrupt exception handler;
pointing context associated with the user mode comprises pointing a stack pointer register to a user stack and pointing a program counter to a user mode address;
executing the second interrupt exception handler to determine a user-mode interrupt handler corresponding to the user-mode interrupt request.
However, Deshpande discloses: switching, by the processor, to a user mode from the kernel model through first privilege level switching, and the first privilege level switching includes pointing a stack pointer register to a user stack and pointing a program counter to a user mode address (see lines 51-24 of cols. 5-6; “An execution context of a thread consists of: 1. CPU--which has previously executed or is currently executing or will potentially execute the corresponding thread. In FIG. 3, user thread 312 is running on CPU 0 (322), whereas interrupt 314 is running on CPU 1 (323). Kernel thread 313 potentially has information about the CPU, which was running the thread before being swapped out to wait. 2. Program Counter--which points to the address of machine instruction that the CPU is currently executing (for running thread) or will execute (when the thread is scheduled to execute on the CPU) … 3. Stack Pointer--As described before, the stack is used to store local variables of a function and parameters passed to the function. Stack pointer points to the memory address in user or kernel stack and the machine instructions of a function fetch the local variables or the parameters of the corresponding function with respect to the stack pointer value. Therefore, stack pointer acts as an anchor to help CPU easily locate local variables of a function when the corresponding function is executing on the CPU”. At one of the reasonable embodiments of switching execution of the kernel thread to execution of user thread, the switching would point stack pointer register to the user thread and point program counter to user mode address).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify context switch from Liu by including context switch that at least modifying program counter and stack pointer associated with a current executing thread from Deshpande, since program counter and stack pointer are well-known generic registers to be used for an execution context of a thread (see lines 51-24 of cols. 5-6 of cols. 5-6 from Deshpande).
In addition, Lee discloses: executing the second interrupt exception handler to determine a user-mode interrupt handler corresponding to the user-mode interrupt request (see [0016], [0024]; “interrupt occurs either due to error or completion. The kernel mode ISR dismisses and disables the interrupt, by reading and writing registers, and it signals the user mode ISR event which processes the result”).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify execution of interrupt from the combination of Liu and Deshpande by including process of using kernel model ISR to signal user mode ISR from Lee, since it would provide a mechanism of “serialization of ISR and DMA request eliminates the contention of accessing hardware registers and any share resources” (see [0024] from Lee).
In addition, Chittigala discloses: performing, by a processor in a kernel mode, anonymization processing on a kernel address of a first interrupt exception handler to obtain a second interrupt exception handler (see Fig. 1, [0008] and [0017]; “the tracking system defines its own kernel memory allocation/de-allocation functions and replaces the addresses of all the existing allocation/de-allocation functions in the kernel global symbol table with the addresses of these newly defined functions” and “the dynamically loaded kernel modules 106 may be divided into two groups: … 2) interrupt handlers 112”).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify kernel model ISR from the combination of Liu, Deshpande and Lee by including address replacement of kernel model ISR from Chittigala, and thus the combination of Liu, Deshpande, Lee and Chittigala would disclose the missing limitations from Liu, since it would provide a mechanism to “identify and resolve kernel memory leaks” (see [0008] from Chittigala).
Regarding to Claim 2, the rejection of Claim 1 is incorporated and further the combination of Liu, Deshpande, Lee and Chittigala discloses: wherein performing the anonymization processing on the kernel address of the first interrupt exception handler comprises: overwriting or deleting the kernel address and information in the kernel address in the first interrupt exception handler (see Fig. 1, [0008] and [0017] from Chittigala; “the tracking system defines its own kernel memory allocation/de-allocation functions and replaces the addresses of all the existing allocation/de-allocation functions in the kernel global symbol table with the addresses of these newly defined functions” and “the dynamically loaded kernel modules 106 may be divided into two groups: … 2) interrupt handlers 112”).
Regarding to Claim 10, Claim 10 is a system claim corresponds to method Claim 1 and is rejected for the same reason set forth in the rejection of Claim 1 above (note: according to “In the fast exception handling method and device for Linux provided by the embodiments of the present invention” from [0005] of Liu, it is understood that such “device for Linux” must include claimed “at least one processor and at least one memory coupled to the at least one processor and storing programming instructions for execution by the at least one processor to perform operations”).
Regarding to Claim 11, Claim 11 is a system claim corresponds to method Claim 2 and is rejected for the same reason set forth in the rejection of Claim 2 above.
Regarding to Claim 19, Claim 19 is a product claim corresponds to method Claim 1 and is rejected for the same reason set forth in the rejection of Claim 1 above (note: also see [0083]-[0084] and [0086] from Lee for claimed “A non-transitory computer-readable storage medium”).
Regarding to Claim 20, Claim 20 is a system claim corresponds to method Claim 1 and is rejected for the same reason set forth in the rejection of Claim 1 above (note: according to “In the fast exception handling method and device for Linux provided by the embodiments of the present invention” from [0005] of Liu, it is understood that such “method and device for Linux” must include claimed “A computer program product, wherein the computer program product comprises computer program code which, when run on a computer, causes the computer to perform operations”).
Claims 3-4 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (CN107526622A-publication date: 12/29/2017-English translation provided by Google Patents, hereafter Liu) in view of Deshpande et al. (US 7870541 B1, hereafter Deshpande), Lee et al. (US 20090138625 A1, hereafter Lee) and Chittigala (US 20090013145 A1) and further in view of Serebrin et al. (US 10684970 B1, hereafter Serebrin).
Regarding to Claim 3, the rejection of Claim 1 is incorporated, the combination of Liu, Deshpande, Lee and Chittigala does not disclose: wherein executing the second interrupt exception handler to determine the user-mode interrupt handler corresponding to the user-mode interrupt request comprises: waking up a user-mode interrupt processing thread corresponding to the user-mode interrupt request, wherein the user-mode interrupt processing thread comprises the user-mode interrupt handler; or obtaining an address of the user-mode interrupt handler corresponding to the user-mode interrupt request.
However, Serebrin discloses: wherein executing the second interrupt exception handler to determine the user-mode interrupt handler corresponding to the user-mode interrupt request comprises: waking up a user-mode interrupt processing thread corresponding to the user-mode interrupt request, wherein the user-mode interrupt processing thread comprises the user-mode interrupt handler; or obtaining an address of the user-mode interrupt handler corresponding to the user-mode interrupt request (see Figs. 2, 3, lines 31-55 of col. 5; “showing an interrupt being delivered to an operating system when a processor is in operating system (OS) mode … an execution mode indicator 206 set to a value of “OS,” indicating that the processor 202 is executing in operating system mode. The processor 202 consults an interrupt descriptor table 208 to determine how to handle the received interrupt. Because the processor 202 is currently executing in operating system mode, the processor 202 does not translate the interrupt number, and reads the address of the interrupt handler associated with interrupt number 0x20 from the interrupt descriptor table 208 at row 210. The processor 202 then delivers the interrupt to operating system 220 by calling interrupt handler 222”).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the process of signaling the user mode ISR from kernel model ISR from the combination of Liu, Deshpande, Lee and Chittigala by including transferring user model interrupt handler based on corresponding interrupt number associated with received interrupt from Serebrin, and thus the combination of Liu, Deshpande, Lee, Chittigala and Serebrin would disclose the missing limitations from the combination of Liu, Deshpande, Lee and Chittigala, since it would provide a mechanism of pre-establishing the mapping relationship between interrupt handler and interrupt number for easily locating interrupt handler (see lines 39-47 of col. 4 from Serebrin; “the interrupt descriptor tables 122 include mappings from interrupt numbers to interrupt handler functions. The interrupt handler functions may be stored as memory addresses within the table. When an interrupt associated with particular interrupt number is received, the processor core 104 may consult the interrupt descriptor table 122 to determine the address of the appropriate interrupt handler to call to handle the interrupt”).
Regarding to Claim 4, the rejection of Claim 3 is incorporated and further the combination of Liu, Deshpande, Lee, Chittigala and Serebrin discloses: wherein obtaining the address of the user-mode interrupt handler corresponding to the user-mode interrupt request comprises: obtaining an interrupt number corresponding to the user-mode interrupt request; and obtaining an address of the user-mode interrupt handler corresponding to the interrupt number (see Figs. 2, 3, lines 31-55 of col. 5 from Serebrin; “showing an interrupt being delivered to an operating system when a processor is in operating system (OS) mode … an execution mode indicator 206 set to a value of “OS,” indicating that the processor 202 is executing in operating system mode. The processor 202 consults an interrupt descriptor table 208 to determine how to handle the received interrupt. Because the processor 202 is currently executing in operating system mode, the processor 202 does not translate the interrupt number, and reads the address of the interrupt handler associated with interrupt number 0x20 from the interrupt descriptor table 208 at row 210. The processor 202 then delivers the interrupt to operating system 220 by calling interrupt handler 222”).
Regarding to Claim 12, Claim 12 is a system claim corresponds to method Claim 3 and is rejected for the same reason set forth in the rejection of Claim 3 above.
Regarding to Claim 13, Claim 13 is a system claim corresponds to method Claim 4 and is rejected for the same reason set forth in the rejection of Claim 4 above.
Claims 5, 8, 14 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (CN107526622A-publication date: 12/29/2017-English translation provided by Google Patents, hereafter Liu) in view of Deshpande et al. (US 7870541 B1, hereafter Deshpande), Lee et al. (US 20090138625 A1, hereafter Lee), Chittigala (US 20090013145 A1) and Serebrin et al. (US 10684970 B1, hereafter Serebrin) and further in view of Hagita (US 20080276027 A1).
Regarding to Claim 5, the rejection of Claim 4 is incorporated and further the combination of Liu, Deshpande, Lee, Chittigala and Serebrin discloses: wherein obtaining the interrupt number corresponding to the user-mode interrupt request comprises: reading, by the processor in the kernel mode, a register of an interrupt controller to obtain the interrupt number corresponding to the user-mode interrupt request (see Figs. 2, 3, lines 31-55 of col. 5 from Serebrin; “showing an interrupt being delivered to an operating system when a processor is in operating system (OS) mode … an execution mode indicator 206 set to a value of “OS,” indicating that the processor 202 is executing in operating system mode. The processor 202 consults an interrupt descriptor table 208 to determine how to handle the received interrupt. Because the processor 202 is currently executing in operating system mode, the processor 202 does not translate the interrupt number, and reads the address of the interrupt handler associated with interrupt number 0x20 from the interrupt descriptor table 208 at row 210. The processor 202 then delivers the interrupt to operating system 220 by calling interrupt handler 222”. Also see lines 11- of col. 4 from Serebrin; “Each of the processor cores 104 also includes an interrupt descriptor table register 110. The interrupt descriptor table register 110 may include a memory address within the memory 120 at which a current interrupt descriptor table 122 may be found. In operation, the processor core 104 may consult this register to determine where in the memory its current interrupt descriptor table 122 is located”. Note: claimed interrupt controller can be interpreted as component/object (no matter software component/object or hardware component/object) that has certain controlling or management function).
However, Hagita discloses: wherein the interrupt controller obtains an acknowledgement message, and the acknowledgement message indicates the interrupt controller to mask an interrupt request whose priority is the same as that of the [user-mode] interrupt request, or to mask an interrupt request whose priority is lower than that of the [user-mode] interrupt request (see [0092]; “When the priority order is provided for the interrupt request, the INCT 212 executes an interrupt request of the highest priority among received interrupt requests. At this time, the INCT 212 masks interrupt requests from interrupt factors having priority lower than that of the executed interrupt factor among interrupt factors to which a message number the same as one for the executed interrupt request is assigned”. The interrupt controller obtains interrupt execution acknowledgement message, such message indicates masking interrupt requests having lower priority than the currently executing interrupt).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the execution of interrupt from the combination of Liu, Deshpande, Lee and Chittigala by including masking lower priority interrupt requests during executing higher priority interrupt request from Hagita, and thus the combination of Liu, Deshpande, Lee, Chittigala, Serebrin and Hagita would disclose the missing limitations from the combination of Liu, Deshpande, Lee, Chittigala and Serebrin, since it would provide a mechanism of avoiding executing multiple interrupts concurrently (see [0092] from Hagita).
Regarding to Claim 8, the rejection of Claim 5 is incorporated and further the combination of Liu, Deshpande, Lee, Chittigala, Serebrin and Hagita discloses: when the processor in the user mode executes the user-mode interrupt handler, concurrently detecting, by the processor in the kernel mode, a result status of the user-mode interrupt handler (see lines 1-20 of col. 7 from Serebrin; “receiving an End of Interrupt (EOI) indication from the user process indicating that the user process has finished processing the interrupt after delivering the interrupt as the second interrupt number. In some implementation, an APIC may include a special EOI instruction accessible by the user process. In some cases, the processor may generate an EOI for the user process to the APIC as part of delivering the interrupt”. The APIC executed in the kernel mode continues to wait for receiving EOI, i.e., the APIC in the kernel model concurrently detects result status of the user mode interrupt handler when the user mode interrupt handler is executed in the user mode).
Regarding to Claim 14, Claim 14 is a system claim corresponds to method Claim 5 and is rejected for the same reason set forth in the rejection of Claim 5 above.
Regarding to Claim 17, Claim 17 is a system claim corresponds to method Claim 8 and is rejected for the same reason set forth in the rejection of Claim 8 above.
Claims 6 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (CN107526622A-publication date: 12/29/2017-English translation provided by Google Patents, hereafter Liu) in view of Deshpande et al. (US 7870541 B1, hereafter Deshpande), Lee et al. (US 20090138625 A1, hereafter Lee), Chittigala (US 20090013145 A1), Serebrin et al. (US 10684970 B1, hereafter Serebrin) and Hagita (US 20080276027 A1) and further in view of Chung et al. (US 20110040913 A1, hereafter Chung) and Kimelman et al. (US 20050177666 A1, hereafter Kimelman).
Regarding to Claim 6, the rejection of Claim 5 is incorporated, the combination of Liu, Deshpande, Lee, Chittigala, Serebrin and Hagita does not disclose:
setting, by the processor in the kernel mode, an interrupt priority group for the interrupt controller, wherein the interrupt priority group comprises a first interrupt priority group and a second interrupt priority group, the first interrupt priority group comprises a kernel-mode interrupt request, the second interrupt priority group comprises the interrupt request whose priority is the same as that of the user-mode interrupt request or the interrupt request whose priority is lower than that of the user-mode interrupt request, and a priority of the first interrupt priority group is higher than that of the second interrupt priority group; and
setting, by the processor in the kernel mode, a preemption operation for the interrupt controller, wherein the preemption operation comprises that the first interrupt priority group preempts the second interrupt priority group.
However, Chung discloses: setting, by the processor in the kernel mode, an interrupt priority group for the interrupt controller, wherein the interrupt priority group comprises a first interrupt priority group and a second interrupt priority group, the first interrupt priority group comprises a kernel-mode interrupt request, the second interrupt priority group comprises the interrupt request whose priority is the same as that of the user-mode interrupt request or the interrupt request whose priority is lower than that of the user-mode interrupt request, and a priority of the first interrupt priority group is higher than that of the second interrupt priority group (see [0026]; “When local APIC 308 accepts a user-level interrupt, it routes the interrupt to core 304 for processing (410). In general, the core will process a user-level interrupt when the user-level interrupt has higher priority than other accepted interrupts and a thread currently executing on the core. For example, a user-level interrupt has lower priority than any operating system-level interrupts … core 304 invokes program code for user-level interrupts”).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the interrupts from the combination of Liu, Deshpande, Lee, Chittigala, Serebrin and Hagita by including policy of OS or kernel level interrupts have higher priority than user level interrupts from Chung, since it would provide a mechanism of prioritizing OS or kernel level interrupts to allow OS or kernel level interrupts are handled before user level interrupts (see [0026] from Chung; “When local APIC 308 accepts a user-level interrupt, it routes the interrupt to core 304 for processing (410). In general, the core will process a user-level interrupt when the user-level interrupt has higher priority than other accepted interrupts and a thread currently executing on the core. For example, a user-level interrupt has lower priority than any operating system-level interrupts … core 304 invokes program code for user-level interrupts”).
In addition, Kimelman discloses: setting, by the processor in the kernel mode, a preemption operation for the interrupt controller, wherein the preemption operation comprises that the first interrupt priority group preempts the second interrupt priority group (see [0016] and [0046]-[0047], “A pending interrupt is one where the interrupt signal has been detected by the nested vector interrupt controller 24 but has not yet been actioned, i.e. the associated interrupt handling program has not yet started execution. An active interrupt is one in which the interrupt handling program has started execution, although it may not be currently executing as it may itself have been pre-empted by a higher priority interrupt”).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify interrupt controller having policy of assigning higher priority to OS or kernel level interrupts than user level interrupts from the combination of Liu, Deshpande, Lee, Chittigala, Hagita and Chung by including interrupt controller having policy of allowing a higher priority interrupt preempts resource of current executing interrupt from Kimelman, and thus the combination of Liu, Deshpande, Lee, Chittigala, Hagita, Chung and Kimelman would teach limitations from the combination of Liu, Deshpande, Lee, Chittigala, Serebrin and Hagita, since it would provide a mechanism to ensure higher priority interrupt is executed before lower priority interrupt even if the lower priority interrupt might already started execution (see [0016] and [0046]-[0047] from Kimelman).
Regarding to Claim 15, Claim 15 is a system claim corresponds to method Claim 6 and is rejected for the same reason set forth in the rejection of Claim 6 above.
Claims 7 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (CN107526622A-publication date: 12/29/2017-English translation provided by Google Patents, hereafter Liu) in view of Deshpande et al. (US 7870541 B1, hereafter Deshpande), Lee et al. (US 20090138625 A1, hereafter Lee), Chittigala (US 20090013145 A1), Serebrin et al. (US 10684970 B1, hereafter Serebrin) and Hagita (US 20080276027 A1) and further in view of Liang (CN101699417B-publication date: 8/29/2012-English translation provided by Google Patents).
Regarding to Claim 7, the rejection of Claim 5 is incorporated and further the combination of Liu, Deshpande, Lee, Chittigala, Serebrin and Hagita discloses: wherein after switching, by the processor, to the kernel mode from the user mode through the second privilege level switching, the method further comprises: writing, by the processor in the kernel mode, an end of interrupt (EOI) to the register of the interrupt controller, wherein the interrupt controller receives the EOI (see lines 11-20 of col. 7 from Serebrin; “receiving an End of Interrupt (EOI) indication from the user process indicating that the user process has finished processing the interrupt after delivering the interrupt as the second interrupt number. In some implementation, an APIC may include a special EOI instruction accessible by the user process. In some cases, the processor may generate an EOI for the user process to the APIC as part of delivering the interrupt”).
The combination of Liu, Deshpande, Lee, Chittigala, Serebrin and Hagita does not disclose: the EOI indicates the interrupt controller to unmask the interrupt request whose priority is the same as that of the user-mode interrupt request, or to mask the interrupt request whose priority is lower than that of the user-mode interrupt request.
However, Liang discloses: the interrupt completion signal indicates the interrupt controller to unmask the interrupt request whose priority is the same as that of the [user-mode] interrupt request, or to mask the interrupt request whose priority is lower than that of the [user-mode] interrupt request (see [0040]; “processor can be managed said interrupt request singal through IMR … The interrupt request that the disconnected source A of processor present is sent, this moment, interrupt source B sent new interrupt request singal, and interrupt source B and interrupt source A belong to that All factors being equal, preference will be give to grade; Then IMR shields the interrupt request singal that interrupt source B is sent; Up to handling the interrupt request singal that interrupt source A is sent, just remove shielding, the interrupt request singal that interrupt source B is sent sends to processor”. In response to completion of interrupt request from interrupt source A, the system unmasks or un-shields the interrupt request from interrupt source B has same priority as the interrupt source A).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the process of execution of interrupt request from the combination of Liu, Deshpande, Lee, Chittigala and Serebrin by including masking other interrupt requests during a current interrupt request is not completed from Liang, and thus the combination of Liu, Deshpande, Lee, Chittigala, Serebrin and Liang would disclose the missing limitations from the combination of Liu, Deshpande, Lee, Chittigala and Serebrin, since it would provide a mechanism of avoiding executing multiple interrupts concurrently (see [0040] from Liang).
Regarding to Claim 16, Claim 16 is a system claim corresponds to method Claim 7 and is rejected for the same reason set forth in the rejection of Claim 7 above.
Claims 9 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (CN107526622A-publication date: 12/29/2017-English translation provided by Google Patents, hereafter Liu) in view of Deshpande et al. (US 7870541 B1, hereafter Deshpande), Lee et al. (US 20090138625 A1, hereafter Lee), Chittigala (US 20090013145 A1), Serebrin et al. (US 10684970 B1, hereafter Serebrin) and Hagita (US 20080276027 A1) and further in view of Cockx et al. (US 6952825 B1, hereafter Cockx).
Regarding to Claim 9, the rejection of Claim 8 is incorporated and further the combination of Liu, Deshpande, Lee, Chittigala, Serebrin and Hagita discloses: and writing an end of interrupt (EOI) to the register of the interrupt controller (see lines 11-20 of col. 7 from Serebrin; “receiving an End of Interrupt (EOI) indication from the user process indicating that the user process has finished processing the interrupt after delivering the interrupt as the second interrupt number. In some implementation, an APIC may include a special EOI instruction accessible by the user process. In some cases, the processor may generate an EOI for the user process to the APIC as part of delivering the interrupt”).
Note: the current claim language is not explicitly written in a manner of the claimed writing EOI is performed in response to the condition of claimed “if the result status of the user-mode interrupt handler indicates that the user-mode interrupt handler does not end”, and thus the whole claim 9 can be interpreted as: in response of claimed condition of “if the result status of the user-mode interrupt handler indicates that the user-mode interrupt handler does not end”, performing claimed “disabling” limitation, and then performing the claimed “writing” limitation due to something else. In addition, current claim 9 is a method claim with conditional language, such claim can also be rejected under alternative condition, i.e., if the result status of the user-mode interrupt handler indicates that the user-mode interrupt handler ends.
The combination of Liu, Deshpande, Lee, Chittigala, Serebrin and Hagita does not disclose: if the result status of the user-mode interrupt handler indicates that the user-mode interrupt handler does not end, disabling, by the processor in the kernel mode, the user-mode interrupt request.
However, Cockx discloses: if the result status indicates that the interrupt handler does not end, disabling the executing interrupt request (see lines 58-7 of cols. 25-26; “An interrupt handler is a piece of code that is executed on a processor … Interrupts can selectively enable or disable other interrupts while running”. Certain interrupts are running, i.e., result status indicates the interrupt handler does not end, but the interrupt handler may disable the running interrupt due to some other interrupts).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the execution of user mode interrupts from the combination of Liu, Deshpande, Lee, Chittigala and Serebrin by including priority preemption policy to allow some interrupts preempt some other running interrupts from Cockx, and thus the combination of Liu, Deshpande, Lee, Chittigala, Serebrin and Cockx would disclose the missing limitations from the combination of Liu, Deshpande, Lee, Chittigala and Serebrin, since it would provide a mechanism of ensuring certain interrupts are able to be executed before some other interrupts even if such some other interrupts are currently running (see lines 58-7 of cols. 25-26 from Cockx).
Regarding to Claim 18, Claim 18 is a system claim corresponds to method Claim 9 and is rejected for the same reason set forth in the rejection of Claim 9 above.
Response to Arguments
Applicant’s arguments, filed 7/7/2026, with respect to rejections of claims 1-20 under 35 U.S.C. 103 have been full considered. New grounds of rejections are made based on the amended limitations from the independent claims. However, some of Applicant’s arguments are not persuasive. Such as, at pages 10-11 of the Remarks, Applicant argued that “Applicant respectfully submits that Liu merely refers to there being no need to save context when switching from user mode to kernel model. In contrast to the features of claim 1 as presently presented, Liu has not been shown to teach or suggest that the switching is performed through first privilege level switching” (see 1st paragraph of page 11 from the Remarks). In response to such argument, Applicant is suggested to review the corresponding descriptions of the reference carefully. Such as, [0014] from Liu not only discusses “switching from user mode to kernel model” but also discusses switching from kernel model to user mode (see “exiting from kernel mode to user mode” from [0014]). According to the context of [0014], the feature of “there is no need to save the context” is applied to both of “exiting from kernel mode to user mode” and “when switching from user mode to kernel mode” instead of “when switching from user mode to kernel mode” alone/only. In this way, reference Liu does teach the limitations of “switching, by the processor, to a user mode from the kernel mode through first privilege level switching”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ismael et al. (US 10592678 B1) discloses: an execution context 320 is illustratively a representation of a thread (associated with an operating system process) and, to that end, defines a state of the thread for execution on CPU 212. In an embodiment, the execution context may include inter alia (i) contents of CPU registers, (ii) pointers/values on a stack, (iii) a program counter (see lines 49-55 of col. 7).
Grisenthwaite et al. (US 20070266374 A1) discloses: when operating at the user level the user level stack pointer operates to indicate the memory address to which data values are to be pushed or from which data values are to be popped when a stack memory access is made (see [0004]).
Kawamoto (US 20110067034 A1) discloses: The pointer to context structure D14 is a pointer for identifying a context structure that is correlated with a thread. The pointer to context structure D14 is set when a context correlated with a thread is generated, and, as will be described later, is updated when switching between threads is performed without performing the context save/set process (see [0083]) and such context structure D14 includes program counter and stack pointer (see [0147] and [0223]).
Grocutt (US 20220366037 A1) discloses: the instruction which triggers a branch to a given target address could be any of a variety of instructions which cause the program counter register R15 to be modified to the branch target address. In some cases this may be a dedicated branch instruction, but it could also be a register move instruction which moves the branch target address into the program counter register (see [0198]).
Kleiman (US 5515538 A) discloses: by at least setting the kernel stack pointers to point to thread B's stack to permit Thread B to handle the interrupt without yet having to make a complete context switch (see lines 21-66 of col. 13).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHI CHEN whose telephone number is (571)272-0805. The examiner can normally be reached on M-F from 9:30AM to 5:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, April Y Blair can be reached on 571-270-1014. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Zhi Chen/
Patent Examiner, AU2196
/APRIL Y BLAIR/Supervisory Patent Examiner, Art Unit 2196
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