DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Otake et al (US 2009/0179227) in view of Kim (US 2021/0057599) and in further view of Noguchi et al (JP 2005056940).
Regarding Claim 1, Otake et al discloses a semiconductor device (a nitride semiconductor device [0056] Fig 1) comprising:
a substrate (may be a silicon substrate 1 [0057]);
a first gallium nitride layer (n-type GaN layer 3 [0059]) arranged on the substrate (1), the first gallium nitride layer (3) being a first conductivity type (n-type);
a gate electrode (gate electrode 13 [0071]) opposed to the first gallium nitride layer (3); and
a gate insulating layer (gate insulating film 12 [0070]) between the first gallium nitride layer (3) and the gate electrode (13).
Otake et al does not disclose
an amorphous glass substrate; and
an oriented insulating layer arranged on the amorphous glass substrate and having a crystal orientation.
Kim, in the related art of semiconductor devices that include transistors, discloses
a transistor (TFT photodetector 100 [0054] Fig 4) with an amorphous glass substrate (amorphous glass substrate [0054]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Otake et al to include an amorphous glass substrate as taught by Kim in order to allow for a transistor to have a display function and an image sensing function [0005]-[0006]. Further, a person of ordinary skill in the art would have recognized that having a amorphous glass substrate would be a simple substitution of one known element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate).
The combination of Otake et al and Kim does not disclose
an oriented insulating layer arranged on the amorphous glass substrate and having a crystal orientation; and
a first gallium nitride layer arranged on the oriented insulating layer and in contact with the oriented insulating layer, the first gallium nitride layer being a first conductivity type.
Noguchi et al, in the related art of semiconductor devices that include gallium nitride devices, discloses
an oriented insulating layer (adhesion film 12, which may be aluminum nitride [0048]-[0049] Fig 1) arranged on the amorphous glass substrate (substrate 11 may be amorphous glass [0034]) and having a crystal orientation ([0001] orientation [0053]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Otake et al and Kim to include and oriented insulating layer as taught by Noguchi et al in order to have improved crystallinity in the conductive layer above it [0038]. Further, a person of ordinary skill in the art would have recognized that having a conductive layer with improved crystallinity would be advantageous in improving the electrical functioning and reliability of the device (see MPEP 2143.I(D)).
The combination of Otake et al, Kim, and Noguchi et al now discloses
a first gallium nitride layer (3 Fig 1 Otake et al) arranged on the oriented insulating layer (12 Fig 1 Noguchi et al) and in contact with the oriented insulating layer (12 Fig 1 Noguchi et al), the first gallium nitride layer (3 Fig 1 Otake et al) being a first conductivity type (n-type [0059] Otake et al).
Regarding Claim 2, the combination of Otake et al, Kim, and Noguchi et al discloses the limitations of claim 1 as explained above. The combination of Otake et al, Kim, and Noguchi et al further discloses
wherein the oriented insulating layer (12 Fig 1 Noguchi et al) has a plane with 6-fold rotational symmetry (adhesion film 12, which may be aluminum nitride [0048]-[0049] Noguchi et al, which has a 6-fold rotational symmetry).
Regarding Claim 3, the combination of Otake et al, Kim, and Noguchi et al discloses the limitations of claim 2 as explained above. The combination of Otake et al, Kim, and Noguchi et al further discloses
wherein the oriented insulating layer has a (0001) plane ([0001] orientation [0053] Noguchi et al in a hexagonal close-packed structure [0053] Noguchi et al) in a hexagonal close-packed structure or a (111) plane in a face-centered cubic structure.
Regarding Claim 4, the combination of Otake et al, Kim, and Noguchi et al discloses the limitations of claim 1 as explained above. The combination of Otake et al, Kim, and Noguchi et al further discloses
wherein the oriented insulating layer (adhesion film 12, which may be aluminum nitride [0048]-[0049] Noguchi et al) includes aluminum nitride, gallium oxide, titanium nitride, or titanium oxide.
Regarding Claim 5, the combination of Otake et al, Kim, and Noguchi et al discloses the limitations of claim 1 as explained above. The combination of Otake et al, Kim, and Noguchi et al further discloses
wherein the gate electrode (gate electrode 13 [0071] Otake et al) is arranged on the first gallium nitride layer (n-type GaN layer 3 [0059] Otake et al).
Regarding Claim 6, the combination of Otake et al, Kim, and Noguchi et al discloses the limitations of claim 1 as explained above. The combination of Otake et al, Kim, and Noguchi et al further discloses
further comprising a second gallium nitride layer (p-type GaN layer 4 [0066] Fig 1 Otake et a) having higher conductivity ((p) is higher than (n-) of layer 7 of the first GaN layer 3, Otake et al) than the first gallium nitride layer (3 Fig 1 Otake et al),
the second gallium nitride layer (4) being a second conductivity type (p-type [0066] Otake et al),
wherein the second gallium nitride layer (4) is in contact with the first gallium nitride layer (3) from above the first gallium nitride layer (3).
Claims 10-12, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Otake et al (US 2009/0179227) in view of Kim (US 2021/0057599).
Regarding Claim 10, Otake et al discloses a semiconductor device (a nitride semiconductor device [0056] Fig 1) comprising:
a substrate (may be a silicon substrate 1 [0057]);
a gate electrode (gate electrode 13 [0071]) arranged on the substrate (1);
a gate insulating layer (gate insulating film 12 [0070]) arranged on the gate electrode (13) and having a crystal orientation (gate insulating film may be silicon nitride [0070] which has a c-axis orientation); and
a first gallium nitride layer (n-type GaN layer 3 [0059]) arranged on the gate insulating layer (12) and in contact with the gate insulating layer (12), the first gallium nitride layer (3) being a first conductivity type (n-type).
Otake et al does not disclose
an amorphous glass substrate;
a gate electrode arranged on the amorphous glass substrate.
Kim, in the related art of semiconductor devices that include transistors, discloses
a transistor (TFT photodetector 100 [0054] Fig 4) with an amorphous glass substrate (amorphous glass substrate [0054]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Otake et al to include an amorphous glass substrate as taught by Kim in order to allow for a transistor to have a display function and an image sensing function [0005]-[0006]. Further, a person of ordinary skill in the art would have recognized that having a amorphous glass substrate would be a simple substitution of one known element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate).
The combination of Otake et al and Kim now discloses
a gate electrode (13 Otake et al) arranged on the amorphous glass substrate (amorphous glass substrate [0054] Kim/ substrate 1 [0057] Otake et al).
Regarding Claim 11, the combination of Otake et al and Kim discloses the limitations of claim 10 as explained above. The combination of Otake et al and Kim further discloses
wherein the gate insulating layer (gate insulating film 12 which may be silicon nitride [0070] Otake et al) has a plane with 6-fold rotational symmetry (silicon nitride has a 6-fold symmetry).
Regarding Claim 12, the combination of Otake et al and Kim discloses the limitations of claim 11 as explained above. The combination of Otake et al and Kim further discloses
wherein the gate insulating layer (gate insulating film 12 which may be silicon nitride [0070] Otake et al) has a (0001) plane in a hexagonal close-packed structure (silicon nitride has a hexagonal close-packed structure) or a (111) plane in a face-centered cubic structure.
Regarding Claim 18, the combination of Otake et al and Kim discloses the limitations of claim 10 as explained above. The combination of Otake et al and Kim further discloses
further comprising a second gallium nitride layer (4 Fig 1 Otake et al) having higher conductivity ((p) is higher than (n-) of layer 7 of the first GaN layer 3, Otake et al) than the first gallium nitride layer (3 Fig 1 Otake et al), the second gallium nitride layer (4 Fig 1 Otake et al) being a second conductivity type (p-type [0066] Otake et al), and
wherein the gate insulating layer (12 Fig 1 Otake et al) is in contact with the first gallium nitride layer (3 Fig 1 Otake et al), and
the first gallium nitride layer (3 Fig 1 Otake et al) is in contact with the second gallium nitride layer (4 Fig 1 Otake et al) in a region overlapping the second gallium nitride layer (4 Fig 1 Otake et al) in a plan view (the examiner notes that since the first gallium nitride layer 3 is in contact with the second gallium nitride layer 4 in a region overlapping the second gallium nitride layer 4 in the cross section shown in Fig 1, and the same would apply in a plan view, so the limitation is still considered to be met by the prior art).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Otake et al (US 2009/0179227) in view of Kim (US 2021/0057599), and in further view of Hashimoto et al (US 7872285).
Regarding Claim 13, the combination of Otake et al and Kim discloses the limitations of claim 10 as explained above. The combination of Otake et al and Kim does not disclose
wherein the gate insulating layer includes aluminum nitride, gallium oxide, titanium nitride, or titanium oxide.
Hashimoto et al, in the related art of semiconductor devices that include gallium nitride devices, discloses
wherein the gate insulating layer (gate insulating film 59 [column 7, lines 1-20] Fig 5) includes aluminum nitride (may be aluminum nitride [column 7, lines 1-20]), gallium oxide, titanium nitride, or titanium oxide.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Otake et al and Kim to include wherein the gate insulating layer includes aluminum nitride as taught by Hashimoto et al in order to optimize the electron mobility in the gate of the transistor. Further, a person of ordinary skill in the art would have recognized that having a gate insulator that includes aluminum nitride would be a simple substitution of one known element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate).
Claims 14 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Otake et al (US 2009/0179227) in view of Kim (US 2021/0057599), and in further view of Noguchi et al (JP 2005056940).
Regarding Claim 14, the combination of Otake et al and Kim discloses the limitations of claim 10 as explained above. The combination of Otake et al and Kim does not disclose
further comprising an oriented insulating layer arranged between the amorphous glass substrate and the gate electrode, and having a crystal orientation, wherein the gate electrode and the gate insulating layer have the same crystal orientation as the oriented insulating layer.
Noguchi et al, in the related art of semiconductor devices that include gallium nitride devices, discloses
an oriented insulating layer (adhesion film 12, which may be aluminum nitride [0048]-[0049] Fig 1) arranged on the amorphous glass substrate (substrate 11 may be amorphous glass [0034]) and having a crystal orientation (0001 orientation [0053]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Otake et al and Kim to include and oriented insulating layer as taught by Noguchi et al in order to have improved crystallinity in the conductive layer above it [0038]. Further, a person of ordinary skill in the art would have recognized that having a conductive layer with improved crystallinity would be advantageous in improving the electrical functioning and reliability of the device (see MPEP 2143.I(D)).
The combination of Otake et al, Kim, and Noguchi et al now discloses
further comprising an oriented insulating layer (adhesion film 12, which may be aluminum nitride [0048]-[0049] Fig 1 Noguchi et al) arranged between the amorphous glass substrate (amorphous glass substrate [0054] Kim/ substrate 1 [0057] Otake et al) and the gate electrode (13 Otake et al), and having a crystal orientation (0001 orientation [0053] Noguchi et al), wherein the gate electrode (13 Otake et al) and the gate insulating layer (gate insulating film 12 [0070] Otake et al) have the same crystal orientation (gate insulating film 12 which may be silicon nitride [0070] Otake et al, which has a [0001] orientation and a hexagonal close-packed structure/( adhesion film 12, which may be aluminum nitride [0048]-[0049] Fig 1 Otake et al, has a [0001] orientation [0053] Noguchi et al in a hexagonal close-packed structure [0053] Noguchi et al) as the oriented insulating layer (12 Noguchi et al).
Regarding Claim 17, the combination of Otake et al and Kim discloses the limitations of claim 10 as explained above. The combination of Otake et al and Kim further discloses
further comprising a second gallium nitride layer (4 Fig 1 Otake et al) having higher conductivity ((p) is higher than (n-) of layer 7 of the first GaN layer 3, Otake et al) than the first gallium nitride layer (3 Fig 1 Otake et al), the second gallium nitride layer (4 Fig 1 Otake et al) being a second conductivity type (p-type [0066] Otake et al), and
wherein the second gallium nitride layer (4 Fig 1 Otake et al) is in contact with the first gallium nitride layer (3 Fig 1 Otake et al) from above the first gallium nitride layer (3 Fig 1 Otake et al).
The combination of Otake et al and Kim does not disclose
an oriented insulating layer having a crystal orientation in contact with the first gallium nitride layer between the amorphous glass substrate and the first gallium nitride layer in a region overlapping the second gallium nitride layer in a plan view.
Noguchi et al (JP 2005056940) discloses
an oriented insulating layer (adhesion film 12, which may be aluminum nitride [0048]-[0049] Fig 1) arranged on the amorphous glass substrate (substrate 11 may be amorphous glass [0034]) and having a crystal orientation ([0001] orientation [0053]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Otake et al and Kim to include and oriented insulating layer as taught by Noguchi et al in order to have improved crystallinity in the conductive layer above it [0038]. Further, a person of ordinary skill in the art would have recognized that having a conductive layer with improved crystallinity would be advantageous in improving the electrical functioning and reliability of the device (see MPEP 2143.I(D)).
The combination of Otake et al, Kim, and Noguchi et al now discloses
an oriented insulating layer (12 Fig 1 Noguchi et al) having a crystal orientation in contact with the first gallium nitride layer (3 Fig 1 Otake et al) between the amorphous glass substrate (amorphous glass substrate [0054] Kim/ substrate 1 [0057] Otake et al) and the first gallium nitride layer (3 Fig 1 Otake et al) in a region overlapping the second gallium nitride layer (4 Fig 1 Otake et al) in a plan view (the examiner notes that since the oriented insulating layer is in contact with the first gallium nitride layer (3) in a region overlapping the second gallium nitride layer (4) in the cross section shown in Fig 1 Otake et al, and the same would apply in a plan view, so the limitation is still considered to be met by the prior art).
Allowable Subject Matter
Claims 7-9, 15-16, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 7:
Regarding Claim 7, the combination of Otake et al, Kim, and Noguchi et al discloses the limitations of claim 1 as explained above. The combination of Otake et al, Kim, and Noguchi et al further discloses
further comprising a second gallium nitride layer (4 Fig 1 Otake et al) having higher conductivity ((p) is higher than (n-) of layer 7 of the first GaN layer 3, Otake et al) than the first gallium nitride layer (3 Fig 1 Otake et al), the second gallium nitride layer (4 Fig 1 Otake et al) being a second conductivity type (p-type [0066] Otake et al), and
the first gallium nitride layer (3 Fig 1 Otake et al) is in contact with the oriented insulating layer (adhesion film 12, which may be aluminum nitride [0048]-[0049] Fig 1 Noguchi et al) exposed (shown in annotated Fig 1 Otake et al) from the second gallium nitride layer (4 Otake et al) in a second region (shown in annotated Fig 1 Otake et al) different from the first region (shown in annotated Fig 1 Otake et al).
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The reason for the indication of allowability of Claim 7 is the inclusion of
wherein the first gallium nitride layer is in contact with the second gallium nitride layer from above the second gallium nitride layer in a first region.
Specifically, as shown above in annotated Fig 1 Otake et al, there is no portion of n-type layer 3 above the p-type layer 4 in any region to meet the limitation of being in contact with from above (the examiner notes that the n+sup GaN layer 5 Otake et al cannot be used as the first GaN layer to meet the limitation due to the incorporation of the oriented insulating layer 12 from Noguchi et al), and in the event that another reference that discloses this limitation were to be found, it would not be obvious to a person of ordinary skill in the art to make this alteration to the combination of Otake et al, Kim, and Noguchi et al.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Claim 8:
Claim 8 would be allowable based on its dependency on Claim 7.
Claim 9:
Regarding Claim 9, the combination of Otake et al, Kim, and Noguchi et al discloses the limitations of claim 1 as explained above. The combination of Otake et al, Kim, and Noguchi further discloses
further comprising a second gallium nitride layer (4 Fig 1 Otake et al) having higher conductivity ((p) is higher than (n-) of layer 7 of the first GaN layer 3, Otake et al) than the first gallium nitride layer (3 Fig 1 Otake et al), the second gallium nitride layer (4 Fig 1 Otake et al) being a second conductivity type (p-type [0066] Otake et al), and
wherein the gate insulating layer (gate insulating film 12 [0070] Fig 1 Otake et al) is in contact with the first gallium nitride layer (3 Fig 1 Otake et al) from above the first gallium nitride layer (3 Fig 1 Otake et al).
The reason for the indication of allowability of Claim 9 is the inclusion of
a part of the second gallium nitride layer is in contact with the gate insulating layer from above the gate insulating layer.
Specifically, there is no portion of the p-type layer 4 in any region that is above the gate insulating layer (12 Fig 1 Otake et al) is the instant application has intended, and in the event that another reference that discloses this limitation were to be found, it would not be obvious to a person of ordinary skill in the art to make this alteration to the combination of Otake et al, Kim, and Noguchi et al.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Claim 15:
Regarding Claim 15, the combination of Otake et al, Kim, and Noguchi et al discloses the limitations of claim 14 as explained above. The combination of Otake et al, Kim, and Noguchi et al further discloses
further comprising a second gallium nitride layer (p-type GaN layer 4 [0066] Fig 1 Otake et a) having higher conductivity ((p) is higher than (n-) of layer 7 of the first GaN layer 3, Otake et al) than the first gallium nitride layer (3 Fig 1 Otake et al),
the second gallium nitride layer (4) being a second conductivity type (p-type [0066] Otake et al).
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The reason for the indication of allowability of Claim 15 is the inclusion of
wherein the second gallium nitride layer is in contact with the oriented insulating layer from above the oriented insulating layer and is in contact with the first gallium nitride layer from below the first gallium nitride layer.
Specifically, as shown above in annotated Fig 1 Otake et al, there is no portion of the p-type layer 4 in physical or direct contact with the oriented insulating layer (12 Noguchi et al) in the location incorporated from the Noguchi et al reference, and does not correspond from above (the examiner notes that although they could be considered to still be in electrical contact with each other in the broadest sense, it does not appear to be reasonable in light of the specification and drawings of the instant application), and in the event that another reference that discloses this limitation were to be found, it would not be obvious to a person of ordinary skill in the art to make this alteration to the combination of Otake et al, Kim, and Noguchi et al.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Claim 16:
Regarding Claim 16, the combination of Otake et al and Kim discloses the limitations of claim 10 as explained above. The combination of Otake et al and Kim further discloses
further comprising a second gallium nitride layer (4 Fig 1 Otake et al) having higher conductivity ((p) is higher than (n-) of layer 7 of the first GaN layer 3, Otake et al) than the first gallium nitride layer (3 Fig 1 Otake et al), the second gallium nitride layer (4 Fig 1 Otake et al) being a second conductivity type (p-type [0066] Otake et al).
Noguchi et al (JP 2005056940) discloses
an oriented insulating layer (adhesion film 12, which may be aluminum nitride [0048]-[0049] Fig 1) arranged on the amorphous glass substrate (substrate 11 may be amorphous glass [0034]) and having a crystal orientation ([0001] orientation [0053]).
The reason for the indication of allowability of Claim 16 is the inclusion of
the oriented insulating layer being in contact with the second gallium nitride layer, wherein the gate electrode has a crystal orientation and is in contact with the gate insulating layer, and the second gallium nitride layer is in contact with the first gallium nitride layer from below the first gallium nitride layer.
Specifically the oriented insulating layer as incorporated above could not be in physical contact with the second gallium nitride layer (the examiner notes that although they could be considered to still be in electrical contact with each other in the broadest sense, it does not appear to be reasonable in light of the specification and drawings of the instant application), and in the event that another reference that discloses this limitation were to be found, it would not be obvious to a person of ordinary skill in the art to make this alteration to the combination of Otake et al and Kim.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Claim 19:
Regarding Claim 19, the combination of Otake et al and Kim discloses the limitations of claim 10 as explained above. The combination of Otake et al and Kim further discloses
further comprising a second gallium nitride layer (4 Fig 1 Otake et al) having higher conductivity ((p) is higher than (n-) of layer 7 of the first GaN layer 3, Otake et al) than the first gallium nitride layer (3 Fig 1 Otake et al), the second gallium nitride layer (4 Fig 1 Otake et al) being a second conductivity type (p-type [0066] Otake et al), and
wherein the second gallium nitride layer (4 Fig 1 Otake et al) is in contact with the gate insulating layer (12 Fig 1 Otake et al) in an arbitrary first direction on a main surface of the amorphous glass substrate (amorphous glass substrate [0054] Kim/ substrate 1 [0057] Otake et al).
The reason for the indication of allowability of Claim 19 is the inclusion of
wherein the second gallium nitride layer is in contact with the gate insulating layer at a position adjacent to the first gallium nitride layer.
Specifically, there is no portion of the second GaN layer 4 (p-type) that is considered to be adjacent to the first GaN layer 3 (n-type) since the entirety of the p-type layer 4 is above the n-type layer and not adjacent to it on the same level, and in the event that another reference that discloses this limitation were to be found, it would not be obvious to a person of ordinary skill in the art to make this alteration to the combination of Otake et al and Kim.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Azize et al (US 2020/0075664) which discloses MESFET devices [0032], and et al (US 2016/0079370) which discloses a light emitting diode and a HEMT device [0018].
Conclusion
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/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812