DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendments filed on 6/8/2026 have been entered.
Response to Arguments
Applicant’s arguments filed on 6/8/2026 regarding Claims 1-20 have been fully considered but are not persuasive.
Regarding Claim 1, Applicant argues that the prior art reference Kuang et al does not disclose wherein the first gate capping pattern (22 Fig 17B) overlaps the second gate capping pattern (82 Fig 17B) in the second direction (y-direction). The examiner disagrees in that in the broadest reasonable interpretation, overlap would mean sharing the same space along the coordinates of the claimed direction. This interpretation is shown in annotated Fig 17B of Kuang et al, which still appears to read on Claim 1.
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Therefore, the prior art rejections of Claims 1-2, 4-6, and 8-12 will be maintained.
In the interest of compact prosecution, the examiner notes that further description of overlap such as “at least partially overlap in the third direction” etc. as shown in annotated Fig 3 of the instant application would be helpful in overcoming the prior art of record.
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The examiner is available for an interview at Applicant’s convenience.
Regarding Claims 13 and 20, Applicant argues the gate spacer 46g and first gate capping pattern 22 overlap each other in the z direction in Fig 17B of Kuang et al. The examiner notes that this argument appears to be persuasive, therefore the prior art rejections of Claims 13-20 have been withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-6, and 9-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kuang et al (US 2022/0278196).
Regarding Claim 1, Kuang et al discloses a semiconductor device (semiconductor device [0010]) comprising:
a substrate (substrate 10 [0010] Fig 17A-C);
an active pattern (shown in annotated Fig 17C) comprising: a lower pattern (shown in annotated Fig 17C) extending in a first direction (x direction 17C) that intersects a second direction (y direction 17B); and
a plurality of sheet patterns (first channel layers 15 of nanosheet stack 17 [0012] Fig 17C) above the uppermost surface of the lower pattern (shown in annotated Fig 17C) and spaced apart from the lower pattern (shown in annotated Fig 17C) in a third direction (z direction 17C) substantially perpendicular to the first direction (x direction 17C) and the second direction (y direction Fig 17B);
a gate structure (gate dielectric layer 72 and gate electrode 74 [0077] Fig 17C) on the lower pattern (shown in annotated Fig 17C) and comprising a gate electrode (gate electrode 74 Fig 17C) and a gate insulating film (gate dielectric 72 [0077] Fig 17C), the gate electrode (74 Fig 17C) and the gate insulating film (72 Fig 17C) at least partially surrounding the plurality of sheet patterns (15 Fig 17C);
a first gate capping pattern (hard mask layer 22 [0057] Fig 17C) on the gate structure (72, 74 Fig 17C) and above the plurality of sheet patterns (15 Fig 17C) in the third direction (z direction 17B);
a gate spacer (gate sidewall spacer 46g [0041] and inner air spacers 78 [0072] Fig 17C) extending along a side wall of the gate structure (72, 74 Fig 17C);
a second gate capping pattern (metal gate liner 82 [0078] Fig 17C) extending along an uppermost surface of the gate structure (72, 74 Fig 17C) and an uppermost surface of the first gate capping pattern (22 Fig 17C);
a source/drain pattern (source/drain 56 [0050] Fig 17C) on at least one side of the gate structure (72, 74 Fig 17C); and
an etching stop film (CESL 66 [0060] Fig 17C) on the source/drain pattern (56 Fig 17C) and a first side wall of the first gate capping pattern (22 Fig 17C),
wherein the second gate capping pattern (82 Fig 17C) at least partially covers the uppermost surface of the gate spacer (46g and 78 Fig 17C), and
wherein, from the lower pattern (shown in annotated Fig 17C), the uppermost surface of the first gate capping pattern (22 Fig 17C) is higher than the uppermost surface of the gate structure (72, 74 Fig 17C),
wherein the first gate capping pattern (22 Fig 17C) overlaps (shown in annotated Fig 17B) the second gate capping pattern (82 Fig 17C) in the second direction (y direction Fig 17B).
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Regarding Claim 2, Kuang et al discloses the limitations of claim 1 as explained above. Kuang et al further discloses
further comprising: a field insulating film (isolation layer 26 [0031] Fig 5 and Fig 17B) at least partially covering the side wall of the lower pattern (shown above in annotated Fig 17C), wherein the first gate capping pattern (22 Fig 17B-C) does not overlap (shown in annotated Fig 17B) the field insulating film (26 Fig 5 and Fig 17B) in the third direction (z direction Fig 17B).
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Regarding Claim 4, Kuang et al discloses the limitations of claim 1 as explained above. Kuang et al further discloses
wherein the side wall of the second gate capping pattern (82 Fig 17C) contacts (shown in Fig 17C) the etching stop film (66 Fig 17C).
Regarding Claim 5, Kuang et al discloses the limitations of claim 1 as explained above. Kuang et al further discloses
wherein the first gate capping pattern (22 Fig 17B-C) does not overlap (shown in annotated Fig 17B) the gate spacer (46g and 78 Fig 17B-C) in the second direction (y direction Fig 17B).
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Regarding Claim 6, Kuang et al discloses the limitations of claim 1 as explained above. Kuang et al further discloses
wherein, in the third direction (z direction) and from the uppermost surface of the lower pattern (shown in annotated Fig 17C), a height of the uppermost surface of the gate structure (72, 74 Fig 17C) is different from a height of an uppermost surface of the source/drain pattern (56 Fig 17C).
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Regarding Claim 9, Kuang et al discloses the limitations of claim 1 as explained above. Kuang et al further discloses
further comprising an inner spacer (46g and 78 Fig 17C) between the gate structure (72, 74 Fig 17C) and the source/drain pattern (56 Fig 17C), wherein the gate structure (72, 74 Fig 17C) comprises a plurality of inter-gate structures (72, 74 Fig 17C) between the lower pattern (shown above in annotated Fig 17C) and the plurality of sheet patterns (15 Fig 17C), and between adjacent sheet patterns (15 Fig 17C) of the plurality of sheet patterns (15 Fig 17C), and wherein the plurality of inter-gate structures (72, 74 Fig 17C) contacts the inner spacer (46g and 78 Fig 17C).
Regarding Claim 10, Kuang et al discloses the limitations of claim 1 as explained above. Kuang et al further discloses
further comprising a source/drain contact (conductive features 94 [0084] Fig 17C) on the source/drain pattern (56 Fig 17C) and connected to the source/drain pattern (56 Fig 17C), wherein, in the third direction (z direction) from the lower pattern (shown above in annotated Fig 17C), an uppermost surface of the source/drain contact (94 Fig 17C) is higher than the uppermost surface of the first gate capping pattern (22 Fig 17C).
Regarding Claim 11, Kuang et al discloses the limitations of claim 1 as explained above. Kuang et al further discloses
wherein the first gate capping pattern (22 Fig 17C) comprises second side walls (left and right shown in annotated Fig 17B), opposite to each other in the second direction (y direction Fig 17B) intersecting the first direction (x direction Fig 17C), and wherein the second side walls (left and right shown in annotated Fig 17B) contact the second gate capping pattern (82 Fig 17C).
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Regarding Claim 12, Kuang et al discloses the limitations of claim 1 as explained above. Kuang et al further discloses
wherein, in the third direction (z direction), the uppermost surface of the first gate capping pattern (22 Fig 17C) is on a first plane (shown in Fig 17C) that is different from a second plane (shown in Fig 17C) of an upper surface of the etching stop film (66 Fig 17C).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kuang et al (US 2022/0278196) in view of Noh et al (US 2020/0091152).
Regarding Claim 8, Kuang et al discloses the limitations of claim 1 as explained above. Kuang et al further discloses
wherein the gate structure (72, 74 Fig 17C) comprises a plurality of inter-gate structures (72, 74 Fig 17C) between the lower pattern (shown above in annotated Fig 17C) and the plurality of sheet patterns (15 Fig 17C), and between adjacent sheet patterns (15 Fig 17C) of the plurality of sheet patterns (15 Fig 17C).
Kuang et al does not dislcose
wherein the source/drain pattern contacts each of the plurality of inter-gate structures.
Noh et al, in the related art of semiconductor devices that include multi-gate transistors, multi-bride channel elements, and nano-sheets discloses
wherein the source/drain pattern (source/drain region 152 of third gate structures G3 [0027] Fig 5) contacts each of the plurality of inter-gate structures (first, second and third wire patterns 141, 142, 143 of the third gate structures G3 [0022] Fig 5).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Kuang et al to include wherein the source/drain pattern contacts each of the plurality of inter-gate structures as taught by Noh in order to have a device wherein the current control capability my be improved without increasing a gate length of the multi-gate transistors [0003]. Further, a person of ordinary skill in the art would have recognized that having the source/drain patterns each contact the inter-gate structures would be advantageous in optimizing the electrical functioning of the device (see MPEP 2143.I(D)).
Allowable Subject Matter
Claims 13-19 are allowable.
Regarding Claim 13, Kuang et al (US 2022/0278196) discloses a semiconductor device (semiconductor device [0010]) comprising:
a substrate (substrate 10 [0010] Fig 17A-C);
an active pattern (shown in annotated Fig 17C) comprising: a lower pattern (shown in annotated Fig 17C) extending in a first direction (x direction Fig 17C) that intersects a second direction (y direction Fig 17B); and
a plurality of sheet patterns (first channel layers 15 of nanosheet stack 17 [0012] Fig 17C) above an uppermost surface of the lower pattern (shown in annotated Fig 17C) and spaced apart from the lower pattern (shown in annotated Fig 17C) in a third direction (z direction 17B-C) substantially perpendicular to the first direction (x direction Fig 17C) and the second direction (y direction Fig 17B);
a gate structure (gate dielectric layer 72 and gate electrode 74 [0077] Fig 17C) on the lower pattern (shown in annotated Fig 17C) and comprising a gate electrode (gate electrode 74 Fig 17C) and a gate insulating film (gate dielectric layer 72 Fig 17C), the gate electrode (74 Fig 17C) and the gate insulating film (72 Fig 17C) at least partially surrounding the plurality of sheet patterns (15 Fig 17C);
a first gate capping pattern (hard mask layer 22 [0057] Fig 17C) on the gate structure (72, 74 Fig 17C) and above the plurality of sheet patterns (15 Fig 17C) in the third direction (z direction Fig 17B-C);
a gate spacer (gate sidewall spacer 46g [0041] and inner air spacer 78 [0072] Fig 17C) extending along a side wall of the gate structure (72, 74 Fig 17C);
a second gate capping pattern (metal gate liner 82 [0078] Fig 17C) extending along an uppermost surface of the gate structure (72, 74 Fig 17C) and an uppermost surface of the first gate capping pattern (22 Fig 17C) in the third direction (z direction Fig 17B);
a source/drain pattern (source/drain 56 [0050] Fig 17C) on at least one side of the gate structure (72, 74 Fig 17C); and
an etching stop film (CESL 66 [0060] Fig 17C) on the source/drain pattern (56 Fig 17C) and a side wall of the first gate capping pattern (22 Fig 17C), wherein the gate structure (72, 74 Fig 17C) comprises a plurality of inter-gate structures (72, 74 Fig 17C) between the lower pattern (shown in annotated Fig 17C) and the plurality of sheet patterns (15 Fig 17C), and between adjacent sheet patterns (15 Fig 17C) of the plurality of sheet patterns (17C),
and wherein, from the lower pattern (shown in annotated Fig 17C), the uppermost surface of the first gate capping pattern (22 Fig 17C) is higher than the uppermost surface of the gate structure (72, 74 Fig 17C).
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The reason for the indication of allowability of Claim 13 is the inclusion of
wherein the first gate capping pattern does not overlap the gate spacer in the third direction.
Specifically, the prior art reference Kuang et al discloses the gate spacer (46g and 78 Fig 17B) at least partially overlaps the first gate capping pattern (22 Fig 17B-C) along the z-direction as shown in annotated Fig 17B, which does not appear to meet this limitation. Further, should another reference be found that discloses this claim limitation, it would not be obvious to a person of ordinary skill in the art to combine the references and make this alteration to Kuang et al.
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It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Claim 20 is allowable.
Regarding Claim 20, Kuang et al (US 2022/0278196) discloses a semiconductor device (semiconductor device [0010]) comprising:
a substrate (substrate 10 [0010] Fig 17A-C);
an active pattern (shown in annotated Fig 17C) comprising: a lower pattern (shown in annotated Fig 17C) extending in a first direction (x direction Fig 17C) intersecting a second direction (y direction Fig 17B); and
a plurality of sheet patterns (first channel layers 15 of nanosheet stack 17 [0012] Fig 17C) above an upper surface of the lower pattern (shown in annotated Fig 17C) and spaced apart from the lower pattern (shown in annotated Fig 17C) in a third direction (z direction Fig 17B-C) substantially perpendicular to the first direction (x direction Fig 17C) and the second direction (y direction Fig 17B);
a field insulating film (isolation layer 26 [0031] Fig 5 and Fig 17B) at least partially covering (shown in annotated Fig 5) a side wall of the lower pattern (shown in annotated Fig 17C);
a gate structure (gate dielectric layer 72 and gate electrode 74 [0077] Fig 17C) on the lower pattern (shown in annotated Fig 17C) and the field insulating film (26 Fig 5 and Fig 17C), extending in a second direction (y direction Fig 17B), and comprising a gate electrode (gate electrode 74 Fig 17C) and a gate insulating film (gate dielectric layer 72 Fig 17C), the gate electrode (74 Fig 17C) and the gate insulating film (72 Fig 17C) at least partially surrounding the plurality of sheet patterns (15 Fig 17C);
a first gate capping pattern (hard mask layer 22 [0057] Fig 17C) on the gate structure (72, 74 Fig 17C) and above the plurality of sheet patterns (15 Fig 17C) in the third direction (z direction Fig 17B-C);
a gate spacer (gate sidewall spacer 46g [0041] Fig 17C) extending along a side wall of the gate structure (72, 74 Fig 17C) in the second direction (y direction Fig 17B);
a second gate capping pattern (metal gate liner 82 [0078] Fig 17C) extending along an uppermost surface of the gate structure (72, 74 Fig 17C) and an uppermost surface of the first gate capping pattern (22 Fig 17C);
a gate contact (gate contact 96 [0084] Fig 17B-C) penetrating (shown in Fig 17B) the first gate capping pattern (22 Fig 17B-C) and the second gate capping pattern (82 Fig 17B-C) on the gate electrode (74 Fig B-C), the gate contact (96 Fig 17B-C) being connected to the gate electrode (74 Fig 17B-C);
a source/drain pattern (source/drain 56 [0050] Fig 17C) on at least one side of the gate structure (72, 74 Fig 17C);
an etching stop film (CESL 66 [0060] Fig 17C) on the source/drain pattern (56 Fig 17C) and a side wall of the first gate capping pattern (22 Fig 17C); and
a source/drain contact (conductive features 94 [0084] Fig 17C) on the source/drain pattern (56 Fig 17C) and connected to the source/drain pattern (56 Fig 17C),
wherein a second gate capping pattern (82 Fig 17C) at least partially covers an upper surface of the gate spacer (46g Fig 17C),
wherein a side wall of the second gate capping pattern (82 Fig 17C) contacts the etching stop film (66 Fig 17C), and
wherein, in the third direction (z direction Fig 17B-C) and from the lower pattern (shown in annotated Fig 17C), the uppermost surface of the first gate capping pattern (22 Fig 17C) is higher than the uppermost surface of the gate structure (72, 74 Fig 17C).
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The reason for the indication of allowability of Claim 20 is the inclusion of
wherein the first gate capping pattern does not overlap the first insulating film in the third direction.
Specifically, the prior art reference Kuang et al discloses the gate spacer (46g and 78 Fig 17B) at least partially overlaps the first gate capping pattern (22 Fig 17B-C) along the z-direction as shown in annotated Fig 17B, which does not appear to meet this limitation. Further, should another reference be found that discloses this claim limitation, it would not be obvious to a person of ordinary skill in the art to combine the references and make this alteration to Kuang et al.
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It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Claims 3 and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 3:
Regarding Claim 3, Kuang et al (US 2022/0278196) discloses the limitations of claim 2 as explained above. Kuang et al (US 2022/0278196) further discloses
wherein a first height from the uppermost surface of the lower pattern (shown above in annotated Fig 17C) to the uppermost surface of the gate structure (72, 74 Fig 17C) at a portion in which the gate structure (72, 74 Fig 17C) is positioned above at least one sheet pattern (15 Fig 17C) of the plurality of sheet patterns (15 Fig 17C) is substantially the same as a second height from the uppermost surface of the lower pattern (shown above in annotated Fig 17C) to the uppermost surface of the gate structure (72, 74 Fig 17C) at a portion in which the gate structure (72, 74 Fig 17C) is positioned above the field insulating film (26 Fig 17B).
The reason for the indication of allowability of Claim 3 is the inclusion of
wherein a first height from the uppermost surface of the lower pattern to the uppermost surface of the gate structure at a portion in which the gate structure is positioned above at least one sheet pattern of the plurality of sheet patterns is greater than a second height from the uppermost surface of the lower pattern to the uppermost surface of the gate structure at a portion in which the gate structure is positioned above the field insulating film.
Specifically, the prior art reference Kuang et al discloses that the first height appears to be the same as the second height, which does not appear to meet this claim limitation. Further, should another reference be found that discloses this feature, it would not be obvious to a person of ordinary skill in the art to combine the references to alter Kuang et al to meet this requirement.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Claim 7:
Regarding Claim 7, Kuang et al (US 2022/0278196) discloses the limitations of claim 1 as explained above. Kuang et al (US 2022/0278196) further discloses
Wherein an upper surface of the substrate (10 Fig 17A-C), a height of the upper surface of the gate structure (72, 74 Fig 17C) is equal (shown in annotated Fig 17C) to or greater than a height of the upper surface of the gate spacer (46g and 78 Fig 17C).
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The reason for the indication of allowability of Claim 7 is the inclusion of
wherein, in the third direction and from an uppermost surface of the substrate, a height of the uppermost surface of the gate structure is equal to or greater than a height of the uppermost surface of the gate spacer.
Specifically, it can be observed in Fig 17C of the prior art reference Kuang et al that the uppermost surface of the gate structure (72 and 74 Fig 17C) is less than the uppermost surface of the gate spacer (46g and 78 Fig 17C). Although this limitation may be interpreted to be met by Kuang et al when including the claim language “an upper surface”, when the claim language “uppermost surface” is applied, Kuang et al does not appear to disclose this feature since it appears to be the opposite type of arrangement than the amended claim language suggests. Further, should another reference be found that discloses this limitation, it would not be obvious to a person of ordinary skill in the art to combine the references and alter Kuang et al to include this feature.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Choe et al (US 2010/0237401) which discloses gate structures in a semiconductor device [0008], and Haran et al (US 2019/0267371) which discloses FinFET devices [0013].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID PAUL SEDOROOK whose telephone number is (571)272-4158. The examiner can normally be reached Monday - Friday 7:30 am -5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached on (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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