DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: A Semiconductor Device Comprising a First Gate Capping Pattern and A Second Gate Capping Pattern.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 11 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 11, the claim language requires “the first gate capping pattern comprises second side walls opposite each other in a third direction intersecting the first direction, and where in the second sidewalls contact the second gate capping pattern.” However, the first gate capping pattern is labeled 125 in the specification and has sidewalls opposite each other in the first direction D1 (as shown in Fig 2) and sidewalls opposite each other in the second direction D2 (as shown in Fig 3), but the figures do not show any sidewalls that are opposite each other in the third direction D3 (which appears to be the vertical z direction), so it is unclear what applicant is intending as the second sidewalls opposite each other in the third direction D3, since the second direction is D2 and the first direction is D1.
For the purposes of compact prosecution, the examiner notes that the sidewalls will be interpreted as the top and bottom of the first gate capping layer which would be opposite each other in the third direction D3 as indicated in the instant application.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, 9-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kuang et al (US 2022/0278196).
Regarding Claim 1, Kuang et al discloses a semiconductor device (semiconductor device [0010]) comprising:
a substrate (substrate 10 [0010] Fig 17A-C);
an active pattern (shown in annotated Fig 17C) comprising: a lower pattern (shown in annotated Fig 17C) extending in a first direction (x direction 17C); and
a plurality of sheet patterns (first channel layers 15 of nanosheet stack 17 [0012] Fig 17C) above an upper surface of the lower pattern (shown in annotated Fig 17C) and spaced apart from the lower pattern (shown in annotated Fig 17C) in a second direction (y direction 17B) substantially perpendicular to the first direction (x direction 17C);
a gate structure (gate dielectric layer 72 and gate electrode 74 [0077] Fig 17C) on the lower pattern (shown in annotated Fig 17C) and comprising a gate electrode (gate electrode 74 Fig 17C) and a gate insulating film (gate dielectric 72 [0077] Fig 17C), the gate electrode (74 Fig 17C) and the gate insulating film (72 Fig 17C) at least partially surrounding the plurality of sheet patterns (15 Fig 17C);
a first gate capping pattern (hard mask layer 22 [0057] Fig 17C) on the gate structure (72, 74 Fig 17C) and above the plurality of sheet patterns (15 Fig 17C) in the second direction (y direction 17B);
a gate spacer (gate sidewall spacer 46g [0041] Fig 17C) extending along a side wall of the gate structure (72, 74 Fig 17C);
a second gate capping pattern (metal gate liner 82 [0078] Fig 17C) extending along an upper surface of the gate structure (72, 74 Fig 17C) and an upper surface of the first gate capping pattern (22 Fig 17C);
a source/drain pattern (source/drain 56 [0050] Fig 17C) on at least one side of the gate structure (72, 74 Fig 17C); and
an etching stop film (CESL 66 [0060] Fig 17C) on the source/drain pattern (56 Fig 17C) and a first side wall of the first gate capping pattern (22 Fig 17C),
wherein the second gate capping pattern (82 Fig 17C) at least partially covers an upper surface of the gate spacer (46g Fig 17C), and
wherein, from the lower pattern (shown in annotated Fig 17C), the upper surface of the first gate capping pattern (22 Fig 17C) is higher than the upper surface of the gate structure (72, 74 Fig 17C).
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Regarding Claim 2, Kuang et al discloses the limitations of claim 1 as explained above. Kuang et al further discloses
further comprising: a field insulating film (isolation layer 26 [0031] Fig 5 and Fig 17B) at least partially covering the side wall of the lower pattern (shown above in annotated Fig 17C), wherein the first gate capping pattern (22 Fig 17B-C) does not overlap (shown in annotated Fig 17B) the field insulating film (26 Fig 5 and Fig 17B) in the second direction (y direction Fig 17B).
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Regarding Claim 3, Kuang et al discloses the limitations of claim 2 as explained above. Kuang et al further discloses
wherein a first height from the upper surface of the lower pattern (shown above in annotated Fig 17C) to the upper surface of the gate structure (72, 74 Fig 17C) at a portion in which the gate structure (72, 74 Fig 17C) is positioned above at least one sheet pattern (15 Fig 17C) of the plurality of sheet patterns (15 Fig 17C) is greater than a second height from the upper surface of the lower pattern (shown above in annotated Fig 17C) to the upper surface of the gate structure (72, 74 Fig 17C) at a portion in which the gate structure (72, 74 Fig 17C) is positioned above the field insulating film (26 Fig 17B).
Regarding Claim 4, Kuang et al discloses the limitations of claim 1 as explained above. Kuang et al further discloses
wherein the side wall of the second gate capping pattern (82 Fig 17C) contacts (shown in Fig 17C) the etching stop film (66 Fig 17C).
Regarding Claim 5, Kuang et al discloses the limitations of claim 1 as explained above. Kuang et al further discloses
wherein the first gate capping pattern (22 Fig 17B-C) does not overlap (shown in annotated Fig 17B) the gate spacer (46g Fig 17B-C) in the second direction (y direction Fig 17B).
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Regarding Claim 6, Kuang et al discloses the limitations of claim 1 as explained above. Kuang et al further discloses
wherein, from the upper surface of the lower pattern (shown above in annotated Fig 17C), a height of the upper surface of the gate structure (72, 74 Fig 17C) is different from a height of an upper surface of the source/drain pattern (56 Fig 17C).
Regarding Claim 7, Kuang et al discloses the limitations of claim 1 as explained above. Kuang et al further discloses
wherein, from an upper surface of the substrate (10 Fig 17A-C), a height of the upper surface of the gate structure (72, 74 Fig 17C) is equal (shown in annotated Fig 17C) to or greater than a height of the upper surface of the gate spacer (46g Fig 17C).
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Regarding Claim 9, Kuang et al discloses the limitations of claim 1 as explained above. Kuang et al further discloses
further comprising an inner spacer (46g Fig 17C) between the gate structure (72, 74 Fig 17C) and the source/drain pattern (56 Fig 17C), wherein the gate structure (72, 74 Fig 17C) comprises a plurality of inter-gate structures (72, 74 Fig 17C) between the lower pattern (shown above in annotated Fig 17C) and the plurality of sheet patterns (15 Fig 17C), and between adjacent sheet patterns (15 Fig 17C) of the plurality of sheet patterns (15 Fig 17C), and wherein the plurality of inter-gate structures (72, 74 Fig 17C) contacts the inner spacer (46g Fig 17C).
Regarding Claim 10, Kuang et al discloses the limitations of claim 1 as explained above. Kuang et al further discloses
further comprising a source/drain contact (conductive features 94 [0084] Fig 17C) on the source/drain pattern (56 Fig 17C) and connected to the source/drain pattern (56 Fig 17C), wherein, from the lower pattern (shown above in annotated Fig 17C), an upper surface of the source/drain contact (94 Fig 17C) is higher than the upper surface of the first gate capping pattern (22 Fig 17C).
Regarding Claim 11, Kuang et al discloses the limitations of claim 1 as explained above. Kuang et al further discloses
wherein the first gate capping pattern (22 Fig 17C) comprises second side walls (top and bottom Fig 17C, (see the above 112(b) rejection) opposite to each other in a third direction (z direction Fig 17C) intersecting the first direction (x direction Fig 17C), and wherein the second side walls (top and bottom Fig 17C (see the above 112(b) rejection) contact the second gate capping pattern (82 Fig 17C).
Regarding Claim 12, Kuang et al discloses the limitations of claim 1 as explained above. Kuang et al further discloses
wherein the upper surface of the first gate capping pattern (22 Fig 17C) is on a first plane (shown in Fig 17C) that is different from a second plane (shown in Fig 17C) of an upper surface of the etching stop film (66 Fig 17C).
Regarding Claim 13, Kuang et al discloses a semiconductor device (semiconductor device [0010]) comprising:
a substrate (substrate 10 [0010] Fig 17A-C);
an active pattern (shown in annotated Fig 17C) comprising: a lower pattern (shown in annotated Fig 17C) extending in a first direction (x direction Fig 17C); and
a plurality of sheet patterns (first channel layers 15 of nanosheet stack 17 [0012] Fig 17C) above an upper surface of the lower pattern (shown in annotated Fig 17C) and spaced apart from the lower pattern (shown in annotated Fig 17C) in a second direction (y direction 17B) substantially perpendicular to the first direction (x direction Fig 17C);
a gate structure (gate dielectric layer 72 and gate electrode 74 [0077] Fig 17C) on the lower pattern (shown in annotated Fig 17C) and comprising a gate electrode (gate electrode 74 Fig 17C) and a gate insulating film (gate dielectric layer 72 Fig 17C), the gate electrode (74 Fig 17C) and the gate insulating film (72 Fig 17C) at least partially surrounding the plurality of sheet patterns (15 Fig 17C);
a first gate capping pattern (hard mask layer 22 [0057] Fig 17C) on the gate structure (72, 74 Fig 17C) and above the plurality of sheet patterns (15 Fig 17C) in the second direction (y direction Fig 17B);
a gate spacer (gate sidewall spacer 46g [0041] Fig 17C) extending along a side wall of the gate structure (72, 74 Fig 17C);
a second gate capping pattern (metal gate liner 82 [0078] Fig 17C) extending along an upper surface of the gate structure (72, 74 Fig 17C) and an upper surface of the first gate capping pattern (22 Fig 17C);
a source/drain pattern (source/drain 56 [0050] Fig 17C) on at least one side of the gate structure (72, 74 Fig 17C); and
an etching stop film (CESL 66 [0060] Fig 17C) on the source/drain pattern (56 Fig 17C) and a side wall of the first gate capping pattern (22 Fig 17C), wherein the gate structure (72, 74 Fig 17C) comprises a plurality of inter-gate structures (72, 74 Fig 17C) between the lower pattern (shown in annotated Fig 17C) and the plurality of sheet patterns (15 Fig 17C), and between adjacent sheet patterns (15 Fig 17C) of the plurality of sheet patterns (17C),
wherein the first gate capping pattern (22 Fig 17C) does not overlap (shown in annotated Fig 17B) the gate spacer (46g Fig 17C) in the second direction (y direction Fig 17B),
and wherein, from the lower pattern (shown in annotated Fig 17C), the upper surface of the first gate capping pattern (22 Fig 17C) is higher than the upper surface of the gate structure (72, 74 Fig 17C).
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Regarding Claim 14, Kuang et al discloses the limitations of claim 13 as explained above. Kuang et al further discloses
wherein the second gate capping pattern (82 Fig 17C) at least partially covers (shown in Fig 17C) an upper surface of the gate spacer (46g Fig 17C).
Regarding Claim 15, Kuang et al discloses the limitations of claim 13 as explained above. Kuang et al does not disclose
further comprising an inner spacer (46g Fig 17C) between the gate structure (72, 74 Fig 17C) and the source/drain pattern (56 Fig 17C),
wherein the inner spacer (46g Fig 17C) contacts the plurality of inter-gate structures (72, 74 Fig 17C).
Regarding Claim 16, Kuang et al discloses the limitations of claim 13 as explained above. Kuang et al further discloses
wherein, from the upper surface of the lower pattern (shown above in annotated Fig 17C), a height of the upper surface of the gate structure (72, 74 Fig 17C) is equal (equal shown in Fig 17C) to or greater than a height of an upper surface of the source/drain pattern (56 Fig 17C).
Regarding Claim 17, Kuang et al discloses the limitations of claim 13 as explained above. Kuang et al further discloses
wherein, from the lower pattern (shown above in annotated Fig 17C), an upper surface of the etching stop film (66 Fig 17C) is higher (shown in Fig 17C) than the upper surface of the first gate capping pattern (22 Fig 17C).
Regarding Claim 18, Kuang et al discloses the limitations of claim 13 as explained above. Kuang et al further discloses
wherein, from the substrate (substrate 10 [0010] Fig 17A-C), an upper surface of the gate spacer (46g Fig 17C) is lower than an upper surface of the second gate capping pattern (82 Fig 17C).
Regarding Claim 19, Kuang et al discloses the limitations of claim 13 as explained above. Kuang et al further discloses
further comprising: a source/drain contact (conductive features 94 [0084] Fig 17C) on the source/drain pattern (56 Fig 17C) and connected to the source/drain pattern (56 Fig 17C),
wherein, from the lower pattern (shown above in annotated Fig 17C), an upper surface of the source/drain contact (94 Fig 17C) is higher than the upper surface of the first gate capping pattern (82 Fig 17C).
Regarding Claim 20, Kuang et al discloses a semiconductor device (semiconductor device [0010]) comprising:
a substrate (substrate 10 [0010] Fig 17A-C);
an active pattern (shown in annotated Fig 17C) comprising: a lower pattern (shown in annotated Fig 17C) extending in a first direction (x direction Fig 17C); and
a plurality of sheet patterns (first channel layers 15 of nanosheet stack 17 [0012] Fig 17C) above an upper surface of the lower pattern (shown in annotated Fig 17C) and spaced apart from the lower pattern (shown in annotated Fig 17C) in a second direction (y direction Fig 17B) substantially perpendicular to the first direction (x direction Fig 17C);
a field insulating film (isolation layer 26 [0031] Fig 5 and Fig 17B) at least partially covering (shown in annotated Fig 5) a side wall of the lower pattern (shown in annotated Fig 17C);
a gate structure (gate dielectric layer 72 and gate electrode 74 [0077] Fig 17C) on the lower pattern (shown in annotated Fig 17C) and the field insulating film (26 Fig 5 and Fig 17C), extending in a third direction (vertical z direction Fig 5, Fig 17A-C), and comprising a gate electrode (gate electrode 74 Fig 17C) and a gate insulating film (gate dielectric layer 72 Fig 17C), the gate electrode (74 Fig 17C) and the gate insulating film (72 Fig 17C) at least partially surrounding the plurality of sheet patterns (15 Fig 17C);
a first gate capping pattern (hard mask layer 22 [0057] Fig 17C) on the gate structure (72, 74 Fig 17C) and above the plurality of sheet patterns (15 Fig 17C) in the second direction (y direction Fig 17B);
a gate spacer (gate sidewall spacer 46g [0041] Fig 17C) extending along a side wall of the gate structure (72, 74 Fig 17C) in the third direction (z direction Fig 17C);
a second gate capping pattern (metal gate liner 82 [0078] Fig 17C) extending along an upper surface of the gate structure (72, 74 Fig 17C) and an upper surface of the first gate capping pattern (22 Fig 17C);
a gate contact (gate contact 96 [0084] Fig 17B-C) penetrating (shown in Fig 17B) the first gate capping pattern (22 Fig 17B-C) and the second gate capping pattern (82 Fig 17B-C) on the gate electrode (74 Fig B-C), the gate contact (96 Fig 17B-C) being connected to the gate electrode (74 Fig 17B-C);
a source/drain pattern (source/drain 56 [0050] Fig 17C) on at least one side of the gate structure (72, 74 Fig 17C);
an etching stop film (CESL 66 [0060] Fig 17C) on the source/drain pattern (56 Fig 17C) and a side wall of the first gate capping pattern (22 Fig 17C); and
a source/drain contact (conductive features 94 [0084] Fig 17C) on the source/drain pattern (56 Fig 17C) and connected to the source/drain pattern (56 Fig 17C),
wherein the first gate capping pattern (22 Fig 17C) does not overlap (shown in annotated Fig 17B) the first insulating film (26 Fig 5 and Fig 17C) in the second direction (y direction Fig 17B),
wherein a second gate capping pattern (82 Fig 17C) at least partially covers an upper surface of the gate spacer (46g Fig 17C),
wherein a side wall of the second gate capping pattern (82 Fig 17C) contacts the etching stop film (66 Fig 17C), and
wherein, from the lower pattern (shown in annotated Fig 17C), the upper surface of the first gate capping pattern (22 Fig 17C) is higher than the upper surface of the gate structure (72, 74 Fig 17C).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kuang et al (US 2022/0278196) in view of Noh et al (US 2020/0091152).
Regarding Claim 8, Kuang et al discloses the limitations of claim 1 as explained above. Kuang et al further discloses
wherein the gate structure (72, 74 Fig 17C) comprises a plurality of inter-gate structures (72, 74 Fig 17C) between the lower pattern (shown above in annotated Fig 17C) and the plurality of sheet patterns (15 Fig 17C), and between adjacent sheet patterns (15 Fig 17C) of the plurality of sheet patterns (15 Fig 17C).
Kuang et al does not dislcose
wherein the source/drain pattern contacts each of the plurality of inter-gate structures.
Noh et al, in the related art of semiconductor devices that include multi-gate transistors, multi-bride channel elements, and nano-sheets discloses
wherein the source/drain pattern (source/drain region 152 of third gate structures G3 [0027] Fig 5) contacts each of the plurality of inter-gate structures (first, second and third wire patterns 141, 142, 143 of the third gate structures G3 [0022] Fig 5).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Kuang et al to include wherein the source/drain pattern contacts each of the plurality of inter-gate structures as taught by Noh in order to have a device wherein the current control capability my be improved without increasing a gate length of the multi-gate transistors [0003]. Further, a person of ordinary skill in the art would have recognized that having the source/drain patterns each contact the inter-gate structures would be advantageous in optimizing the electrical functioning of the device (see MPEP 2143.I(D)).
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Choe et al (US 2010/0237401) which discloses gate structures in a semiconductor device [0008], and Haran et al (US 2019/0267371) which discloses FinFET devices [0013].
Conclusion
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached on (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812