DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The three information disclosure statement (IDS), submitted on 3/31/25, 3/19/24, 12/27/23, is in compliance with the provisions of 37 CFR 1.97. Accordingly, the three IDS is being considered by the examiner.
Claim Objections
Claim 13 objected to because of the following informalities:
“pitching” should read “etching” line 6 (see spec. 0028)
. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 (and claim 5 via dependency) rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites the limitation "the surface" in line 2. There is insufficient antecedent basis for this limitation in the claim. Applicant is advised to replace with “the at least one surface”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li (WO-2020247291-A1) in view of Kageyama (JP-2009218281-A, machine translation “Kageyama_English” cited and included herewith).
Regarding claim 1, Li discloses a method for producing a semiconductor component for emitting light (fig. 2, 0019), the method comprising: providing a base body (base body 240+250+260+261+271, 0041), the base body comprising an active layer for generating the light and a tunnel contact (240+250+260+261+271 comprises active layer 250 and tunnel contact 260+261+271, 0041), and forming a stop structure by implantation in a region (stop structure 270 formed by implantation in region corresponding to 270, 0041), wherein the stop structure delimits the tunnel contact and serves to constrict a current introduced into the active layer (270 delimits 260+261+271 and constricts a current into 250).
Li does not explicitly disclose wherein defects due to crystal imperfections are generated by the implantation so that the implanted region is transparent for the light having an emitted wavelength.
Kageyama discloses a surface light emitting laser element with hydrogen ion implantation resulting in a composite defect in the implanted region, and the current confinement layer being transparent to the laser’s emitted wavelength (figs. 3-5 current confinement layer 115/108, 0034, 0038-0041).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have defects due to crystal imperfections are generated by the implantation so that the implanted region is transparent for the light having an emitted wavelength to reduce light absorption loss in the implanted region/increase efficiency (Kageyama 0034).
Regarding claim 2, modified Li discloses the method as claimed in claim 1, wherein the implantation comprises a proton implantation (0038), and an implantation energy is selected such that the stop structure is formed inside layers that form the tunnel contact and does not extend into adjacent layers on at least one side of the tunnel contact in relation to an implantation direction (270 formed inside layers that form 260+261+271 and does not extend into adjacent layers beneath 260+261+271 in relation to implantation direction (top to bottom fig. 2)).
Regarding claim 3, modified Li discloses the method as claimed in claim 1,wherein an implantation energy is selected such that the stop structure is formed inside layers that form the tunnel contact (270 formed inside layers that form 260+261+271), and at least a part of the stop structure extends into a layer adjacent to the tunnel contact (270 extends into DBR 280 adjacent to 260+261+271, 0041).
Regarding claim 15, Li discloses a semiconductor component for emitting light (fig. 2), comprising a base body having at least one mesa section with an emission region for the light (base body 201 has mesa section 201 with emission region 208, 0041), a first mirror (first mirror 230), a second mirror (second mirror 280), an active section arranged between the first mirror and the second mirror for generating the light (active region 250 between 230 and 280), and a tunnel contact delimited by a stop structure (tunnel contact 260+261+271 delimited by stop structure 270), and wherein the semiconductor component is based on indium phosphide (0044, InP).
Li does not explicitly disclose the fig. 2 embodiment containing gallium and arsenide.
Li separately discloses using a semiconductor combination that includes AlGaInAs/InP (0043).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include gallium and arsenide to make the device more suitable for performance at high temperature and improve efficiency.
Li does not explicitly disclose wherein an implanted region forming the stop structure is transparent for light having an emitted wavelength.
Kageyama discloses a surface light emitting laser element with hydrogen ion implantation resulting in a composite defect in the implanted region, and the current confinement layer being transparent to the laser’s emitted wavelength (figs. 3-5 current confinement layer 115/108, 0034, 0038-0041).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have an implanted region forming the stop structure is transparent for light having an emitted wavelength to reduce light absorption loss in the implanted region/increase efficiency (Kageyama 0034).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Kageyama and Onishi (US-20090097518-A1).
Regarding claim 4, modified Li discloses the method as claimed in claim 1, comprising applying a blocking structure to form the implantation region (0044, “mask”), wherein a surface of the base body is to be irradiated with an implantation radiation (top surface of base body irradiated w/ 270), so that the implantation radiation penetrates the base body at least as far as the tunnel contact in regions not covered by the mask (270 penetrates 240+250+260+261+271 at least as far as 260+261+271 in regions not covered by the blocking structure/mask (peripheral regions)).
Modified Li does not explicitly disclose further comprising applying a blocking structure on at least one surface of the base body.
Onishi discloses a VCSEL with a mask formed on a top surface of a base body, wherein the top surface of the base body is to be irradiated with an implantation radiation (fig. 2b mask 64 formed on top surface, implantation region = 61b/dotted line, 0037).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have applied a blocking structure on at least one surface of the base body to ensure that the mask sufficiently protects the regions it is meant to and improve accuracy of 270 formation.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Kageyama, Onishi, and Sirbu (US-20020131464-A1).
Regarding claim 5, modified Li discloses the method as claimed in claim 4, wherein the stop structure forms an aperture defining an access region not affected by the implantation radiation (270 forms aperture in center defining access region 298 not affected by implantation radiation, 0041).
Modified Li does not disclose wherein the blocking structure comprises a photoresist applied before the implantation so as to correspond to the aperture.
Sirbu discloses a VCSEL method of fabrication with a blocking structure comprising a photoresist applied before implantation so as to correspond to an aperture (fig. 6 blocking structure photoresist mask/disc 27 corresponds to aperture, 0054-0055).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the blocking structure comprise a photoresist to simplify and improve precision of implantation region formation.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Kageyama and Carson (US-20200335942-A1).
Regarding claim 7, modified Li discloses the method as claimed in claim 1, wherein a plurality of stop structures are formed (fig. 5F multi-VCSEL example w/ plurality of stop structures 570, 0057).
Modified Li does not disclose so that the semiconductor component comprises a plurality of tunnel contacts.
Tunnel contact layer 560+561+570 continuous.
Carson discloses a VCSEL device with a plurality of VCSELs + each VCSEL having its own separate tunnel junction (fig. 10d VCSELs 103 each w/ tunnel junction 107, 0085-0086).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have semiconductor component comprising separate tunnel contacts for each VCSEL (i.e. a plurality of tunnel contacts) to help isolate damage/issues and not need to replace entire continuous tunnel contact for all VCSELs.
Claim(s) 8, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Kageyama, Carson, and Zhao (US-20210399525-A1).
Regarding claim 8, modified Li discloses the method as claimed in claim 7.
Modified Li does not disclose further comprising forming electrical insulation barriers arranged laterally with respect to the plurality of tunnel contacts, so that mesa sections corresponding to the respective tunnel contacts are electrically divided from one another at least in a region of the active layer.
Zhao discloses using electrical insulation barriers between adjacent VCSELs in VCSEL array, with electrical insulation barriers lateral with respect to tunnel junctions, electrically dividing adjacent VCSEL at least in region of active layer (fig. 2b electrical insulation barriers trenches+isolation implant 224 between adjacent VCSELs, tunnel junctions 214, active layer 208, 0026, 0041, 0050).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form electrical insulation barriers arranged laterally with respect to the plurality of tunnel contacts, so that mesa sections corresponding to the respective tunnel contacts are electrically divided from one another at least in a region of the active layer to isolate adjacent mesa sections and prevent free carriers from crossing into adjacent emitters (Zhao 0041).
Regarding claim 16, modified Li discloses the semiconductor component as claimed in claim 15, wherein a plurality of mesa sections are provided (fig. 5f plurality of 501s, 0027).
Modified Li does not disclose the semiconductor component comprises a plurality of tunnel contacts.
Tunnel contact layer 560+561+570 continuous.
Carson discloses a VCSEL device with a plurality of VCSELs + each VCSEL having its own separate tunnel junction (fig. 10d VCSELs 103 each w/ tunnel junction 107, 0085-0086).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have semiconductor component comprising separate tunnel contacts for each VCSEL (i.e. a plurality of tunnel contacts) to help isolate damage/issues and not need to replace entire continuous tunnel contact for all VCSELs.
Modified Li does not disclose wherein the plurality of mesa sections are divided from one another by implanted electrical insulation barriers.
Zhao discloses using isolation implants between adjacent VCSELs in VCSEL array (fig. 2b isolation implant 224 between adjacent VCSELs, 0041, 0050).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the plurality of mesa sections are divided from one another by implanted electrical insulation barriers to isolate adjacent mesa sections and prevent free carriers from crossing into adjacent emitters (Zhao 0041).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Kageyama, Carson, Zhao, and Yuen (US-20190181609-A1).
Regarding claim 9, modified Li discloses the method as claimed in claim 8.
Modified Li does not disclose wherein all electrically conductive layers in the base body are divided by the electrical insulation barriers.
Yuen discloses an emitter array with electrical insulation barriers that extend down into a common substrate between emitters (fig. 3, insulation barriers 310+312 extend into substrate 306 and between, 0051-0054).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have all electrically conductive layers in the base body are divided by the electrical insulation barriers to provide further/more reliable electrical isolation between adjacent emitters (Yuen 0052).
Claim(s) 10, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Kageyama and Huo (CN-111224320-A, machine translation "Huo_English" cited and included herewith).
Regarding claim 10, modified Li discloses the method as claimed in claim 1.
Modified Li does not disclose further comprising applying an insulating layer on a surface of the base body.
Huo discloses applying an insulating layer on a surface of a base body of a VCSEL structure (fig. 10 insulating layer 110 on surface of VCSEL, lines 323-331).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply an insulating layer on a surface of the base body to improve electrical isolation and protect layers of VCSEL (Huo lines 328-331). See modified fig. 2.
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Modified fig. 2 (one rough example of proposed modification)
Regarding claim 12, modified Li discloses the method as claimed in claim 10, further comprising fitting a functional section on the insulating layer, the functional section containing a mirror and/or a photodiode (modified fig. 2 functional section DBR mirror 230 (or 280) on insulating layer).
def. on –
used as a function word to indicate position in contact with and supported by the top surface of (Merriam-Webster def. 1a)
used as a function word to indicate position in or in contact with an outer surface (Merriam-Webster def. 1b)
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Kageyama, Huo, and Otto (US-20180294378-A1).
Regarding claim 11, modified Li discloses the method as claimed in claim 10.
Modified Li does not disclose wherein the insulating layer is arranged inside a dielectric superficial protective layer.
Otto discloses a method for producing an optoelectronic semiconductor component with an insulating passivation layer arranged inside a superficial dielectric layer (fig. 1J insulating passivation layer 72 inside dielectric layer 73+74, 0075, 0088, 0099).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the insulating layer is arranged inside a dielectric superficial protective layer to help planarize a top surface of the device and allow for additional layers/components to be attached (Otto 0099).
Claim(s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Kageyama, Carson, and Pfeuffer (US-20170084777-A1).
Regarding claim 13, modified Li discloses the method as claimed in claim 7.
Modified Li does not disclose further comprising: introducing trenches by etching for forming electrical contacts of the semiconductor component, passivating an entire surface relief of the semiconductor component that contains the trenches, and freeing deepest points of the trenches from the passivation by etching.
Pfeuffer discloses an optoelectronic semiconductor chip with a trench for forming electrical contacts of the semiconductor component (fig. 1c trench at 70,71 location for forming electrical contacts from layer 33, 0086), passivating an entire surface relief of the semiconductor component that contains the trenches (passivation layer 51 covers entire surface of trench, 0084), and freeing deepest points of the trenches from the passivation (bottom surface of trench has 51 removed). Pfeuffer separately discloses etching to remove semiconductor regions (0005).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have added trenches by etching for forming electrical contacts of the semiconductor component, passivating an entire surface relief of the semiconductor component that contains the trenches, and freeing deepest points of the trenches from the passivation by etching to allow for both metal layers/electrodes/terminals to be located on one side of the device and provide more open space on the opposite side for additional components/layers. Also having individual vertical electrical contacts allows for smaller sections to be replaced if there are issues. See modified fig. 5f.
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Modified fig. 5f (one rough example of proposed modification)
Regarding claim 14, modified Li discloses the method as claimed in claim 13, wherein at least one subsection of a mirror is removed by etching between two neighboring trenches which correspond to different tunnel contacts.
Select two trenches that are separated by a third trench in between, and the third trench will correspond to a subsection of a mirror that is removed by etching. Modified fig. 5f first and third trench from left correspond to different tunnel contacts and are neighboring. Second trench from left corresponds to etched subsection of mirror 580 between first and third trench.
def. neighboring – next to or near each other (Cambridge Dictionary)
Allowable Subject Matter
Claim 6 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 6: Prior art of record does not disclose fitting of both a first mirror and a second mirror on different sides of a base body after removal of carrier substrate. Prior art of record discloses fitting one mirror before carrier substrate removal and fitting a second mirror after carrier substrate removal.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Imai US-20080181267-A1
Chantre US-20160047986-A1.
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/A.E./Examiner, Art Unit 2828
/MINSUN O HARVEY/Supervisory Patent Examiner, Art Unit 2828
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