DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 16 – 20 have been considered but are moot because upon further consideration, a new ground(s) of rejection is made in view of Zhang et al (US 8,902,094) and Shrivastava et al (US 10,476,542).
Examiner attempted to expedite prosecution of the application by calling Applicants Representative and leaving a voicemail to discuss potential amendments to claim 16. No response was received.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 16 and 19 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al (US 8,902,094) in view of Shrivastava et al (US 10,476,542).
Re claim 16, Zhang teaches of a method comprising: receiving an analog input signal (#118, Figures 1 – 2); providing an analog signal current, representative of the analog input signal (communication signals inherently involve both voltage and current), at an output of an amplifier (#210, Fig.2) for direct sampling by a first sampling capacitor (first capacitor after #200, Fig.2); activating a first sampling switch (first switch after #200, Fig.2) coupled to the first sampling capacitor for a first time duration (T, Fig.3); activating a second sampling switch (second switches after #210, Fig.2) to couple a second sampling capacitor (second capacitor after #210, Fig.2) to the first sampling capacitor (as shown in Fig.2) for a second time duration (NT, Fig.3), in which a portion of the second time duration overlaps a portion of the first time duration (overlapping as shown in Fig.3), to provide an analog voltage (communication signals inherently involve both voltage and current); and converting the analog voltage to the digital output signal (#220, Fig.2). However, Zhang does not specifically teach of the amplifier being a digital step attenuator.
Shrivastava teaches of a system comprising: a digital step attenuator (DSA) having an input and an output (DSA, Fig.7B); a sampling system having an input coupled to the output of the DSA (#720B, 730B, #740B, #750B, Fig.7B), the sampling system including a first sampling capacitor (730B, Fig.7B), a second sampling capacitor (740B, Fig.7B), and at least one sampling switch (#720B, Fig.7B), the sampling system configured to sample an analog signal current provided from the DSA (Col 1, Lines 13 – 28 and Fig.7B) on the first sampling capacitor and the second sampling capacitor concurrently (as shown in Fig.7B) in response to activation of the at least one sampling switch to integrate the analog signal current as a sampling voltage on both the first and second sampling capacitors (as shown in Fig.7B); and an ADC having an input and an output, the input of the ADC coupled to the output of the sampling system (ADC1, ADC2, Fig.7B) (Col 10, Lines 14 – 38).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the amplifier be a digital step attenuator for its high accuracy and performance.
Re claim 19, Zhang teaches of further comprising setting a length of the first time duration (T, Fig.3) to define a sampling bandwidth of an ADC (NT, Fig.3).
Re claim 20, Zhang teaches of the second sampling switch is a first of a plurality of second sampling switches (plurality of second sampling switches as shown in Fig.2), the second sampling capacitor is a first of a plurality of second sampling capacitors (plurality of second sampling capacitors as shown in Fig.2), the ADC is a first of a plurality of ADCs (plurality of ADCs (#220) as shown in Fig.2), the method further comprising: activating the second sampling switches in an interleaved manner (time-interleaved ADC, Abstract) to couple a respective one of the second sampling capacitors (plurality of second sampling capacitors as shown in Fig.2) to an intermediate node for the second time duration (node after #210, Fig.2) to integrate the analog signal current on both the first sampling capacitor and on the respective one of the second sampling capacitors as the second sampling voltage (analog signal current is integrated on both the fist and second sampling capacitors); and converting the second sampling voltage to the digital output signal via a respective one of the ADC in the interleaved manner (time-interleaved ADC, Abstract).
Allowable Subject Matter
Claims 1 – 6, 8 – 15 and 21 are allowed.
Claims 17 – 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/ARISTOCRATIS FOTAKIS/
Primary Examiner, Art Unit 2633