DETAILED ACTION
Allowable Subject Matter
Claims 2-3, 5, 8, 12-13, 17, 21-22, 24, 27-28 and 30 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4, 6-7, 9, 20, 23, 25-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Smith-Lacey US 2023/0334708 hereinafter referred to as Smith-Lacey in view of Schaefer et al. US 2020/0278908 hereinafter referred to as Smith-Lacey.
In regards to claim 1, Smith-Lacey teaches:
“An apparatus for data processing, comprising: a memory; and a processor coupled to the memory and, based on information stored in the memory, the processor is configured to: obtain a set of bits including a first subset of bits and a second subset of bits”
Smith-Lacey teaches in paragraph [0185] The algorithms and methods described herein could be performed by one or more processors executing code that causes the processor(s) to perform the algorithms/methods. Examples of a computer-readable storage medium include a random-access memory (RAM), read-only memory (ROM), an optical disc, flash memory, hard disk memory, and other memory devices that may use magnetic, optical, and other techniques to store instructions or other data and that can be accessed by a machine. Smith-Lacey Figure 1A and paragraph [0063] teaches data for a single channel such that data value 101 comprises 10 bits. Smith-Lacey paragraph [0064] teaches The data value 101 to be compressed is split (i.e. divided) by the dividing logic 115 into a first subset of bits 102 and a second subset of bits 103.
“wherein a bit width of the set of bits is greater than a configured bit width of compression hardware”
Smith-Lacey paragraph [0064] and Figure 1A teach the first subset 102 comprises 8 bits and the second subset 103 comprises 2 bits. The first subset comprises the 8 most significant bits (MSBs) of the 10-bit data value. The second subset 103 comprises the 2 least significant bits (LSBs) of the 10-bit value. The second least significant bit of the 10-bit data value 101 is the most significant bit of the second subset of bits 103. The Examiner interprets from Figure 1A that the first compression module 104 is configured to process 8-bits and the second compression module is configured to process 2-bits. The original bit width of the data is 10-bits and therefore the bit-width is greater than the configured compression hardware.
“process the first subset of bits [and second subset of bits]”
Smith Lacey paragraph [0066] and Figure 1A teaches Following independent compression of the first subset of bits and the second subset of bits, the first and second compressed subsets of bits are packed together and stored in memory as compressed data 108.
“and output, for a decoder of the compression hardware, the set of bits including the processed first subset of bits and the second subset of bits”
Smith-Lacey teaches in Figure 1D and paragraph [0071] decompression of the data value (compressed using the scheme shown in FIG. 1A) implemented in a decompression unit. The decompression unit comprises a first decompression module 109, a second decompression module 110 and combining logic 114.
Smith-Lacey does not explicitly teach:
“[process first subset of bits] based on a parity corresponding to the second subset of bits”
Schaefer paragraph [0151] teaches each parity bit of the first set corresponding to parity information for a respective first subset of the data and each parity bit of the second set corresponding to parity information for a respective second subset of the data, where each of the respective first subsets overlap with at least one of the respective second subsets for at least one bit of the data, performing an error detection operation on the data read from the memory array based on the first set of parity bits and the second set of parity bits. The Examiner interprets that using the parity of the second subset of bits to compare with the first subset of bits to determine an error is a form of processing the first subset of bits. The processing is to determine and error and is based on the value of parity bits of the second subset of bits. It would have been obvious for a person with ordinary skill in the art before the invention was effectively filed to have modified Smith-Lacey in view of Schaefer to have included the features of “[process first subset of bits] based on a parity corresponding to the second subset of bits” for improving memory devices, generally, may include increasing memory cell density, increasing read/write speeds, increasing reliability, increasing data integrity, reducing power consumption, or reducing manufacturing costs, among other metrics (Schaefer [0005]).
In regards to claim 4, Smith-Lacey/Schaefer teach all the limitations of claim 1 and further teach:
“wherein the first subset of bits corresponds to a least significant bit (LSB) component of the set of bits, and wherein the second subset of bits corresponds to a most significant bit (MSB) component of the set of bits”
Smith-Lacey paragraph [0064] and Figure 1A teach the first subset 102 comprises 8 bits and the second subset 103 comprises 2 bits. The first subset comprises the 8 most significant bits (MSBs) of the 10-bit data value. The second subset 103 comprises the 2 least significant bits (LSBs) of the 10-bit value. The Examiner interprets that the subset 103 would correspond to the Applicant’s claims first subset and the subset 102 would correspond to Applicant’s claimed second subset.
In regards to claim 6, Smith-Lacey/Schaefer teach all the limitations of claim 1 and further teach:
“wherein the set of bits corresponds to a set of pixels in a frame”
Smith-Lacey paragraph [0063] teaches each pixel in the image represented by the image data comprises 10 bits per channel. FIG. 1A shows data for a single channel such that data value 101 comprises 10 bits.
In regards to claim 7, Smith-Lacey/Schaefer teach all the limitations of claim 1 and further teach:
“wherein to output the set of bits including the processed first subset of bits and the second subset of bits, the processor is configured to transmit, to the decoder of the compression hardware, the set of bits including the processed first subset of bits and the second subset of bits”
Figures 1B, 3B, 5B, 6, inter alia.
In regards to claim 9, Smith-Lacey/Schaefer teach all the limitations of claim 1 and further teach:
“wherein the bit width of the set of bits is 10 bits, 12 bits, 14 bits, or 16 bits”
Smith-Lacey paragraph [0063] teaches each pixel in the image represented by the image data comprises 10 bits per channel. FIG. 1A shows data for a single channel such that data value 101 comprises 10 bits.
In regards to claim 20, Smith-Lacey/Schaefer teaches all the limitations of claim 1 and claim 20 contains similar limitations. Therefore, claim 20 is rejected for similar reasoning.
In regards to claim 23, Smith-Lacey/Schaefer teach all the limitations of claim 20 and claim 23 contains similar limitations as in claim 4. Therefore, claim 23 is rejected for similar reasoning as applied to claim 4.
In regards to claim 25, Smith-Lacey/Schaefer teach all the limitations of claim 20 and claim 25 contains similar limitations as in claim 6. Therefore, claim 25 is rejected for similar reasoning as applied to claim 6.
In regards to claim 26, Smith-Lacey/Schaefer teach all the limitations of claim 20 and claim 26 contains similar limitations as in claim 7. Therefore, claim 26 is rejected for similar reasoning as applied to claim 7.
In regards to claim 28, Smith-Lacey/Schaefer teach all the limitations of claim 20 and claim 28 contains similar limitations as in claim 9. Therefore, claim 28 is rejected for similar reasoning as applied to claim 9.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Smith-Lacey in view of Schaefer in view of Singh et al. US 8,176,524 hereinafter referred to as Singh.
In regards to claim 10, Smith-Lacey/Schaefer teach all the limitations of claim 1 and further teach:
“wherein the apparatus is a wireless communication device comprising at least one of a transceiver or an antenna coupled to the processor, wherein to output the set of bits, the processor is configured to output the set of bits via at least one of the transceiver or the antenna”
Singh teaches a system and method for wireless communication of video data having partial compression (title). Singh Figure 2 teaches a receiver and transmitter having antennas. It would have been obvious for a person with ordinary skill in the art before the invention was effectively file to have modified Smith-Lacey/Schaefer in view of Singh to have included the features of “wherein the apparatus is a wireless communication device comprising at least one of a transceiver or an antenna coupled to the processor, wherein to output the set of bits, the processor is configured to output the set of bits via at least one of the transceiver or the antenna” because transmission of uncompressed video over a wireless channel is challenging because uncompressed video requires transmission of a larger amount of data than compressed video (Singh column 1 lines 39-44).
Claim(s) 11, 14-16, 18, 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Smith-Lacey in view of Schaefer in view of Liu et al. US 9,767,529 hereinafter referred to as Liu.
In regards to claim 11, Smith-Lacey teaches:
“An apparatus for data processing, comprising: a memory; and a processor coupled to the memory and, based on information stored in the memory, the processor is configured to: obtain ... a set of bits including a first subset of bits and a second subset of bits”
Smith-Lacey teaches in paragraph [0185] The algorithms and methods described herein could be performed by one or more processors executing code that causes the processor(s) to perform the algorithms/methods. Examples of a computer-readable storage medium include a random-access memory (RAM), read-only memory (ROM), an optical disc, flash memory, hard disk memory, and other memory devices that may use magnetic, optical, and other techniques to store instructions or other data and that can be accessed by a machine. Smith-Lacey Figure 1A and paragraph [0063] teaches data for a single channel such that data value 101 comprises 10 bits. Smith-Lacey paragraph [0064] teaches The data value 101 to be compressed is split (i.e. divided) by the dividing logic 115 into a first subset of bits 102 and a second subset of bits 103.
“wherein a bit width of the set of bits is greater than a configured bit width of compression hardware”
Smith-Lacey paragraph [0064] and Figure 1A teach the first subset 102 comprises 8 bits and the second subset 103 comprises 2 bits. The first subset comprises the 8 most significant bits (MSBs) of the 10-bit data value. The second subset 103 comprises the 2 least significant bits (LSBs) of the 10-bit value. The second least significant bit of the 10-bit data value 101 is the most significant bit of the second subset of bits 103. The Examiner interprets from Figure 1A that the first compression module 104 is configured to process 8-bits and the second compression module is configured to process 2-bits. The original bit width of the data is 10-bits and therefore the bit-width is greater than the configured compression hardware.
“process the first subset of bits [and second subset of bits]”
Smith Lacey paragraph [0066] and Figure 1A teaches Following independent compression of the first subset of bits and the second subset of bits, the first and second compressed subsets of bits are packed together and stored in memory as compressed data 108.
“and output, for a decoder of the compression hardware, the set of bits including the processed first subset of bits and the second subset of bits”
Smith-Lacey teaches in Figure 1D and paragraph [0071] decompression of the data value (compressed using the scheme shown in FIG. 1A) implemented in a decompression unit. The decompression unit comprises a first decompression module 109, a second decompression module 110 and combining logic 114.
Smith-Lacey does not explicitly teach:
“[process first subset of bits] based on a parity corresponding to the second subset of bits”
Schaefer paragraph [0151] teaches each parity bit of the first set corresponding to parity information for a respective first subset of the data and each parity bit of the second set corresponding to parity information for a respective second subset of the data, where each of the respective first subsets overlap with at least one of the respective second subsets for at least one bit of the data, performing an error detection operation on the data read from the memory array based on the first set of parity bits and the second set of parity bits. The Examiner interprets that using the parity of the second subset of bits to compare with the first subset of bits to determine an error is a form of processing the first subset of bits. The processing is to determine and error and is based on the value of parity bits of the second subset of bits. It would have been obvious for a person with ordinary skill in the art before the invention was effectively filed to have modified Smith-Lacey in view of Schaefer to have included the features of “[process first subset of bits] based on a parity corresponding to the second subset of bits” for improving memory devices, generally, may include increasing memory cell density, increasing read/write speeds, increasing reliability, increasing data integrity, reducing power consumption, or reducing manufacturing costs, among other metrics (Schaefer [0005]).
“[obtain] from and encoder of compression hardware”
Liu teaches in column 12 lines 29-36 the 8-bit pixel may include 8 most significant bits (MSBs) of the N-bit pixel, and the (N−8)-bit pixel may include (N−8) least significant bits (LSBs) of the N-bit pixel. The compressor 112 of the processing circuit 104 applies data compression to an encoding unit composed of multiple N-bit pixels (N>8), and generates an output bitstream to the frame buffer 102 based on a data compression result of the encoding unit. It would have been obvious for a person with ordinary skill in the art before the invention was effectively filed to have modified Smith-Lacey/Schaefer in view of Liu to have included the features of “[obtain] from and encoder of compression hardware” because if data of the compressed image frame is continuously stored in the frame buffer, the graphic processor/display processor may have difficulty in randomly accessing data of the compressed image frame in the frame buffer (Liu column 1 lines 31-36).
In regards to claim 14, Smith-Lacey/Schaefer teach all the limitations of claim 1 and further teach:
“wherein the first subset of bits corresponds to a least significant bit (LSB) component of the set of bits, and wherein the second subset of bits corresponds to a most significant bit (MSB) component of the set of bits”
Smith-Lacey paragraph [0064] and Figure 1A teach the first subset 102 comprises 8 bits and the second subset 103 comprises 2 bits. The first subset comprises the 8 most significant bits (MSBs) of the 10-bit data value. The second subset 103 comprises the 2 least significant bits (LSBs) of the 10-bit value. The Examiner interprets that the subset 103 would correspond to the Applicant’s claims first subset and the subset 102 would correspond to Applicant’s claimed second subset.
In regards to claim 15, Smith-Lacey/Schaefer/Liu teach all the limitations of claim 11 and further teach:
“wherein the set of bits corresponds to a set of pixels in a frame”
Smith-Lacey paragraph [0063] teaches each pixel in the image represented by the image data comprises 10 bits per channel. FIG. 1A shows data for a single channel such that data value 101 comprises 10 bits.
In regards to claim 16, Smith-Lacey/Schaefer/Liu teach all the limitations of claim 11 and further teach:
“wherein to output the set of bits including the processed first subset of bits and the second subset of bits, the processor is configured to: transmit the set of bits to a display; or store the set of bits in at least one of the memory, a buffer, or a cache”
Smith-Lacey Figure 1B, inter alia, illustrates output to the combining logic which must be able to store the bits for some time, at least during the combining. This is equivalent to a memory, buffer or cache.
In regards to claim 18, Smith-Lacey/Schaefer/Liu teach all the limitations of claim 1 and further teach:
“wherein the bit width of the set of bits is 10 bits, 12 bits, 14 bits, or 16 bits”
Smith-Lacey paragraph [0063] teaches each pixel in the image represented by the image data comprises 10 bits per channel. FIG. 1A shows data for a single channel such that data value 101 comprises 10 bits.
In regards to claim 29, Smith-Lacey/Schaefer/Liu teaches all the limitations of claim 11 and claim 29 contains similar limitations. Therefore, claim 29 is rejected for similar reasoning.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Smith-Lacey in view of Schaefer in view of Liu in view of Singh.
In regards to claim 19, Smith-Lacey/Schaefer/Liu/Singh teach all the limitations of claim 1 and further teach:
“wherein the apparatus is a wireless communication device comprising at least one of a transceiver or an antenna coupled to the processor, wherein to output the set of bits, the processor is configured to output the set of bits via at least one of the transceiver or the antenna”
Singh teaches a system and method for wireless communication of video data having partial compression (title). Singh Figure 2 teaches a receiver and transmitter having antennas. It would have been obvious for a person with ordinary skill in the art before the invention was effectively file to have modified Smith-Lacey/Schaefer in view of Singh to have included the features of “wherein the apparatus is a wireless communication device comprising at least one of a transceiver or an antenna coupled to the processor, wherein to output the set of bits, the processor is configured to output the set of bits via at least one of the transceiver or the antenna” because transmission of uncompressed video over a wireless channel is challenging because uncompressed video requires transmission of a larger amount of data than compressed video (Singh column 1 lines 39-44).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL E TEITELBAUM, Ph.D. whose telephone number is (571)270-5996. The examiner can normally be reached 8:30AM-5:00PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, John Miller can be reached at 571-272-7353. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL E TEITELBAUM, Ph.D./Primary Examiner, Art Unit 2422