DETAILED ACTION
This Action is responsive to the Amendments filed on 09/30/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Claims 1-30 are amended. Claims 1-30 are pending and have been examined.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-30 are rejected under 35 U.S.C. 103 as being unpatentable over Chun et al. (US 20190026028 A1)(cited by examiner in previous action)(hereafter referred to as Chun) further in view of Bains (US 20150317096 A1)(hereafter referred to as Bains).
Regarding Claim 1,
Chun discloses the following limitations:
An apparatus, comprising:
a memory controller (Decode & Control Module 264, Fig. 1) coupled to a memory module (DRAM Sub-System 200, Fig. 1) through a first channel (DRAM Bus 6, Fig. 1) and configured to access data stored in the memory module through the first channel (¶0031), and configured to perform operations comprising:
receiving (Fig. 6, step 620), from a host device (SoC 1, Fig. 1), a merged command (batch refresh command 320, Fig. 3) for performing at least a precharge operation (“a precharge (P) field” [0046] // ¶0033), a refresh operation (“a refresh (R) field” [0046] // ¶0034), and an activate operation (“the plurality of activate (A) fields” [0046] // ¶0033) on one or more rows (“four portions (e.g., rows) of each bank of the DRAM cell array” [0051] // Fig. 4) of the memory module (“At 620, the refresh scheduler 61 issues the batch memory refresh command to the dynamic volatile memory sub-system” [0059]) – As clarified in ¶0051 and Fig. 4, a “quadruple batch all bank” type of batch refresh command is performed on four rows of each memory bank--;
wherein the merged command includes a plurality of bits (P + R + A fields of Batch Refresh Command 320, Fig. 3 // Fig. 4) – As shown in Fig. 3, batch refresh command 320 includes plural fields (P, R, and A fields). Examiner considers the collective bits which form the P, R, and A fields of batch refresh command 320 as “a plurality of bits” included in batch refresh command 320--
of a format of the merged command (Figs. 4 + 5 // “The refresh scheduler 61 can issue a batch refresh command to refresh one, two, or four rows of one bank, one, two, or four rows of each bank of a group of banks, or one, two, or four rows of all banks” [0050] // ¶¶0051-54) – As shown in Figs. 4 + 5 and detailed in ¶¶0051-54, the aforementioned bits CA4-CA6 can be set to distinct values respectively corresponding to a particular number of rows and a particular number of banks on which to perform the batch refresh command. Examiner considers a batch refresh command performed on a respective number of rows and banks (e.g., ‘2X batch All Bank’ [0051] or ‘4X batch Per Bank’ [0053]) as a respective “format” of batch refresh command 320--
wherein the plurality of bits is repurposed (Fig. 4 // ¶¶0044-47; 0049 // Fig. 2, steps 230 + 232) – As shown in Fig. 4, bits CA4-CA6 are interpreted differently depending on whether the DRAM system is determined to be operating in a “normal” or a “batch” refresh mode (see Fig. 2 // ¶0044). Examiner accordingly considers the aforementioned bits CA4-CA6 (i.e., of batch refresh command 320) as being “repurposed” (i.e., interpreted differently) with respect to the same bits CA4-CA6 of normal refresh command 310 (see truth table 410 of Fig. 4)--
to indicate that … the refresh operation … should be performed (“a batch refresh command 320 … includes a precharge (P) field, the two refresh (R) fields … and the plurality of activate (A) fields” [0046] // Fig. 3 // ¶¶0033-34; 0045-48 // ¶0051) – As shown in Fig. 4 and described in ¶0046, bits included within the R fields of batch refresh command 320 (e.g., bits CA4-CA6 of Falling edge) can be set to indicate a refresh should be performed as part of performing the batch refresh command 320--
and
performing (Fig. 6, step 620) the precharge operation, the refresh operation, and the activate operation in accordance with receipt of the merged command (“the dynamic volatile memory sub-system … refreshes the DRAM cell array 210 as instructed” [0059])
Chun does not provide specific detail regarding the bits of the Precharge (P) and Activate (A) fields and therefore does not explicitly disclose the following limitations:
wherein the plurality of bits is repurposed to indicate that the precharge operation, the refresh operation, and the activate operation should be performed
However, Bains clarifies within the context of performing refresh operations on DRAM devices that repurposing bits of a command can indicate that a precharge operation and an active operation should be performed on a DRAM.
Bains discloses the following limitations:
wherein the plurality of bits (Fig. 4) is repurposed to indicate that the precharge operation (PreCharge (per Bank, all Banks), Fig. 4), the refresh operation (Refresh (per Bank), Fig. 4), and the activate operation (Activate, Fig. 4) should be performed (“Command truth table 400 represents one example of a truth table which includes multi-cycle commands… Of particular note in table 400 are the four-cycle Activate command, the two-cycle PreCharge command and the two Refresh commands (per Bank and all Bank, respectively)” [0037-38] // Fig. 4) – As shown in the Bain Fig. 4 truth table, various bits of a multi-cycle memory command (e.g., bits CA0 and CA1) are set to various values (i.e., are “repurposed”) to indicate respective memory operations to performed (e.g., CA0 and CA1 bits taking values of LL, LH, and HH, respectively, indicate “Refresh (per Bank)”, “Activate”, and “PreCharge (per Bank, all Banks)” operations should be performed, respectively.)
Chun discloses a DRAM memory device (DRAM Sub-System 200, Fig. 1) which is accessed using a merged memory command (see Figs. 3 + 4), which is considered analogous to the Bains DRAM memory device (Memory Resources 114, Fig. 1 // ¶0008) which is accessed using multi-cycle commands (see Fig. 4). Bains discloses a known method of repurposing bits of a multi-cycle command to indicate that a precharge, a refresh, and an activate operation should be performed (see limitation mappings above). It would have been obvious to one of ordinary skill in the art, as taught by Bains, to implement the method of repurposing bits of a multi-cycle command to indicate that a precharge, a refresh, and an activate operation should be performed in the DRAM memory device accessed using a merged memory command of Chun. A person of ordinary skill in the art would have recognized that applying the known technique of repurposing bits of a multi-cycle command to indicate that a precharge, a refresh, and an activate operation should be performed as taught by Bains to a DRAM memory device accessed using a merged memory command would have yielded the predictable result of a merged memory command including repurposed bits to indicate that a precharge, a refresh, and an activate operation should be performed. A merged memory command including repurposed bits to indicate that a precharge, a refresh, and an activate operation should be performed would have been expected to reduce command overhead for performing the precharge, refresh, and activate operations by using a single merged command to perform three memory operations. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to apply the known technique of repurposing bits of a multi-cycle command to indicate that a precharge, a refresh, and an activate operation should be performed, as taught by Bains, to the DRAM memory device accessed using a merged memory command of Chun. Doing so would predictably result in a merged memory command including repurposed bits to indicate that a precharge, a refresh, and an activate operation should be performed. See MPEP 2143, Rationale D.
Regarding Claim 2,
The same motivation to combine provided in Claim 1 is equally applicable to Claim 2. The combined teachings of Chun and Bains disclose the following limitations:
The apparatus of claim 1, wherein: the merged command is received by the memory controller from the host device via a command bus (Chun, DRAM bus 6, Fig. 1 // ¶0031)
Regarding Claim 3,
The same motivation to combine provided in Claim 1 is equally applicable to Claim 3. The combined teachings of Chun and Bains disclose the following limitations:
The apparatus of claim 1 (see Claim 1 limitation mappings above), wherein the format of the merged command is a read command format (Bains, “Read” Fig. 4) or a write command format (Bains, “Write” Fig. 4) – As shown in Bains Fig. 4, multi-cycle commands can additionally specify whether a Read or a Write should be performed on the DRAM.
Regarding Claim 4,
The same motivation to combine provided in Claim 1 is equally applicable to Claim 4. The combined teachings of Chun and Bains disclose the following limitations:
The apparatus of claim 3, wherein the merged command comprises
an indication that the precharge operation (Chun, Fig. 3 // “a precharge (P) field” [0046]) and the activate operation (Chun, “the plurality of activate fields” [0046]) are to be performed on a first row of a first bank of the memory module (Bains, Fig. 4 // “BA# bits to represent bank address information, R# bits to represent row address information” [0038]) – As shown in Bains Fig. 4, certain bits of multi-cycle command specify on which banks and which rows a memory operation should be performed. As shown in Fig. 4, “Activate” is performed on addresses specified by bits BA0-2 and R0-12 (i.e., on at least “a first row of a first bank”); and “PreCharge” is performed on all Banks (i.e., on at least “a first row of a first bank”)--
and that the refresh operation (Chun, “the two refresh (R) fields” [0046]) is to be performed (Chun, “a batch refresh command 320 … includes a precharge (P), the two refresh fields (R), … and the plurality of activate (A) fields” [0046] // ¶0048) – As shown in Chun Fig. 3 and detailed in ¶0046, a batch refresh command can include each of a precharge field, a plurality of activate fields, and two refresh fields, which examiner considers as “indication[s]” that the respective operations should be performed.—
on the first bank of the memory module. (Chun, Fig. 5, “2X batch All Bank Refresh” // Fig. 4, bits CA0-CA6, falling edge // “the two refresh (R) fields identifying the two portions of the DRAM cell array to be refreshed” [0046] // ¶¶0045-46; 0050-51) – As detailed in Chun ¶¶0045-46 and shown in Fig. 4, bits CA0-CA6 of the falling clock edge (e.g., BA0-BA3, 2X, 4X, and AB) specify “the two portions” (i.e., the two rows of a bank; see ¶0045) to be refreshed. As clarified in Chun ¶0050-51, when the ‘all bank refresh flag bit (AB)’ of batch refresh command 320 is set to high, a refresh operation will be performed on all banks (i.e., at least a “first bank” of the DRAM)—
Regarding Claim 5,
The same motivation to combine provided in Claim 1 is equally applicable to Claim 5. The combined teachings of Chun and Bains disclose the following limitations:
The apparatus of claim 1, wherein the format of the merged command is a precharge command format (Chun, Fig. 3 // “Note that the precharge (P) … fields are not always present; they are generated in response to the need to read/write rows in the DRAM” [0048] // ¶¶0033; 0046) -- As shown in Chun Fig. 3 and detailed in ¶0046, a single batch refresh command 320 includes each of precharge (P), refresh (R), and activate (A) fields respectively causing precharge, refresh, and activate operations to be performed as part of the batch refresh command. Examiner considers a format of a merged command which causes a precharge operation to generally be performed, such as the 4X batch All Bank Refresh type of batch refresh command 320 of Chun, as reading on the claimed concept of “a precharge command format”, under the BRI of the claimed language.
Regarding Claim 6,
The same motivation to combine provided in Claim 1 is equally applicable to Claim 6. The combined teachings of Chun and Bains disclose the following limitations:
The apparatus of claim 5 (see Claim 5 limitation mappings above), wherein the merged command comprises
an indication that the precharge operation is to be performed (Chun, Fig. 3 // “a precharge (P) field” [0046]) on a first row of a first bank of the memory module (Bains, Fig. 4 // “BA# bits to represent bank address information, R# bits to represent row address information” [0038]) –– As shown in Bains Fig. 4, certain bits of multi-cycle command specify on which banks and which rows a memory operation should be performed. As shown in Bains Fig. 4, “PreCharge” is performed on all Banks (i.e., on at least “a first row of a first bank”)--,
that the refresh operation (Chun, “the two refresh (R) fields” [0046]) is to be performed (Chun, “a batch refresh command 320 … includes a precharge (P), the two refresh fields (R), … and the plurality of activate (A) fields” [0046] // ¶0048) – As shown in Chun Fig. 3 and detailed in ¶0046, a batch refresh command can include each of a precharge field, a plurality of activate fields, and two refresh fields, which examiner considers as “indication[s]” that the respective operations should be performed.—
on the first bank of the memory module (Chun, Fig. 5, “2X batch All Bank Refresh” // Fig. 4, bits CA0-CA6, falling edge // “the two refresh (R) fields identifying the two portions of the DRAM cell array to be refreshed” [0046] // ¶¶0045-46; 0050-51) – As detailed in Chun ¶¶0045-46 and shown in Fig. 4, bits CA0-CA6 of the falling clock edge (e.g., BA0-BA3, 2X, 4X, and AB) specify “the two portions” (i.e., the two rows of a bank; see ¶0045) to be refreshed. As clarified in Chun ¶0050-51, when the ‘all bank refresh flag bit (AB)’ of batch refresh command 320 is set to high, a refresh operation will be performed on all banks (i.e., at least a “first bank” of the DRAM)—
, and
that the activate operation is to be performed (Chun, “the plurality of activate fields” [0046]) on the first row of the first bank of the memory module (Bains, Fig. 4) -- As shown in Bains Fig. 4, “Activate” is performed on addresses specified by bits BA0-2 and R0-12 (i.e., on at least “a first row of a first bank”)
Regarding Claim 7,
The same motivation to combine provided in Claim 1 is equally applicable to Claim 7. The combined teachings of Chun and Bains disclose the following limitations:
The apparatus of claim 5 (see Claim 5 limitation mappings above), wherein the merged command comprises:
a first indication that the precharge operation is to be performed on a first row of a first bank of the memory module and a second row, corresponding to the first row, of a second bank of the memory module, that the refresh operation is to be performed on the first bank and the second bank, and the activate operation is to be performed on the first row of the first bank of the memory module,
wherein the first bank and the second bank belong to a bank pair (Chun) – Examiner considers the first two (of all) banks refreshed by a “2X batch All Bank Refresh” batch refresh command as “a bank pair”.;
a second indication that the precharge operation is to be performed on the first row of the first bank of the memory module and the second row of the second bank of the memory module, that the refresh operation is to be performed on the first bank and the second bank of the memory module, and that the activate operation is to be performed on the second row of the second bank of the memory module;
or (see MPEP 2143.03)
a third indication that the precharge operation is to be performed (Chun, Fig. 3 // “a precharge (P) field” [0046]) on the first row of the first bank of the memory module and the second row of the second bank of the memory module (Bains, Fig. 4 // “BA# bits to represent bank address information, R# bits to represent row address information” [0038]) –– As shown in Bains Fig. 4, certain bits of multi-cycle command specify on which banks and which rows a memory operation should be performed. As shown in Bains Fig. 4, “PreCharge” is performed on all Banks (i.e., on at least “the first row of the first bank” and “the second row of the second bank”)--,
that the refresh operation is to be performed (Chun, “the two refresh (R) fields” [0046]) on the first bank and the second bank (Chun, Fig. 5, “2X batch All Bank Refresh” // ¶¶0050-51) – As detailed in Chun, when the ‘all bank refresh flag bit (AB)’ of batch refresh command 320 is set to high, a refresh operation will be performed on all banks (i.e., at least a “first bank” and a “second bank” of the DRAM)—, and
that the activate operation is to be performed (Chun, “the plurality of activate fields” [0046] // “a batch refresh command 320 … includes a precharge (P), the two refresh fields (R), … and the plurality of activate (A) fields” [0046] // ¶0048) – As shown in Chun Fig. 3 and detailed in ¶0046, a batch refresh command can include each of a precharge field, a plurality of activate fields, and two refresh fields, which examiner considers as “indication[s]” that the respective operations should be performed-- on the first row of the first bank of the memory module and the second row of the second bank of the memory module (Bains, Fig. 4) -- As shown in Bains Fig. 4, “Activate” is performed on addresses specified by bits BA0-2 and R0-12 (i.e., on at least “the first row of the first bank” and “the second row of the second bank”)
Regarding Claim 8,
The same motivation to combine provided in Claim 1 is equally applicable to Claim 8. The combined teachings of Chun and Bains disclose the following limitations:
The apparatus of claim 1, wherein the format of the merged command is a refresh command format (Chun, Fig. 3 // “a batch refresh command 320 … includes … the two refresh (R) fields” [0046]) -- As shown in Fig. 3 and detailed in ¶0046, batch refresh command 320 is formatted to include at least a refresh (R) field. Examiner considers a format of a merged command which causes a refresh operation to generally be performed, such as the 4X batch All Bank Refresh type of batch refresh command 320 of Chun, as reading on the claimed concept of “a refresh command format”, under the BRI of the claimed language.
Regarding Claim 9,
The same motivation to combine provided in Claim 1 is equally applicable to Claim 7. The combined teachings of Chun and Bains disclose the following limitations:
The apparatus of claim 8 (see Claim 8 limitation mappings above), wherein the merged command comprises:
a first indication that the precharge operation is to be performed on a first row of a first bank of the memory module and a second row, corresponding to the first row, of a second bank of the memory module, that the refresh operation is to be performed on the first bank and the second bank, and the activate operation is to be performed on the first row of the first bank of the memory module,
wherein the first bank and the second bank belong to a bank pair (Chun) – Examiner considers the first two (of all) banks refreshed by a “2X batch All Bank Refresh” batch refresh command as “a bank pair”.;
a second indication that the precharge operation is to be performed on the first row of the first bank of the memory module and the second row of the second bank of the memory module, that the refresh operation is to be performed on the first bank and the second bank of the memory module, and that the activate operation is to be performed on the second row of the second bank of the memory module;
or (see MPEP 2143.03)
a third indication that the precharge operation is to be performed (Chun, Fig. 3 // “a precharge (P) field” [0046]) on the first row of the first bank of the memory module and the second row of the second bank of the memory module (Bains, Fig. 4 // “BA# bits to represent bank address information, R# bits to represent row address information” [0038]) –– As shown in Bains Fig. 4, certain bits of multi-cycle command specify on which banks and which rows a memory operation should be performed. As shown in Bains Fig. 4, “PreCharge” is performed on all Banks (i.e., on at least “the first row of the first bank” and “the second row of the second bank”)--,
that the refresh operation is to be performed (Chun, “the two refresh (R) fields” [0046]) on the first bank and the second bank (Chun, Fig. 5, “2X batch All Bank Refresh” // ¶¶0050-51) – As detailed in Chun, when the ‘all bank refresh flag bit (AB)’ of batch refresh command 320 is set to high, a refresh operation will be performed on all banks (i.e., at least a “first bank” and a “second bank” of the DRAM)—, and
that the activate operation is to be performed (Chun, “the plurality of activate fields” [0046] // “a batch refresh command 320 … includes a precharge (P), the two refresh fields (R), … and the plurality of activate (A) fields” [0046] // ¶0048) – As shown in Chun Fig. 3 and detailed in ¶0046, a batch refresh command can include each of a precharge field, a plurality of activate fields, and two refresh fields, which examiner considers as “indication[s]” that the respective operations should be performed-- on the first row of the first bank of the memory module and the second row of the second bank of the memory module (Bains, Fig. 4) -- As shown in Bains Fig. 4, “Activate” is performed on addresses specified by bits BA0-2 and R0-12 (i.e., on at least “the first row of the first bank” and “the second row of the second bank”)
Regarding Claim 10,
Chun discloses the following limitations:
A method, comprising:
receiving (Fig. 6, step 620), from a host device (SoC 1, Fig. 1) by a memory controller (Decode & Control Module 264, Fig. 1) coupled to a memory module (DRAM Sub-System 200, Fig. 1) through a first channel (DRAM Bus 6, Fig. 1) and configured to access data stored in the memory module through the first channel (¶0031),
a merged command (batch refresh command 320, Fig. 3) for performing at least a precharge operation (“precharging” [0033]), a refresh operation (“Refresh” [0034]), and an activate operation (“Activation” [0033]) on one or more rows of the memory module (“Refresh is the act of opening a row, then immediately precharging it” [0034] // “With batch refresh, multiple rows (e.g., 2x or 4x in all banks or in a single (per) bank) can be refreshed using a single command” [0034] // ¶¶0033-34; 0059) – As shown in Fig. 6 (see also ¶0059), SoC 1 generates and transmits a batch refresh command to DRAM 200. As disclosed in ¶0034, “refresh” (i.e., “a refresh operation”) includes “opening a row” (i.e., “an activate operation”; see also ¶0033) and “immediately precharging” (i.e., “a precharge operation”; see also ¶0033) the row. As clarified in ¶0034, a batch refresh command enables “multiple rows” to be refreshed using a single command--;
wherein the merged command includes a plurality of bits (P + R + A fields of Batch Refresh Command 320, Fig. 3 // Fig. 4) – As shown in Fig. 3, batch refresh command 320 includes plural fields (P, R, and A fields). Examiner considers the collective bits which form the P, R, and A fields of batch refresh command 320 as “a plurality of bits” included in batch refresh command 320--
of a format of the merged command (Figs. 4 + 5 // “The refresh scheduler 61 can issue a batch refresh command to refresh one, two, or four rows of one bank, one, two, or four rows of each bank of a group of banks, or one, two, or four rows of all banks” [0050] // ¶¶0051-54) – As shown in Figs. 4 + 5 and detailed in ¶¶0051-54, the aforementioned bits CA4-CA6 can be set to distinct values respectively corresponding to a particular number of rows and a particular number of banks on which to perform the batch refresh command. Examiner considers a batch refresh command performed on a respective number of rows and banks (e.g., ‘2X batch All Bank’ [0051] or ‘4X batch Per Bank’ [0053]) as a respective “format” of batch refresh command 320--
wherein the plurality of bits is repurposed (Fig. 4 // ¶¶0044-47; 0049 // Fig. 2, steps 230 + 232) – As shown in Fig. 4, bits CA4-CA6 are interpreted differently depending on whether the DRAM system is determined to be operating in a “normal” or a “batch” refresh mode (see Fig. 2 // ¶0044). Examiner accordingly considers the aforementioned bits CA4-CA6 (i.e., of batch refresh command 320) as being “repurposed” (i.e., interpreted differently) with respect to the same bits CA4-CA6 of normal refresh command 310 (see truth table 410 of Fig. 4)--
to indicate that … the refresh operation … should be performed (“a batch refresh command 320 … includes a precharge (P) field, the two refresh (R) fields … and the plurality of activate (A) fields” [0046] // Fig. 3 // ¶¶0033-34; 0045-48 // ¶0051) – As shown in Fig. 4 and described in ¶0046, bits included within the R fields of batch refresh command 320 (e.g., bits CA4-CA6 of Falling edge) can be set to indicate a refresh should be performed as part of performing the batch refresh command 320--
and
performing (Fig. 6, step 620) the precharge operation, the refresh operation, and the activate operation in accordance with receipt of the merged command (“the DRAM sub-system 200, refreshes the DRAM cell array 210 as instructed.” [0059]) – As clarified in ¶0059, DRAM 200 is refreshed after receiving a batch refresh command from SoC 1. As previously discussed (see limitation mappings above), a refresh includes an activate operation immediately followed by a precharge operation. One of ordinary skill in the art would therefore understand that refreshing DRAM 200 “as instructed” by a batch refresh command at least includes performing “the precharge operation”, “the refresh operation”, and “the activate operation” “in accordance with” (e.g., on rows indicated by) the batch refresh command.
Chun does not provide specific detail regarding the bits of the Precharge (P) and Activate (A) fields and therefore does not explicitly disclose the following limitations:
wherein the plurality of bits is repurposed to indicate that the precharge operation, the refresh operation, and the activate operation should be performed
However, Bains clarifies within the context of performing refresh operations on DRAM devices that repurposing bits of a command can indicate that a precharge operation and an active operation should be performed on a DRAM.
Bains discloses the following limitations:
wherein the plurality of bits (Fig. 4) is repurposed to indicate that the precharge operation (PreCharge (per Bank, all Banks), Fig. 4), the refresh operation (Refresh (per Bank), Fig. 4), and the activate operation (Activate, Fig. 4) should be performed (“Command truth table 400 represents one example of a truth table which includes multi-cycle commands… Of particular note in table 400 are the four-cycle Activate command, the two-cycle PreCharge command and the two Refresh commands (per Bank and all Bank, respectively)” [0037-38] // Fig. 4) – As shown in the Bain Fig. 4 truth table, various bits of a multi-cycle memory command (e.g., bits CA0 and CA1) are set to various values (i.e., are “repurposed”) to indicate respective memory operations to performed (e.g., CA0 and CA1 bits taking values of LL, LH, and HH, respectively, indicate “Refresh (per Bank)”, “Activate”, and “PreCharge (per Bank, all Banks)” operations should be performed, respectively.)
Chun discloses a DRAM memory device (DRAM Sub-System 200, Fig. 1) which is accessed using a merged memory command (see Figs. 3 + 4), which is considered analogous to the Bains DRAM memory device (Memory Resources 114, Fig. 1 // ¶0008) which is accessed using multi-cycle commands (see Fig. 4). Bains discloses a known method of repurposing bits of a multi-cycle command to indicate that a precharge, a refresh, and an activate operation should be performed (see limitation mappings above). It would have been obvious to one of ordinary skill in the art, as taught by Bains, to implement the method of repurposing bits of a multi-cycle command to indicate that a precharge, a refresh, and an activate operation should be performed in the DRAM memory device accessed using a merged memory command of Chun. A person of ordinary skill in the art would have recognized that applying the known technique of repurposing bits of a multi-cycle command to indicate that a precharge, a refresh, and an activate operation should be performed as taught by Bains to a DRAM memory device accessed using a merged memory command would have yielded the predictable result of a merged memory command including repurposed bits to indicate that a precharge, a refresh, and an activate operation should be performed. A merged memory command including repurposed bits to indicate that a precharge, a refresh, and an activate operation should be performed would have been expected to reduce command overhead for performing the precharge, refresh, and activate operations by using a single merged command to perform three memory operations. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to apply the known technique of repurposing bits of a multi-cycle command to indicate that a precharge, a refresh, and an activate operation should be performed, as taught by Bains, to the DRAM memory device accessed using a merged memory command of Chun. Doing so would predictably result in a merged memory command including repurposed bits to indicate that a precharge, a refresh, and an activate operation should be performed. See MPEP 2143, Rationale D.
Regarding Claim 11,
The same motivation to combine provided in Claim 10 is equally applicable to Claim 11. The combined teachings of Chun and Bains disclose the following limitations:
The method of claim 10, wherein: the merged command is received by the memory controller from the host device via a command bus (Chun, DRAM bus 6, Fig. 1 // ¶0031)
Regarding Claim 12,
The same motivation to combine provided in Claim 10 is equally applicable to Claim 12. The combined teachings of Chun and Bains disclose the following limitations:
The method of claim 10 (see Claim 10 limitation mappings above), wherein the format of the merged command is a read command format (Bains, “Read” Fig. 4) or a write command format (Bains, “Write” Fig. 4) – As shown in Bains Fig. 4, multi-cycle commands can additionally specify whether a Read or a Write should be performed on the DRAM.
Regarding Claim 13,
The same motivation to combine provided in Claim 10 is equally applicable to Claim 13. The combined teachings of Chun and Bains disclose the following limitations:
The method of claim 12, wherein the merged command comprises
an indication that the precharge operation (Chun, Fig. 3 // “a precharge (P) field” [0046]) and the activate operation (Chun, “the plurality of activate fields” [0046]) are to be performed on a first row of a first bank of the memory module (Bains, Fig. 4 // “BA# bits to represent bank address information, R# bits to represent row address information” [0038]) – As shown in Bains Fig. 4, certain bits of multi-cycle command specify on which banks and which rows a memory operation should be performed. As shown in Fig. 4, “Activate” is performed on addresses specified by bits BA0-2 and R0-12 (i.e., on at least “a first row of a first bank”); and “PreCharge” is performed on all Banks (i.e., on at least “a first row of a first bank”)--
and that the refresh operation (Chun, “the two refresh (R) fields” [0046]) is to be performed (Chun, “a batch refresh command 320 … includes a precharge (P), the two refresh fields (R), … and the plurality of activate (A) fields” [0046] // ¶0048) – As shown in Chun Fig. 3 and detailed in ¶0046, a batch refresh command can include each of a precharge field, a plurality of activate fields, and two refresh fields, which examiner considers as “indication[s]” that the respective operations should be performed.—
on the first bank of the memory module. (Chun, Fig. 5, “2X batch All Bank Refresh” // Fig. 4, bits CA0-CA6, falling edge // “the two refresh (R) fields identifying the two portions of the DRAM cell array to be refreshed” [0046] // ¶¶0045-46; 0050-51) – As detailed in Chun ¶¶0045-46 and shown in Fig. 4, bits CA0-CA6 of the falling clock edge (e.g., BA0-BA3, 2X, 4X, and AB) specify “the two portions” (i.e., the two rows of a bank; see ¶0045) to be refreshed. As clarified in Chun ¶0050-51, when the ‘all bank refresh flag bit (AB)’ of batch refresh command 320 is set to high, a refresh operation will be performed on all banks (i.e., at least a “first bank” of the DRAM)—
Regarding Claim 14,
The same motivation to combine provided in Claim 10 is equally applicable to Claim 14. The combined teachings of Chun and Bains disclose the following limitations:
The method of claim 10, wherein the format of the merged command is a precharge command format (Chun, Fig. 3 // “Note that the precharge (P) … fields are not always present; they are generated in response to the need to read/write rows in the DRAM” [0048] // ¶¶0033; 0046) -- As shown in Chun Fig. 3 and detailed in ¶0046, a single batch refresh command 320 includes each of precharge (P), refresh (R), and activate (A) fields respectively causing precharge, refresh, and activate operations to be performed as part of the batch refresh command. Examiner considers a format of a merged command which causes a precharge operation to generally be performed, such as the 4X batch All Bank Refresh type of batch refresh command 320 of Chun, as reading on the claimed concept of “a precharge command format”, under the BRI of the claimed language.
Regarding Claim 15,
The same motivation to combine provided in Claim 10 is equally applicable to Claim 15. The combined teachings of Chun and Bains disclose the following limitations:
The method of claim 14 (see Claim 14 limitation mappings above), wherein the merged command comprises
an indication that the precharge operation is to be performed (Chun, Fig. 3 // “a precharge (P) field” [0046]) on a first row of a first bank of the memory module (Bains, Fig. 4 // “BA# bits to represent bank address information, R# bits to represent row address information” [0038]) –– As shown in Bains Fig. 4, certain bits of multi-cycle command specify on which banks and which rows a memory operation should be performed. As shown in Bains Fig. 4, “PreCharge” is performed on all Banks (i.e., on at least “a first row of a first bank”)--,
that the refresh operation (Chun, “the two refresh (R) fields” [0046]) is to be performed (Chun, “a batch refresh command 320 … includes a precharge (P), the two refresh fields (R), … and the plurality of activate (A) fields” [0046] // ¶0048) – As shown in Chun Fig. 3 and detailed in ¶0046, a batch refresh command can include each of a precharge field, a plurality of activate fields, and two refresh fields, which examiner considers as “indication[s]” that the respective operations should be performed.—
on the first bank of the memory module (Chun, Fig. 5, “2X batch All Bank Refresh” // Fig. 4, bits CA0-CA6, falling edge // “the two refresh (R) fields identifying the two portions of the DRAM cell array to be refreshed” [0046] // ¶¶0045-46; 0050-51) – As detailed in Chun ¶¶0045-46 and shown in Fig. 4, bits CA0-CA6 of the falling clock edge (e.g., BA0-BA3, 2X, 4X, and AB) specify “the two portions” (i.e., the two rows of a bank; see ¶0045) to be refreshed. As clarified in Chun ¶0050-51, when the ‘all bank refresh flag bit (AB)’ of batch refresh command 320 is set to high, a refresh operation will be performed on all banks (i.e., at least a “first bank” of the DRAM)—
, and
that the activate operation is to be performed (Chun, “the plurality of activate fields” [0046]) on the first row of the first bank of the memory module (Bains, Fig. 4) -- As shown in Bains Fig. 4, “Activate” is performed on addresses specified by bits BA0-2 and R0-12 (i.e., on at least “a first row of a first bank”)
Regarding Claim 16,
The same motivation to combine provided in Claim 10 is equally applicable to Claim 16. The combined teachings of Chun and Bains disclose the following limitations:
The method of claim 14 (see Claim 14 limitation mappings above), wherein the merged command comprises:
a first indication that the precharge operation is to be performed on a first row of a first bank of the memory module and a second row, corresponding to the first row, of a second bank of the memory module, that the refresh operation is to be performed on the first bank and the second bank, and the activate operation is to be performed on the first row of the first bank of the memory module,
wherein the first bank and the second bank belong to a bank pair (Chun) – Examiner considers the first two (of all) banks refreshed by a “2X batch All Bank Refresh” batch refresh command as “a bank pair”.;
a second indication that the precharge operation is to be performed on the first row of the first bank of the memory module and the second row of the second bank of the memory module, that the refresh operation is to be performed on the first bank and the second bank of the memory module, and that the activate operation is to be performed on the second row of the second bank of the memory module;
or (see MPEP 2143.03)
a third indication that the precharge operation is to be performed (Chun, Fig. 3 // “a precharge (P) field” [0046]) on the first row of the first bank of the memory module and the second row of the second bank of the memory module (Bains, Fig. 4 // “BA# bits to represent bank address information, R# bits to represent row address information” [0038]) –– As shown in Bains Fig. 4, certain bits of multi-cycle command specify on which banks and which rows a memory operation should be performed. As shown in Bains Fig. 4, “PreCharge” is performed on all Banks (i.e., on at least “the first row of the first bank” and “the second row of the second bank”)--,
that the refresh operation is to be performed (Chun, “the two refresh (R) fields” [0046]) on the first bank and the second bank (Chun, Fig. 5, “2X batch All Bank Refresh” // ¶¶0050-51) – As detailed in Chun, when the ‘all bank refresh flag bit (AB)’ of batch refresh command 320 is set to high, a refresh operation will be performed on all banks (i.e., at least a “first bank” and a “second bank” of the DRAM)—, and
that the activate operation is to be performed (Chun, “the plurality of activate fields” [0046] // “a batch refresh command 320 … includes a precharge (P), the two refresh fields (R), … and the plurality of activate (A) fields” [0046] // ¶0048) – As shown in Chun Fig. 3 and detailed in ¶0046, a batch refresh command can include each of a precharge field, a plurality of activate fields, and two refresh fields, which examiner considers as “indication[s]” that the respective operations should be performed-- on the first row of the first bank of the memory module and the second row of the second bank of the memory module (Bains, Fig. 4) -- As shown in Bains Fig. 4, “Activate” is performed on addresses specified by bits BA0-2 and R0-12 (i.e., on at least “the first row of the first bank” and “the second row of the second bank”)
Regarding Claim 17,
The same motivation to combine provided in Claim 10 is equally applicable to Claim 17. The combined teachings of Chun and Bains disclose the following limitations:
The method of claim 10, wherein the format of the merged command is a refresh command format (Chun, Fig. 3 // “a batch refresh command 320 … includes … the two refresh (R) fields” [0046]) -- As shown in Fig. 3 and detailed in ¶0046, batch refresh command 320 is formatted to include at least a refresh (R) field. Examiner considers a format of a merged command which causes a refresh operation to generally be performed, such as the 4X batch All Bank Refresh type of batch refresh command 320 of Chun, as reading on the claimed concept of “a refresh command format”, under the BRI of the claimed language.
Regarding Claim 18,
The same motivation to combine provided in Claim 10 is equally applicable to Claim 16. The combined teachings of Chun and Bains disclose the following limitations:
The method of claim 17 (see Claim 17 limitation mappings above), wherein the merged command comprises:
a first indication that the precharge operation is to be performed on a first row of a first bank of the memory module and a second row, corresponding to the first row, of a second bank of the memory module, that the refresh operation is to be performed on the first bank and the second bank, and the activate operation is to be performed on the first row of the first bank of the memory module,
wherein the first bank and the second bank belong to a bank pair (Chun) – Examiner considers the first two (of all) banks refreshed by a “2X batch All Bank Refresh” batch refresh command as “a bank pair”.;
a second indication that the precharge operation is to be performed on the first row of the first bank of the memory module and the second row of the second bank of the memory module, that the refresh operation is to be performed on the first bank and the second bank of the memory module, and that the activate operation is to be performed on the second row of the second bank of the memory module;
or (see MPEP 2143.03)
a third indication that the precharge operation is to be performed (Chun, Fig. 3 // “a precharge (P) field” [0046]) on the first row of the first bank of the memory module and the second row of the second bank of the memory module (Bains, Fig. 4 // “BA# bits to represent bank address information, R# bits to represent row address information” [0038]) –– As shown in Bains Fig. 4, certain bits of multi-cycle command specify on which banks and which rows a memory operation should be performed. As shown in Bains Fig. 4, “PreCharge” is performed on all Banks (i.e., on at least “the first row of the first bank” and “the second row of the second bank”)--,
that the refresh operation is to be performed (Chun, “the two refresh (R) fields” [0046]) on the first bank and the second bank (Chun, Fig. 5, “2X batch All Bank Refresh” // ¶¶0050-51) – As detailed in Chun, when the ‘all bank refresh flag bit (AB)’ of batch refresh command 320 is set to high, a refresh operation will be performed on all banks (i.e., at least a “first bank” and a “second bank” of the DRAM)—, and
that the activate operation is to be performed (Chun, “the plurality of activate fields” [0046] // “a batch refresh command 320 … includes a precharge (P), the two refresh fields (R), … and the plurality of activate (A) fields” [0046] // ¶0048) – As shown in Chun Fig. 3 and detailed in ¶0046, a batch refresh command can include each of a precharge field, a plurality of activate fields, and two refresh fields, which examiner considers as “indication[s]” that the respective operations should be performed-- on the first row of the first bank of the memory module and the second row of the second bank of the memory module (Bains, Fig. 4) -- As shown in Bains Fig. 4, “Activate” is performed on addresses specified by bits BA0-2 and R0-12 (i.e., on at least “the first row of the first bank” and “the second row of the second bank”)
Regarding Claim 19,
Chun discloses the following limitations:
An apparatus, comprising:
a host device (SoC 1, Fig. 1) configured to communicate with a memory module (DRAM Sub-System 200, Fig. 1) through a channel (DRAM Bus 6, Fig. 1), the host device comprising a memory controller (DRAM Memory Controller 60, Fig. 1) coupled to the channel, the memory controller configured perform operations including:
generating (Fig. 6, step 610) a merged command (batch refresh command 320, Fig. 3) for performing at least a precharge operation (“precharging” [0033]), a refresh operation (“Refresh” [0034]), and an activate operation (“Activation” [0033]) on one or more rows of the memory module (“Refresh is the act of opening a row, then immediately precharging it” [0034] // “With batch refresh, multiple rows (e.g., 2x or 4x in all banks or in a single (per) bank) can be refreshed using a single command” [0034] // ¶¶0033-34; 0059) – As shown in Fig. 6 (see also ¶0059), SoC 1 generates and transmits a batch refresh command to DRAM 200. As disclosed in ¶0034, “refresh” (i.e., “a refresh operation”) includes “opening a row” (i.e., “an activate operation”; see also ¶0033) and “immediately precharging” (i.e., “a precharge operation”; see also ¶0033) the row. As clarified in ¶0034, a batch refresh command enables “multiple rows” to be refreshed using a single command--;
wherein the merged command includes a plurality of bits (P + R + A fields of Batch Refresh Command 320, Fig. 3 // Fig. 4) – As shown in Fig. 3, batch refresh command 320 includes plural fields (P, R, and A fields). Examiner considers the collective bits which form the P, R, and A fields of batch refresh command 320 as “a plurality of bits” included in batch refresh command 320--
of a format of the merged command (Figs. 4 + 5 // “The refresh scheduler 61 can issue a batch refresh command to refresh one, two, or four rows of one bank, one, two, or four rows of each bank of a group of banks, or one, two, or four rows of all banks” [0050] // ¶¶0051-54) – As shown in Figs. 4 + 5 and detailed in ¶¶0051-54, the aforementioned bits CA4-CA6 can be set to distinct values respectively corresponding to a particular number of rows and a particular number of banks on which to perform the batch refresh command. Examiner considers a batch refresh command performed on a respective number of rows and banks (e.g., ‘2X batch All Bank’ [0051] or ‘4X batch Per Bank’ [0053]) as a respective “format” of batch refresh command 320--
wherein the plurality of bits is repurposed (Fig. 4 // ¶¶0044-47; 0049 // Fig. 2, steps 230 + 232) – As shown in Fig. 4, bits CA4-CA6 are interpreted differently depending on whether the DRAM system is determined to be operating in a “normal” or a “batch” refresh mode (see Fig. 2 // ¶0044). Examiner accordingly considers the aforementioned bits CA4-CA6 (i.e., of batch refresh command 320) as being “repurposed” (i.e., interpreted differently) with respect to the same bits CA4-CA6 of normal refresh command 310 (see truth table 410 of Fig. 4)--
for indicating that … the refresh operation … should be performed (“a batch refresh command 320 … includes a precharge (P) field, the two refresh (R) fields … and the plurality of activate (A) fields” [0046] // Fig. 3 // ¶¶0033-34; 0045-48 // ¶0051) – As shown in Fig. 4 and described in ¶0046, bits included within the R fields of batch refresh command 320 (e.g., bits CA4-CA6 of Falling edge) can be set to indicate a refresh should be performed as part of performing the batch refresh command 320--; and
transmitting (Fig. 6, step 620) the merged command to the memory module (“At 620, the refresh scheduler 61 issues the batch memory refresh command to the dynamic volatile memory sub-system” [0059])
Chun does not provide specific detail regarding the bits of the Precharge (P) and Activate (A) fields and therefore does not explicitly disclose the following limitations:
wherein the plurality of bits is repurposed for indicating that the precharge operation, the refresh operation, and the activate operation should be performed
However, Bains clarifies within the context of performing refresh operations on DRAM devices that repurposing bits of a command can indicate that a precharge operation and an active operation should be performed on a DRAM.
Bains discloses the following limitations:
wherein the plurality of bits (Fig. 4) is repurposed for indicating that the precharge operation (PreCharge (per Bank, all Banks), Fig. 4), the refresh operation (Refresh (per Bank), Fig. 4), and the activate operation (Activate, Fig. 4) should be performed (“Command truth table 400 represents one example of a truth table which includes multi-cycle commands… Of particular note in table 400 are the four-cycle Activate command, the two-cycle PreCharge command and the two Refresh commands (per Bank and all Bank, respectively)” [0037-38] // Fig. 4) – As shown in the Bain Fig. 4 truth table, various bits of a multi-cycle memory command (e.g., bits CA0 and CA1) are set to various values (i.e., are “repurposed”) to indicate respective memory operations to performed (e.g., CA0 and CA1 bits taking values of LL, LH, and HH, respectively, indicate “Refresh (per Bank)”, “Activate”, and “PreCharge (per Bank, all Banks)” operations should be performed, respectively.)
Chun discloses a DRAM memory device (DRAM Sub-System 200, Fig. 1) which is accessed using a merged memory command (see Figs. 3 + 4), which is considered analogous to the Bains DRAM memory device (Memory Resources 114, Fig. 1 // ¶0008) which is accessed using multi-cycle commands (see Fig. 4). Bains discloses a known method of repurposing bits of a multi-cycle command to indicate that a precharge, a refresh, and an activate operation should be performed (see limitation mappings above). It would have been obvious to one of ordinary skill in the art, as taught by Bains, to implement the method of repurposing bits of a multi-cycle command to indicate that a precharge, a refresh, and an activate operation should be performed in the DRAM memory device accessed using a merged memory command of Chun. A person of ordinary skill in the art would have recognized that applying the known technique of repurposing bits of a multi-cycle command to indicate that a precharge, a refresh, and an activate operation should be performed as taught by Bains to a DRAM memory device accessed using a merged memory command would have yielded the predictable result of a merged memory command including repurposed bits to indicate that a precharge, a refresh, and an activate operation should be performed. A merged memory command including repurposed bits to indicate that a precharge, a refresh, and an activate operation should be performed would have been expected to reduce command overhead for performing the precharge, refresh, and activate operations by using a single merged command to perform three memory operations. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to apply the known technique of repurposing bits of a multi-cycle command to indicate that a precharge, a refresh, and an activate operation should be performed, as taught by Bains, to the DRAM memory device accessed using a merged memory command of Chun. Doing so would predictably result in a merged memory command including repurposed bits to indicate that a precharge, a refresh, and an activate operation should be performed. See MPEP 2143, Rationale D.
Regarding Claim 20,
The same motivation to combine provided in Claim 19 is equally applicable to Claim 20. The combined teachings of Chun and Bains disclose the following limitations:
The apparatus of claim 19, wherein: the merged command is transmitted by the host device to the memory module via a command bus of the channel (Chun, DRAM bus 6, Fig. 1 // “The DRAM bus 6 carries data 6d and address/control information 6c to the PHY” [0031])
Regarding Claim 21,
The same motivation to combine provided in Claim 19 is equally applicable to Claim 21. The combined teachings of Chun and Bains disclose the following limitations:
The apparatus of claim 19 (see Claim 19 limitation mappings above), wherein the format of the merged command is a read command format (Bains, “Read” Fig. 4) or a write command format (Bains, “Write” Fig. 4) – As shown in Bains Fig. 4, multi-cycle commands can additionally specify whether a Read or a Write should be performed on the DRAM.
Regarding Claim 22,
The same motivation to combine provided in Claim 19 is equally applicable to Claim 22. The combined teachings of Chun and Bains disclose the following limitations:
The apparatus of claim 21, wherein the merged command comprises
an indication that the precharge operation (Chun, Fig. 3 // “a precharge (P) field” [0046]) and the activate operation (Chun, “the plurality of activate fields” [0046]) are to be performed on a first row of a first bank of the memory module (Bains, Fig. 4 // “BA# bits to represent bank address information, R# bits to represent row address information” [0038]) – As shown in Bains Fig. 4, certain bits of multi-cycle command specify on which banks and which rows a memory operation should be performed. As shown in Fig. 4, “Activate” is performed on addresses specified by bits BA0-2 and R0-12 (i.e., on at least “a first row of a first bank”); and “PreCharge” is performed on all Banks (i.e., on at least “a first row of a first bank”)--
and that the refresh operation (Chun, “the two refresh (R) fields” [0046]) is to be performed (Chun, “a batch refresh command 320 … includes a precharge (P), the two refresh fields (R), … and the plurality of activate (A) fields” [0046] // ¶0048) – As shown in Chun Fig. 3 and detailed in ¶0046, a batch refresh command can include each of a precharge field, a plurality of activate fields, and two refresh fields, which examiner considers as “indication[s]” that the respective operations should be performed.—
on the first bank of the memory module. (Chun, Fig. 5, “2X batch All Bank Refresh” // Fig. 4, bits CA0-CA6, falling edge // “the two refresh (R) fields identifying the two portions of the DRAM cell array to be refreshed” [0046] // ¶¶0045-46; 0050-51) – As detailed in Chun ¶¶0045-46 and shown in Fig. 4, bits CA0-CA6 of the falling clock edge (e.g., BA0-BA3, 2X, 4X, and AB) specify “the two portions” (i.e., the two rows of a bank; see ¶0045) to be refreshed. As clarified in Chun ¶0050-51, when the ‘all bank refresh flag bit (AB)’ of batch refresh command 320 is set to high, a refresh operation will be performed on all banks (i.e., at least a “first bank” of the DRAM)—
Regarding Claim 23,
The same motivation to combine provided in Claim 19 is equally applicable to Claim 23. The combined teachings of Chun and Bains disclose the following limitations:
The apparatus of claim 19, wherein the format of the merged command is a precharge command format (Chun, Fig. 3 // “Note that the precharge (P) … fields are not always present; they are generated in response to the need to read/write rows in the DRAM” [0048] // ¶¶0033; 0046) -- As shown in Chun Fig. 3 and detailed in ¶0046, a single batch refresh command 320 includes each of precharge (P), refresh (R), and activate (A) fields respectively causing precharge, refresh, and activate operations to be performed as part of the batch refresh command. Examiner considers a format of a merged command which causes a precharge operation to generally be performed, such as the 4X batch All Bank Refresh type of batch refresh command 320 of Chun, as reading on the claimed concept of “a precharge command format”, under the BRI of the claimed language.
Regarding Claim 24,
The same motivation to combine provided in Claim 19 is equally applicable to Claim 24. The combined teachings of Chun and Bains disclose the following limitations:
The apparatus of claim 19, wherein the format of the merged command is a refresh command format (Chun, Fig. 3 // “a batch refresh command 320 … includes … the two refresh (R) fields” [0046]) -- As shown in Fig. 3 and detailed in ¶0046, batch refresh command 320 is formatted to include at least a refresh (R) field. Examiner considers a format of a merged command which causes a refresh operation to generally be performed, such as the 4X batch All Bank Refresh type of batch refresh command 320 of Chun, as reading on the claimed concept of “a refresh command format”, under the BRI of the claimed language.
Regarding Claim 25,
Chun discloses the following limitations:
A method, comprising:
generating (Fig. 6, step 610), by a host device (SoC 1, Fig. 1) configured to communicate with a memory module (DRAM Sub-System 200, Fig. 1) via a channel (DRAM Bus 6, Fig. 1), a merged command (batch refresh command 320, Fig. 3) for performing at least a precharge operation (“precharging” [0033]), a refresh operation (“Refresh” [0034]), and an activate operation (“Activation” [0033]) on one or more rows of the memory module (“Refresh is the act of opening a row, then immediately precharging it” [0034] // “With batch refresh, multiple rows (e.g., 2x or 4x in all banks or in a single (per) bank) can be refreshed using a single command” [0034] // ¶¶0033-34; 0059) – As shown in Fig. 6 (see also ¶0059), SoC 1 generates and transmits a batch refresh command to DRAM 200. As disclosed in ¶0034, “refresh” (i.e., “a refresh operation”) includes “opening a row” (i.e., “an activate operation”; see also ¶0033) and “immediately precharging” (i.e., “a precharge operation”; see also ¶0033) the row. As clarified in ¶0034, a batch refresh command enables “multiple rows” to be refreshed using a single command--;
wherein the merged command includes a plurality of bits (P + R + A fields of Batch Refresh Command 320, Fig. 3 // Fig. 4) – As shown in Fig. 3, batch refresh command 320 includes plural fields (P, R, and A fields). Examiner considers the collective bits which form the P, R, and A fields of batch refresh command 320 as “a plurality of bits” included in batch refresh command 320--
of a format of the merged command (Figs. 4 + 5 // “The refresh scheduler 61 can issue a batch refresh command to refresh one, two, or four rows of one bank, one, two, or four rows of each bank of a group of banks, or one, two, or four rows of all banks” [0050] // ¶¶0051-54) – As shown in Figs. 4 + 5 and detailed in ¶¶0051-54, the aforementioned bits CA4-CA6 can be set to distinct values respectively corresponding to a particular number of rows and a particular number of banks on which to perform the batch refresh command. Examiner considers a batch refresh command performed on a respective number of rows and banks (e.g., ‘2X batch All Bank’ [0051] or ‘4X batch Per Bank’ [0053]) as a respective “format” of batch refresh command 320--
wherein the plurality of bits is repurposed (Fig. 4 // ¶¶0044-47; 0049 // Fig. 2, steps 230 + 232) – As shown in Fig. 4, bits CA4-CA6 are interpreted differently depending on whether the DRAM system is determined to be operating in a “normal” or a “batch” refresh mode (see Fig. 2 // ¶0044). Examiner accordingly considers the aforementioned bits CA4-CA6 (i.e., of batch refresh command 320) as being “repurposed” (i.e., interpreted differently) with respect to the same bits CA4-CA6 of normal refresh command 310 (see truth table 410 of Fig. 4)--
to indicate that … the refresh operation … should be performed (“a batch refresh command 320 … includes a precharge (P) field, the two refresh (R) fields … and the plurality of activate (A) fields” [0046] // Fig. 3 // ¶¶0033-34; 0045-48 // ¶0051) – As shown in Fig. 4 and described in ¶0046, bits included within the R fields of batch refresh command 320 (e.g., bits CA4-CA6 of Falling edge) can be set to indicate a refresh should be performed as part of performing the batch refresh command 320--; and
transmitting (Fig. 6, step 620) the merged command to the memory module (“At 620, the refresh scheduler 61 issues the batch memory refresh command to the dynamic volatile memory sub-system” [0059])
Chun does not provide specific detail regarding the bits of the Precharge (P) and Activate (A) fields and therefore does not explicitly disclose the following limitations:
wherein the plurality of bits is repurposed to indicate that the precharge operation, the refresh operation, and the activate operation should be performed
However, Bains clarifies within the context of performing refresh operations on DRAM devices that repurposing bits of a command can indicate that a precharge operation and an active operation should be performed on a DRAM.
Bains discloses the following limitations:
wherein the plurality of bits (Fig. 4) is repurposed to indicate that the precharge operation (PreCharge (per Bank, all Banks), Fig. 4), the refresh operation (Refresh (per Bank), Fig. 4), and the activate operation (Activate, Fig. 4) should be performed (“Command truth table 400 represents one example of a truth table which includes multi-cycle commands… Of particular note in table 400 are the four-cycle Activate command, the two-cycle PreCharge command and the two Refresh commands (per Bank and all Bank, respectively)” [0037-38] // Fig. 4) – As shown in the Bain Fig. 4 truth table, various bits of a multi-cycle memory command (e.g., bits CA0 and CA1) are set to various values (i.e., are “repurposed”) to indicate respective memory operations to performed (e.g., CA0 and CA1 bits taking values of LL, LH, and HH, respectively, indicate “Refresh (per Bank)”, “Activate”, and “PreCharge (per Bank, all Banks)” operations should be performed, respectively.)
Chun discloses a DRAM memory device (DRAM Sub-System 200, Fig. 1) which is accessed using a merged memory command (see Figs. 3 + 4), which is considered analogous to the Bains DRAM memory device (Memory Resources 114, Fig. 1 // ¶0008) which is accessed using multi-cycle commands (see Fig. 4). Bains discloses a known method of repurposing bits of a multi-cycle command to indicate that a precharge, a refresh, and an activate operation should be performed (see limitation mappings above). It would have been obvious to one of ordinary skill in the art, as taught by Bains, to implement the method of repurposing bits of a multi-cycle command to indicate that a precharge, a refresh, and an activate operation should be performed in the DRAM memory device accessed using a merged memory command of Chun. A person of ordinary skill in the art would have recognized that applying the known technique of repurposing bits of a multi-cycle command to indicate that a precharge, a refresh, and an activate operation should be performed as taught by Bains to a DRAM memory device accessed using a merged memory command would have yielded the predictable result of a merged memory command including repurposed bits to indicate that a precharge, a refresh, and an activate operation should be performed. A merged memory command including repurposed bits to indicate that a precharge, a refresh, and an activate operation should be performed would have been expected to reduce command overhead for performing the precharge, refresh, and activate operations by using a single merged command to perform three memory operations. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to apply the known technique of repurposing bits of a multi-cycle command to indicate that a precharge, a refresh, and an activate operation should be performed, as taught by Bains, to the DRAM memory device accessed using a merged memory command of Chun. Doing so would predictably result in a merged memory command including repurposed bits to indicate that a precharge, a refresh, and an activate operation should be performed. See MPEP 2143, Rationale D.
Regarding Claim 26,
The same motivation to combine provided in Claim 25 is equally applicable to Claim 26. The combined teachings of Chun and Bains disclose the following limitations:
The method of claim 25, wherein: the merged command is transmitted by the host device to the memory module via a command bus of the channel (Chun, DRAM bus 6, Fig. 1 // “The DRAM bus 6 carries data 6d and address/control information 6c to the PHY” [0031])
Regarding Claim 27,
The same motivation to combine provided in Claim 25 is equally applicable to Claim 27. The combined teachings of Chun and Bains disclose the following limitations:
The method of claim 25 (see Claim 25 limitation mappings above), wherein the format of the merged command is a read command format (Bains, “Read” Fig. 4) or a write command format (Bains, “Write” Fig. 4) – As shown in Bains Fig. 4, multi-cycle commands can additionally specify whether a Read or a Write should be performed on the DRAM.
Regarding Claim 28,
The same motivation to combine provided in Claim 25 is equally applicable to Claim 28. The combined teachings of Chun and Bains disclose the following limitations:
The method of claim 25, wherein the merged command comprises
an indication that the precharge operation (Chun, Fig. 3 // “a precharge (P) field” [0046]) and the activate operation (Chun, “the plurality of activate fields” [0046]) are to be performed on a first row of a first bank of the memory module (Bains, Fig. 4 // “BA# bits to represent bank address information, R# bits to represent row address information” [0038]) – As shown in Bains Fig. 4, certain bits of multi-cycle command specify on which banks and which rows a memory operation should be performed. As shown in Fig. 4, “Activate” is performed on addresses specified by bits BA0-2 and R0-12 (i.e., on at least “a first row of a first bank”); and “PreCharge” is performed on all Banks (i.e., on at least “a first row of a first bank”)--
and that the refresh operation (Chun, “the two refresh (R) fields” [0046]) is to be performed (Chun, “a batch refresh command 320 … includes a precharge (P), the two refresh fields (R), … and the plurality of activate (A) fields” [0046] // ¶0048) – As shown in Chun Fig. 3 and detailed in ¶0046, a batch refresh command can include each of a precharge field, a plurality of activate fields, and two refresh fields, which examiner considers as “indication[s]” that the respective operations should be performed.—
on the first bank of the memory module. (Chun, Fig. 5, “2X batch All Bank Refresh” // Fig. 4, bits CA0-CA6, falling edge // “the two refresh (R) fields identifying the two portions of the DRAM cell array to be refreshed” [0046] // ¶¶0045-46; 0050-51) – As detailed in Chun ¶¶0045-46 and shown in Fig. 4, bits CA0-CA6 of the falling clock edge (e.g., BA0-BA3, 2X, 4X, and AB) specify “the two portions” (i.e., the two rows of a bank; see ¶0045) to be refreshed. As clarified in Chun ¶0050-51, when the ‘all bank refresh flag bit (AB)’ of batch refresh command 320 is set to high, a refresh operation will be performed on all banks (i.e., at least a “first bank” of the DRAM)—
Regarding Claim 29,
The same motivation to combine provided in Claim 25 is equally applicable to Claim 29. The combined teachings of Chun and Bains disclose the following limitations:
The method of claim 25, wherein the format of the merged command is a precharge command format (Chun, Fig. 3 // “Note that the precharge (P) … fields are not always present; they are generated in response to the need to read/write rows in the DRAM” [0048] // ¶¶0033; 0046) -- As shown in Chun Fig. 3 and detailed in ¶0046, a single batch refresh command 320 includes each of precharge (P), refresh (R), and activate (A) fields respectively causing precharge, refresh, and activate operations to be performed as part of the batch refresh command. Examiner considers a format of a merged command which causes a precharge operation to generally be performed, such as the 4X batch All Bank Refresh type of batch refresh command 320 of Chun, as reading on the claimed concept of “a precharge command format”, under the BRI of the claimed language.
Regarding Claim 30,
The same motivation to combine provided in Claim 25 is equally applicable to Claim 30. The combined teachings of Chun and Bains disclose the following limitations:
The method of claim 25, wherein the format of the merged command is a refresh command format (Chun, Fig. 3 // “a batch refresh command 320 … includes … the two refresh (R) fields” [0046]) -- As shown in Fig. 3 and detailed in ¶0046, batch refresh command 320 is formatted to include at least a refresh (R) field. Examiner considers a format of a merged command which causes a refresh operation to generally be performed, such as the 4X batch All Bank Refresh type of batch refresh command 320 of Chun, as reading on the claimed concept of “a refresh command format”, under the BRI of the claimed language.
Response to Arguments
The previous objection of Claim 19 is withdrawn.
Applicant’s arguments with respect to claims 1-30 have been considered but are moot in view of the newly-applied Bains reference because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
With respect to applicant’s argument located within the 2nd paragraph of the 2nd page of remarks (numbered as page 11) continuing to the 3rd page of remarks (numbered as page 12), which recites:
Claim 1 is novel over Chun. In particular, Chun fails to disclose that "the merged command includes a plurality of bits of a format of the merged command" and that "the plurality of bits is repurposed to indicate that the precharge operation, the refresh operation, and the activate operation should be performed," as recited in amended claim 1.
Chun fails to disclose that that "the merged command includes a plurality of bits of a format of the merged command" and that "the plurality of bits is repurposed to indicate that the precharge operation, the refresh operation, and the activate operation should be performed," because the allegedly repurposed bits of Chun's Figures 4 and 5 are not repurpose to indicate that a precharge operation and an activate operation should be performed. For example, the Office Action states, at page 57, that "as disclosed in Chun Fig. 5, several types of batch refresh . . . can be performed using a batch refresh command" and that "as clarified in Figs. 4 and 5, values of the aforementioned bits . . . can assume a plurality of values, each of which indicate a particular type of batch refresh to perform." For example, as shown in Figures 4 and 5 of Chun, various values for 2X, 4X, and AB of the batch refresh correspond to various different refresh operations. However, Chun does not disclose that the bits 2x, 4x, and AB are repurposed to indicate that a precharge operation and an activate operation should be performed. That is, the allegedly repurposed bits of Chun are not disclosed as being repurposed to indicate that a precharge operation, a refresh operation, and an activate operation should be performed. In fact, Chun specifically states, at paragraph [0048] that "the precharge (P) and activate (A) fields are not always present," and bits corresponding to the precharge and activate fields are not shown in Figure 4 or Figure 5 of Chun. The Office's assertion at page 58 of the Office Action, that "the aforementioned bits are part of a single (e.g., batch refresh) command which causes each of a precharge, a refresh, and an activate operation generally be performed," is insufficient to satisfy the limitations of amended claim 1, as claim 1 recites that "the plurality of bits is repurposed to indicate that the precharge operation, the refresh operation, and the activate operation should be performed." Accordingly, Chun fails to disclose that "the merged command includes a plurality of bits of a format of the merged command" and that "the plurality of bits is repurposed to indicate that the precharge operation, the refresh operation, and the activate operation should be performed," as recited in amended claim 1.
Examiner has fully considered the aforementioned argument but finds it moot in view of the newly-applied Bains reference. See 35 U.S.C. 103 rejections above for additional details. Examiner additionally notes that the outstanding 35 U.S.C. 103 rejection has updated the mappings of the claimed concept of “a plurality of bits of a format of the merged command” in Chun from bits CA4-CA6 of the falling clock edge of batch refresh command 420 of Chun Fig. 4 instead to the collective bits represented by the P, R, and A fields of batch refresh command 320 of Chun Fig. 3. Examiner’s updated mappings was necessitated by the instant amendments to the claims.
Examiner maintains that Batch Refresh Command 320 depicted in Chun Fig. 3 reads on the claimed concept of “a merged command” as currently recited in independent claims. See 35 U.S.C. 103 rejections above. Examiner additionally notes that Normal Refresh Command 310 depicted in Chun Fig. 3 may also read on the claimed concept of “a merged command” which at least causes a precharge, a refresh, and an activate operation. If applicant wishes to distinguish the claimed “a merged command” from either Batch Refresh Command 320 or Normal Refresh Command 310 of Chun, examiner recommends applicant amend the independent claims to provide more clarity regarding how repurposing bits results in “a format” of a merged command. Certain features of the disclosed invention, such as the merged command being comprised of repurposed bits of a standard command format (e.g., Specification ¶0068); in combination with the context that repurposing of bits indicates that a merged command includes a command to perform one or more additional operations (e.g., Specification ¶0068), might be helpful in distinguishing the independent claims from the Chun disclosure.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/J.S.M./Examiner, Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133
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