DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Referring to claims 2-4, and consequently their dependent claims, what “the task” refers to is unclear. In claim 1, there are “tasks initiated by the processing circuitry blocks” for claims 2 and 3 to refer to, but unclear which. For claim 4, see the claiming in claim 15 regarding “the task associated with the timeout”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 10, 12-14, 21, 23 is/are rejected under 35 U.S.C. 102a1/a2 as being anticipated by US 6370656 to Olarig et al.
Referring to claim 1, Olarig discloses a processing system, comprising:
a plurality of processing circuitry blocks; critical domain management circuitry to assign a level of criticality to each of the processing circuitry blocks and to assign a respective timeout duration to tasks initiated by the processing circuitry blocks based at least in part on an assigned level of criticality (From column 6, line 59 (with emphasis), “In a preferred embodiment, various components within computer system 100 periodically send heartbeat messages to the heartbeat monitor 130 via the PCI bus 112. The heartbeat messages are stored within the heartbeat monitor 130 and indicate that the components transmitting the heartbeats (referred to as "heartbeat senders") are functioning properly. The heartbeat period, which is the length of time between each heartbeat, may be different for each heartbeat sender and can be adjusted for a given heartbeat sender depending on time or other system operating conditions as explained below. Initially, the heartbeat monitor 130 determines an appropriate heart rate for each heartbeat sender and preferably notifies a heartbeat sender when and by how much its associated heart rate needs to change. Accordingly, heartbeat senders periodically transmit heartbeats to the heartbeat monitor 130 at the intervals prescribed by the heartbeat monitor 130. Although any component within computer system 100 may transmit heartbeat messages to the heartbeat monitor, a preferably the heartbeats are transmitted by the CPUs 102 and 103, the bridge logic unit 104, and the network interface card (NIC) 121.” Wherein a heartbeat is a sender “task”. From line 65 of column 8, “Because longer heartbeat periods may be advantageous for some situations while shorter heartbeat periods may be better at other times, the heartbeat monitor 130 preferably is capable of dynamically optimizing the heart rate for each component. A frequent heartbeat, (characterized by a short heartbeat period) allows the system to detect and recover from failure more quickly. A frequent heartbeat generally minimizes average recovery time, because the heartbeat period represents the maximum time required for the heartbeat monitor 130 to detect that a component has failed to send a heartbeat since the last detected heartbeat. In addition to reducing average system recovery time, however, shortening the heartbeat period increases the amount of message traffic on the PCI bus 112, thereby reducing the total amount of PCI bus capacity available to other components. Hence, if the heartbeat period is shorter than necessary, then the message traffic created by the heartbeats may interfere with other important computer functions. In contrast, an infrequent heartbeat (characterized by a long heartbeat period) produces less PCI bus traffic. If the heartbeat is too infrequent, however, the heartbeat monitor 130 may not detect component failures quickly enough. Accordingly, it often is desirable to optimize the heartbeat period to be just short enough to facilitate expedient failure recovery but not short enough to bottleneck the PCI bus 112. Thus, the heartbeat of the preferred embodiment is adaptive.” Further, see figure 5 and its corresponding description in the specification, regarding interval determination.); and
error handling circuitry to monitor the processing circuitry blocks and to handle errors based at least in part on the assigned levels of criticality (See for example figure 4b, 448 “heartbeat detected?” and 452 “take corrective actions”.).
Referring to claim 2, Olarig discloses wherein the timeout duration is based at least in part on the assigned level of criticality associated with the processing circuitry block that initiated the task (From column 6, line 59 (with emphasis), “In a preferred embodiment, various components within computer system 100 periodically send heartbeat messages to the heartbeat monitor 130 via the PCI bus 112. The heartbeat messages are stored within the heartbeat monitor 130 and indicate that the components transmitting the heartbeats (referred to as "heartbeat senders") are functioning properly. The heartbeat period, which is the length of time between each heartbeat, may be different for each heartbeat sender and can be adjusted for a given heartbeat sender depending on time or other system operating conditions as explained below. Initially, the heartbeat monitor 130 determines an appropriate heart rate for each heartbeat sender and preferably notifies a heartbeat sender when and by how much its associated heart rate needs to change. Accordingly, heartbeat senders periodically transmit heartbeats to the heartbeat monitor 130 at the intervals prescribed by the heartbeat monitor 130. Although any component within computer system 100 may transmit heartbeat messages to the heartbeat monitor, a preferably the heartbeats are transmitted by the CPUs 102 and 103, the bridge logic unit 104, and the network interface card (NIC) 121.”).
Referring to claim 3, Olarig discloses wherein the timeout duration is based at least in part on the assigned level of criticality associated with a processing circuitry block that is assigned to execute the task (From column 6, line 59 (with emphasis), “In a preferred embodiment, various components within computer system 100 periodically send heartbeat messages to the heartbeat monitor 130 via the PCI bus 112. The heartbeat messages are stored within the heartbeat monitor 130 and indicate that the components transmitting the heartbeats (referred to as "heartbeat senders") are functioning properly. The heartbeat period, which is the length of time between each heartbeat, may be different for each heartbeat sender and can be adjusted for a given heartbeat sender depending on time or other system operating conditions as explained below. Initially, the heartbeat monitor 130 determines an appropriate heart rate for each heartbeat sender and preferably notifies a heartbeat sender when and by how much its associated heart rate needs to change. Accordingly, heartbeat senders periodically transmit heartbeats to the heartbeat monitor 130 at the intervals prescribed by the heartbeat monitor 130. Although any component within computer system 100 may transmit heartbeat messages to the heartbeat monitor, a preferably the heartbeats are transmitted by the CPUs 102 and 103, the bridge logic unit 104, and the network interface card (NIC) 121.”).
Referring to claim 10, Olarig discloses wherein the critical domain management circuitry is further to dynamically modify a level of criticality assigned to at least one processing circuitry block based on one or more changes to an operational state of the processing system (From column 9 line 43, “Still referring to FIG. 1, the heartbeat period preferably is longer for newer components and shorter for older components. In addition, the heartbeat period (or equivalently the heart rate) may be adjusted at any time by the heartbeat monitor 130. In the event that the heartbeat monitor 130 is not able to determine the manufacturing date of a component, the heartbeat period preferably is set to a predetermined default value. The default value preferably is equal to the maximum acceptable delay for determining component failure, although any desired default value may be used without departing from the principles of the invention. Similarly, the heartbeat monitor 130 may also raise or lower the heart rate of any heartbeat sender according to warning signals or environmental conditions within the computer. In a preferred embodiment, heartbeat monitor 130 includes a temperature sensor which determines when the temperature of the computer 100 rises above an acceptable threshold. Because excessive temperatures can increase the likelihood of component failures, the heartbeat monitor 130 preferably increases the heart rates of selected components so that these components can be monitored more often if the temperature exceeds a threshold. If the temperature drops below the temperature threshold, then the heart rates are lowered to the previous level. In addition, the heartbeat monitor 130 is capable of receiving error signals or warning signals from some components to indicate possible impending failures or other dangerous conditions. The heartbeat monitor 130 then respond by increasing the heart rate for that device. In a preferred embodiment, the bridge logic 104 is capable of detecting errors in read and write cycles to main memory 106. If memory transaction errors begin to occur frequently, then the bridge logic 104 preferably notifies the heartbeat monitor 130 of the error condition by transmitting a message over the PCI bus 112. Alternatively, the bridge logic 104 may assert a special interrupt signal or other sideband signal to the heartbeat monitor 130 to indicate excessive memory errors. In response, the heartbeat monitor 130 preferably increases the heart rate of the bridge logic 104 in order to monitor the memory device 106 more often. The heartbeat monitor 130 can decrease the heart rate of the bridge logic 104 if the bridge logic 104 indicates via a PCI message or other signal that the memory errors have subsided. The heartbeat intervals may be decreased in response to some other conditions, as well. For example, the PCI bus 112 may transmit a signal indicating that it has reached a predetermined traffic threshold. Similarly, the bridge logic 104 may transmit a message indicating a large number of pending requests for main memory 106. Because these messages indicate that some resources in the system are undergoing heavy use (i.e., the PCI bus 112 and the memory device 106), the heartbeat monitor 130 preferably responds by increasing the associated heartbeat intervals to allow these devices to operate as efficiently as possible.”).
Referring to claims 12-14, 21, 23 see rejection of claims 1, 10 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11, 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Olarig as applied to claim 1, 12 above, and further in view of Official notice (DSPs).
Referring to claim 11, Olarig discloses the plurality of processing circuitry blocks, and wherein at least one blocks is assigned a higher level of criticality than one or more other of the blocks (see above).
Although Olarig does not specifically disclose these blocks may comprise multiple digital signal processors (DSPs), this is very well known in the art. In a related field of computing, examiner takes official notice for DSPs. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have multiple DSPs because a DSP generally provides for the processing of analog signals, which and how many are going to be determined by the signals that need to be analyzed.
Referring to claim 22, see rejection of claim 11 above.
Allowable Subject Matter
Claims 4-9, 15-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Referring to claims 4-8, the prior art does not teach or fairly suggest wherein to handle errors comprises initiating a soft reset protocol for a task based on a timeout associated with the task expiring prior to completion of the task, in the scope and context of claim 1, further pending resolution of rejection of claims 4-8 above.
Referring to claim 9, the prior art does not teach or fairly suggest wherein the critical domain management circuitry is further to: assign a first task timer timeout value to a task initiated by a first processing circuitry block, the first processing circuitry block assigned a first level of criticality; and assign a second task timer timeout value to a second task initiated by a second processing circuitry block, the second processing circuitry block assigned a second level of criticality that is higher than the first level of criticality; wherein the second task timer timeout value is greater than the first task timer timeout value, in the scope and context of claim 1.
Referring to claims 15-20, see claims 4-9 above.
Response to Arguments
Applicant's arguments filed 24 November 2025 have been fully considered but they are not persuasive.
Regarding Applicant’s remarks (page 8) concerning incorporation of limitations Applicant identified as deemed allowable, this subsequent shift in emphasis has altered examiner’s interpretation of the claims. See rejection above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GABRIEL L CHU whose telephone number is (571)272-3656. The examiner can normally be reached weekdays 8 am to 5 pm.
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/GABRIEL CHU/ Primary Examiner, Art Unit 2114