DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: A Method of Manufacturing a Semiconductor Device by Forming an Aluminum Alloy Film and Removing Possible Defects in the Semiconductor Chips.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over OHSE (US 2021/0391437) in view of Sweetnam et al (US 2022/0099593) and Takahashi (US 2023/0064636), and in further view of CAO et al (US 2021/0025846).
Regarding Claim 1, OHSE discloses a method (method [0021]) of manufacturing a semiconductor device (silicon carbide semiconductor device 40 [0054] Fig 3 and Fig 4), the method comprising:
providing a semiconductor substrate (semiconductor substrate 30 [0054]);
forming a surface structure (structure that includes p-type regions 13 and the front electrode 14 [0055])) including a metal oxide semiconductor (MOS) structure (front electrode 14 [0055]) in the semiconductor substrate (30);
forming an interlayer insulating film (field oxide film 15 [0069]) covering the surface structure (structure that includes 13 and 14);
forming, in the interlayer insulating film (15), a contact hole (contact hole 15a [0071]) to expose the surface structure (structure that includes 13 and 14);
forming a first Al alloy film (aluminum alloy film 32 [0092]) in contact with the surface structure (structure that includes 13 and 14) and covering an entire surface of the interlayer insulating film (15),
OHSE does not disclose
the first Al alloy film having a thickness in a range of 0.05μm to 0.5μm;
detecting, using a dark field, a defect of a surface of the first Al alloy film;
forming a second Al alloy film covering the entire surface of the first Al alloy film;
patterning the first Al alloy film and the second Al alloy film;
annealing the first Al alloy film and the second Al alloy film; and
dicing the semiconductor substrate into a plurality of chips, and picking, among the plurality of chips, chips free of the detected defect.
Sweetnam et al, in the related art of semiconductor devices that include transistors, discloses
detecting, using a dark field (dark field images [0047]), a defect (defects 120 [0047] Fig 4) of a surface of the first Al alloy film (semiconductor layers 110a and 110b [0040]);
forming a second Al alloy film (top electrodes 112 [0045]) covering an entire surface (area where the defect is located) of the first Al alloy film (110a and 110b);
patterning [0060] the first Al alloy film (110a and 110b) and the second Al alloy film (112);
annealing [0060] the first Al alloy film (110a and 110b) and the second Al alloy film (112); and
dicing [0052].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify OHSE to include detecting, using a dark field, a defect of a surface of the first Al alloy film; forming a second Al alloy film covering the entire surface of the first Al alloy film; patterning the first Al alloy film and the second Al alloy film; annealing the first Al alloy film and the second Al alloy film; and dicing as taught by Sweetnam et al in order to reduce defects [0003]. Further, a person of ordinary skill in the art would have recognized that reducing defects would improve the reliability and durability of the device (see MPEP 2143.I(D)).
The combination of OHSE and Sweetnam et al now discloses
forming a second Al alloy film covering the entire surface of the first Al alloy film.
The combination of OHSE and Sweetnam et al does not disclose
the first Al alloy film having a thickness in a range of 0.05μm to 0.5μm; and
dicing the semiconductor substrate into a plurality of chips, and picking, among the plurality of chips, chips free of the detected defect.
Takahashi, in the related art of semiconductor devices that include transistors, discloses
dicing (dicing [0014]) the semiconductor substrate (substrate [0014] shown to be diced in Fig 4) into a plurality of chips (first chip region and second chip region [0014]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of OHSE and Sweetnam et al to include dicing the semiconductor substrate into a plurality of chips, and picking, among the plurality of chips, chips free of the detective defect as taught by Takahashi in order to improve the reliability of the semiconductor device and suppress the reduction in the yield of the semiconductor device [0029]. Further, a person of ordinary skill in the art would have recognized that selecting defect free chips would be advantageous in providing a more reliable and durable device (see MPEP 2143.I(D)).
The combination of OHSE, Sweetnam et al, and Takahashi now discloses
dicing the semiconductor substrate (substrate [0014] shown to be diced in Fig 4 Takahashi) into a plurality of chips (first chip region and second chip region [0014] (Takahashi), and picking, among the plurality of chips, chips free of the detected defect (using defect reduction system 200 [0047] Sweetnam et al).
The combination of OHSE, Sweetnam et al, and Takahashi does not disclose
the first Al alloy film having a thickness in a range of 0.05μm to 0.5μm.
CAO et al, in the related art of semiconductor devices that include FET transistors, discloses
the first Al alloy film (aluminum-copper alloy layer [0017]) having a thickness in a range of 0.05μm to 0.5μm (20 -600 nm [0017] which would be 0.02 microns to 0.6 microns).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of OHSE, Sweetnam et al, and Takahashi to include the first Al alloy film having a thickness in a range of 0.05μm to 0.5μm as taught by CAO et al in order to optimize the electrical function while also optimizing structural support and meeting the small size requirements of the device, and because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05), and further because it would have been an obvious matter of design choice to optimize the thickness of the first Al alloy film since such a modification would have involved a mere change in size of the component. A change in size is generally recognized as being within the level of ordinary skill in the art In Re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) MPEP 2144.04.IV(A). Further, a person of ordinary skill in the art would have recognized that having optimized structural support would be advantageous in improving the reliability of the device (see MPEP 2143.I(D)).
Regarding Claim 4, the combination of OHSE, Sweetnam et al, Takahashi, and CAO et al discloses the limitations of claim 1 as explained above. The combination of OHSE, Sweetnam et al, Takahashi, and CAO et al further discloses
wherein the first Al alloy film is an Al film, an AlSi film (32 is an aluminum silicon film AlSi [0092] OHSE), or an AlSiCu film.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over OHSE (US 2021/0391437) in view of Sweetnam et al (US 2022/0099593), Takahashi (US 2023/0064636), and CAO et al (US 2021/0025846), and in further view of Gotoh et al (US 2006/0181198).
Regarding Claim 2, the combination of OHSE, Sweetnam et al, Takahashi, and CAO et al discloses the limitations of claim 1 as explained above. The combination of OHSE, Sweetnam et al, Takahashi, and CAO et al does not directly disclose
wherein forming the first Al alloy film includes forming the first Al alloy film by a temperature of not more than 100 degrees C.
Gotoh et al, in the related art of semiconductor devices that include transistors, discloses
wherein forming the first Al alloy film (Al alloy film [0024]) includes forming the first Al alloy film (Al alloy film [0024]) by a temperature of not more than 100 degrees C (250 degrees Celsius or lower [0024]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of OHSE, Sweetnam et al, Takahashi, and CAO et al to include wherein forming the first Al alloy film includes forming the first Al alloy film by a temperature of not more than 100 degrees C as taught by Gotoh et al in order to secure a sufficiently low electrical resistivity even when a relatively low thermal processing is used without impairing the advantage of the direct connection with the electrode [0024] and because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over OHSE (US 2021/0391437) in view of Sweetnam et al (US 2022/0099593), Takahashi (US 2023/0064636), and CAO et al (US 2021/0025846), and in further view of Sotani et al (US 2003/0168968).
Regarding Claim 3, the combination of OHSE, Sweetnam et al, Takahashi, and CAO et al discloses the limitations of claim 1 as explained above. The combination of OHSE, Sweetnam et al, Takahashi, and CAO et al does not directly disclose
wherein forming the first Al alloy film includes forming the first Al alloy film in which a size of crystal grain boundaries of Al is not more than 0.2μm.
Sotani et al, in the related art of semiconductor devices that include transistors, discloses
a first Al alloy film (aluminum alloy [0020]) includes forming the first Al alloy film in which a size of crystal grain boundaries of Al is not more than 0.2μm (16.9 nm or more [0020] which would be .0169 microns or more).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of OHSE, Sweetnam et al, Takahashi, and CAO et al to include wherein forming the first Al alloy film includes forming the first Al alloy film in which a size of crystal grain boundaries of Al is not more than 0.2μm as taught by Sotani et al in order to reduce a probability of diffusion of electrons in a grain boundary and therefore to reduce a specific resistance of the layered structure of the wire (s) [0020]. Further, a person of ordinary skill in the art would have recognized that reducing the resistance of a layered structure of wires would be advantageous in improving the electrical functioning of the device (see MPEP 2143.I(D)).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over OHSE (US 2021/0391437) in view of Sweetnam et al (US 2022/0099593), Takahashi (US 2023/0064636), and CAO et al (US 2021/0025846), and in further view of Shastri et al (US 2008/0001186).
Regarding Claim 5, the combination of OHSE, Sweetnam et al, Takahashi, and CAO et al discloses the limitations of claim 1 as explained above. The combination of OHSE, Sweetnam et al, Takahashi, and CAO et al does not directly disclose
wherein a combined thickness of the first Al alloy film and the second Al alloy film is in a range of 4.5μm to 5.5μm.
Shastri et al, in the related art of semiconductor devices that include MOS transistors, discloses
wherein an Al alloy film is about 2μm [0038] (which would indicate that a combined thickness of two Al alloy films would be about 4 μm).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention modify the combination of OHSE, Sweetnam et al, Takahashi, and CAO et al to include wherein a combined thickness of the first Al alloy film and the second Al alloy film is in a range of 4.5μm to 5.5μm as taught by Shastri et al in order to optimize the electrical function while also optimizing structural support and meeting the small size requirements of the device, and because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05), and further because it would have been an obvious matter of design choice to optimize the thickness of the first Al alloy film since such a modification would have involved a mere change in size of the component. A change in size is generally recognized as being within the level of ordinary skill in the art In Re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) MPEP 2144.04.IV(A). Further, a person of ordinary skill in the art would have recognized that having optimized structural support would be advantageous in improving the reliability of the device (see MPEP 2143.I(D)).
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hirose et al (US 2019/0172912) which discloses a method of manufacturing an IGBT device [0028], and Yamazaki (US 2011/0309456) which discloses a highly purified oxide semiconductor film [0037].
Conclusion
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/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812