Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s amendments with respect to claims 1, 8 and 14 have been fully considered. The objection of claim 1, 8 and 14 has been withdrawn.
Applicant’s amendments with respect to claim 18 has been fully considered. The rejection of claim 18-20 under 35 U.S.C. 112(b) has been withdrawn.
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s arguments with respect to claim 8 have been fully considered but they are not persuasive. The applicant argues that “The remote device applies the configured offset as directed by the base station's scheduling framework - it does not independently apply a self-determined offset to its operational data transmissions.”. The examiner respectfully disagrees. As cited in the office action “Han [0013] transmitting, by a remote device, a Time Sensitive Networking (TSN) traffic pattern to a base station; and configuring scheduling of TSN transmissions between the remote device and the base station based on a TSN traffic configuration; wherein the TSN traffic pattern comprises a periodicity value and a time offset value”. The remote device provides TSN traffic pattern comprising a periodicity value and a time offset value to the base station. The base station configures scheduling of TSN transmission based on the TSN traffic pattern (Han [0153]). The remote device determines and applies the offset.
Applicant’s arguments with respect to claim 14 have been fully considered but they are not persuasive. The applicant argues that “it is not readily apparent how the "controller" and the "receiver" can both read on Law's controller 104, as the controller and receiver are separate elements of claim 14”. The examiner respectfully disagrees. Law’s controller 104 has controller function. Law’s controller 104 has receiver function (Law Fig. 2, [0002] as cited in rejection of claim 14.).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 and 5-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20110054640 A1 (hereinafter Law), in view of US 20190268946 A1 (hereinafter Harada) and JP H1185312 A (hereinafter Kitamoto).
Regarding claim 1, Law teaches A receiver comprising (Law [0042] FIG. 2 shows the example
process control system 100 of FIG. 1 including the controller 104.
[0002] A process controller receives signals indicative of process measurements made by the
field devices and/or other information pertaining to the field devices, uses this information to implement a control routine, and generates control signals that are sent over buses or other communication lines to the field devices to control the operation of the process.
[0143] FIG. 10 is a block diagram of an example processor system 1010 that may be used to
implement the example methods and apparatus described herein.
Note: the process controller is the receiver.):
at least one processor (Law [0144] As shown in FIG. 10, the processor system 1010 includes a
processor 1012.); and
memory coupled to the at least one processor, the memory storing computer-executable
instructions (Law system memory 1024 in Fig. 10. [0145] The processor 1012 of FIG. 10 is coupled to a chipset 1018, which includes a memory controller 1020 and a peripheral input/output (I/O) controller 1022. The memory controller 1020 performs functions that enable the processor 1012 (or processors if there are multiple processors) to access a system memory 1024.),
wherein the at least one processor is configured to execute the computer-executable
instructions to cause the receiver to (Law [0149] At least some of the above described example methods and/or systems are implemented by one or more software and/or firmware programs running on a computer processor.):
receive a setup transmission from an emitter via a communications link connecting the emitter
and the receiver (Law [0016] A controller receives signals (e.g., input signals) indicative of process measurements made by the field devices and/or other information pertaining to the field devices, uses this information to implement a control routine, and generates control signals (e.g., output signals) that are sent over the buses or other communication lines to the field devices to control the operation of the process.
Note: the field device is the emitter.);
determine a current variance between a scheduled receive time and a time at which the setup
transmission was received (Law [0042] FIG. 2 shows the example process control system 100 of FIG. 1 including the controller 104 operating a control loop 202. The process components within FIG. 2 include two sets of feedback loops. The first feedback loop includes the field devices 112a and 112b. The second feedback loop includes the field devices 116a and 116b.
[0046] The I/O scheduler 180 and/or the controller 104 manages the timing of the input signals originating from the sensors 112b and 116b. The I/O scheduler 180 forwards the input signals to the control loop 202 during each scheduled time period of the control loop 202.
[0061] FIG. 4A is a timing diagram 400 of the example control loop 202 of FIG. 2. The input signals 430-436 originate from the same field device.
[0062] The timing diagram 400 includes the scheduled time period 422a, which is a specified, predetermined, and/or scheduled time period for the control loop 202 to receive the first input signal 430.
[0063] the first input signal 430 is received during the scheduled time period 422a. However, the second, third, and fourth input signals 432, 434, and 436 are not received during the scheduled time periods 422b-d.
[0048] when the I/O scheduler 180 does not receive input signals during the respective scheduled time periods, the I/O scheduler 180 and/or the controller 104 calculates the time difference between the time at which the input signal was received and its respective scheduled time period (e.g., the beginning or middle of its scheduled time period). ); and
Law does not explicitly teach receive a setup transmission prior to a period when the communications link is active for transmitting operational data;
Harada in the same or similar field of endeavor teaches receive a setup transmission prior to a period when the communications link is active for transmitting operational data (Harada Fig. 1;
[0034] As illustrated in FIG. 1, when an idle (RRC_IDLE) state transitions to an RRC connected (RRC_CONNECTED) state (e.g., at a time of initial access), the user terminal selects one of a plurality of preambles indicated by the PRACH configuration information at random, and transmits the selected preamble on the PRACH (message 1).
[0035] When detecting the preamble, the radio base station transmits a Random Access Response (RAR) as a response to the detection (message 2). When failing receiving the RAR within a predetermined period (RAR window) after transmitting the preamble, the user terminal increases PRACH transmission power and transmits (retransmits) the preamble again. In addition, increasing transmission power during retransmission is also referred to as power ramping.
[0036] The user terminal that has received the RAR adjusts a UL transmission timing based on a timing advance (TA) included in the RAR, and establishes UL synchronization. Furthermore, the user terminal transmits a control message of a higher layer (L2/L3: Layer 2/Layer 3) by using a UL resource indicated by a UL grant included in the RAR (message 3). The control message includes an identifier (UE-ID) of the user terminal.
[0037] The radio base station transmits a contention resolution message according to a control message of the higher layer (message 4). The contention resolution message is transmitted addressed to the identifier of the user terminal included in the above control message. The user terminal that has succeeded detecting the contention resolution message transmits an acknowledgement response (ACK: Acknowledgement) of Hybrid Automatic Repeat request (HARQ) to the radio base station. Thus, the user terminal in the idle state transitions to the RRC connected state.
[0050] When the user terminal establishes RRC connection (RRC Connected), the radio base station can notify each user terminal of information related to the uplink control channel configuration and/or the resources by using RRC signaling. Consequently, the user terminal can select an appropriate uplink control channel configuration and/or resources.
Note: the message 1 is the setup transmission. The setup transmission is received prior to the RRC connected state.);
By modifying Law’s teachings of receive a setup transmission from an emitter via a communications link connecting the emitter and the receiver
with Harada’s teachings of receive a setup transmission prior to a period when the communications link is active for transmitting operational data
the modification results in
receive a setup transmission from an emitter via a communications link connecting the emitter and the receiver prior to a period when the communications link is active for transmitting operational data;
It would have been prima facie obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified Law with Harada’s above teachings. The motivation is reducing a processing load of the device (Harada [0056]).
Although Law teaches transmit a first control message to the emitter, wherein the first control
message indicates the current variance is not acceptable (Law [0048] The I/O scheduler 180 and/or the controller 104 then sends a timing adjustment message to the I/O data acquisition module 190 to adjust the timing of subsequent input signals from the same field device so that the I/O scheduler 180 receives the input signals during the appropriately scheduled time period(s).
[0068] As a result of receiving the timing adjustment message, the I/O data acquisition module 190 adjusts its timing for requesting subsequent input signals from the field device.), Law does not explicitly teach transmit a first control message to the emitter, wherein the first control message indicates the current variance (time difference) is acceptable.
Kitamoto in the same or similar field of endeavor teaches transmit a first control message to the emitter, wherein the first control message indicates the current variance (time difference) is acceptable (Kitamoto page 5, the time difference allowable range confirming means 15 confirms whether or not the time difference is within the allowable range, and the confirmation result is transmitted by the confirmation result transmitting means 16.
The confirmation result data is transmitted to the time correction computer 2. ).
By modifying Law’s teachings of transmit a first control message to the emitter, wherein the first control message indicates the current variance is not acceptable
with Kitamoto’s teachings of transmit a first control message to the emitter, wherein the first control message indicates the current variance (time difference) is acceptable,
the modification results in transmit a first control message to the emitter, wherein the first control message indicates whether the current variance is acceptable.
It would have been prima facie obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified Law as modified by Harada with Kitamoto’s above teachings. The motivation is time synchronization between computers connected to each other via a communication line (Kitamoto page 1).
Regarding claim 5, Law in view of Harada and Kitamoto (hereinafter combination) teaches The
receiver of claim 1.
Although Law teaches wherein the at least one processor is configured to execute the computer-executable instructions (Law [0149] cited above in rejection of claim 1), Law does not explicitly teach further configured to cause the receiver to: generate a dedicated control message including variance information.
Kitamoto teaches further configured to cause the receiver to: generate a dedicated control message including variance information (Kitamoto page 5, the time difference allowable range confirming means 15 confirms whether or not the time difference is within the allowable range, and the confirmation result is transmitted by the confirmation result transmitting means 16. The confirmation result data is transmitted to the time correction computer 2.).
It would have been prima facie obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified the combination with Kitamoto’s above teachings. The motivation is time synchronization between computers connected to each other via a communication line (Kitamoto page 1).
Regarding claim 6, the combination teaches The receiver of claim 1.
Although Law teaches wherein the at least one processor is configured to execute the computer-executable instructions (Law [0149] cited above in rejection of claim 1), Law does not explicitly teach further configured to cause the receiver to: insert variance information into a non-dedicated signal.
Kitamoto teaches further configured to cause the receiver to: insert variance information into a non-dedicated signal (Kitamoto page 5, the time difference allowable range confirming means 15 confirms whether or not the time difference is within the allowable range, and the confirmation result is transmitted by the confirmation result transmitting means 16. The confirmation result data is transmitted to the time correction computer 2.).
It would have been prima facie obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified the combination with Kitamoto’s above teachings. The motivation is time synchronization between computers connected to each other via a communication line (Kitamoto page 1).
Regarding claim 7, the combination teaches The receiver of claim 1.
Law teaches further comprising: an optical line card configured to communicate with the emitter via an optical communications link (Law [0003] Each of these field devices is typically coupled to the process controller via one or more I/O cards and a respective communication path (e.g., a two-wire cable, a wireless link, or an optical fiber).).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Law in view of Harada and Kitamoto as applied to claim 1 above, and further in view of US 20220272604 (hereinafter Leclerc).
Regarding claim 2, the combination teaches The receiver of claim 1.
Although the combination teaches wherein the at least one processor is further
configured to execute the computer-executable instructions to cause the receiver to:
determine that the current variance is acceptable in response to the scheduled receive time and the time at which the setup transmission was received varying by less than a threshold value (Law [0042], [0046, [0061-0063], [0048] and Kitamoto page 5 cited in rejection of claim 1.), the combination does not explicitly teach the time difference is in units of clock cycles.
Leclerc in the same or similar field of endeavor teaches the time difference is in units of clock cycles (Leclerc [0013] In response to a deterministic packet arriving during an actual clock cycle, circuitry can compare the actual clock cycle to a planned clock cycle for reception of the deterministic packet and corrective actions can be performed to resolve any discrepancies.).
By modifying the combination’s teachings of wherein the at least one processor is further configured to execute the computer-executable instructions to cause the receiver to:
determine that the current variance is acceptable in response to the scheduled receive time and the time at which the setup transmission was received varying by less than a threshold value
with Leclerc’s teachings of the time difference is in units of clock cycles,
the modification results in
wherein the at least one processor is further configured to execute the computer-executable instructions to cause the receiver to: determine that the current variance is acceptable in response to the scheduled receive time and the time at which the setup transmission was received varying by less than a threshold number of clock cycles.
It would have been prima facie obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified the combination with Leclerc’s above teachings. The motivation is reducing latency (Leclerc [0010]).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Law in view of Harada and Kitamoto as applied to claim 1 above, and further in view of US 20220304010 A1 (hereinafter Han).
Regarding claim 3, the combination teaches The receiver of claim 1.
Law teaches wherein the at least one processor is further configured to execute the computer-
executable instructions to cause the receiver to:
receive operational data from the emitter during the period when the communication link is active; monitor an operational variance indicating a difference between a first time at which the receiver expected to receive the operational data, and a second time at which the receiver received the operational data (Law [0061] FIG. 4A is a timing diagram 400 of the example control loop 202 of FIG. 2. The input signals 430-436 originate from the same field device.
[0062] The timing diagram 400 includes the scheduled time period 422a, which is a specified, predetermined, and/or scheduled time period for the control loop 202 to receive the first input signal 430.
[0063] the first input signal 430 is received during the scheduled time period 422a. However, the second, third, and fourth input signals 432, 434, and 436 are not received during the scheduled time periods 422b-d.
[0048] when the I/O scheduler 180 does not receive input signals during the respective scheduled time periods, the I/O scheduler 180 and/or the controller 104 calculates the time difference between the time at which the input signal was received and its respective scheduled time period (e.g., the beginning or middle of its scheduled time period).); and
The combination does not explicitly teach transmit a second control message to the emitter, wherein the second control message indicates a transmission offset to be applied by the emitter.
Han in the same or similar field of endeavor teaches transmit a second control message to the emitter, wherein the second control message indicates a transmission offset to be applied by the emitter (Han [0018] adjusting the SPS/CG configuration for subsequent TSN transmissions to compensate an accumulated error.
[0019] re-configuring scheduling of communication between the remote device and the base station based on adjusted SPS/CG configuration having an updated time offset configuration.
[0021] receiving, by the remote device, an explicit signaling indicating adjustment of the SPS/CG configuration.
Note: the remote device is the emitter.).
It would have been prima facie obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified the combination with Han’s above teachings. The motivation is improving timeliness and availability of the communication service (Han [0011]).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Law in view of Harada and Kitamoto as applied to claim 1 above, and further in view of US 20210184781 A1 (hereinafter Meng).
Regarding claim 4, the combination teaches The receiver of claim 1.
Although Law teaches wherein: the setup transmission transmitted in accordance with a
communication schedule shared by the emitter and the receiver (Law [0046] The I/O scheduler 180 and/or the controller 104 manages the timing of the input signals originating from the sensors 112b and 116b. The I/O scheduler 180 forwards the input signals to the control loop 202 during each scheduled time period of the control loop 202.
[0061] FIG. 4A is a timing diagram 400 of the example control loop 202 of FIG. 2. The input signals 430-436 originate from the same field device.
[0062] The timing diagram 400 includes the scheduled time period 422a, which is a specified, predetermined, and/or scheduled time period for the control loop 202 to receive the first input signal 430.), the combination does not explicitly teach the setup transmission includes a probe.
Meng in the same or similar field of endeavor teaches the setup transmission includes a probe
(Meng [0241] the first information may be understood as a probe packet. In other words, the first information is a packet used to establish period mapping relationships between periods of the first network device and the periods of the second network device.).
By modifying Law’s teachings of wherein: the setup transmission transmitted in accordance with
a communication schedule shared by the emitter and the receiver
with Meng’s teachings of the setup transmission includes a probe,
the modification results in wherein: the setup transmission includes a probe transmitted in accordance with a communication schedule shared by the emitter and the receiver.
It would have been prima facie obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified the combination with Meng’s above teachings. The motivation is improving packet scheduling timeliness (Meng [0005]).
Claim(s) 8 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Law in view of Han.
Regarding claim 8, Law teaches An emitter comprising (Law [0042] FIG. 2 shows the example
process control system 100 of FIG. 1 including the controller 104. the field devices 112a and 112b. the field devices 116a and 116b.
[0044] the field devices 112a and 112b (e.g., process control devices).
[0016] The field devices, which may include device controllers, valves, valve actuators, valve
positioners, switches and transmitters. A controller receives signals (e.g., input signals) indicative of process measurements made by the field devices and/or other information pertaining to the field devices, uses this information to implement a control routine, and generates control signals (e.g., output signals) that are sent over the buses or other communication lines to the field devices to control the operation of the process.
Note: the field device is the emitter.):
at least one processor (Law [0144] As shown in FIG. 10, the processor system 1010 includes a
processor 1012.); and
memory coupled to the at least one processor, the memory storing computer-executable
instructions (Law system memory 1024 in Fig. 10. [0145] The processor 1012 of FIG. 10 is coupled to a chipset 1018, which includes a memory controller 1020 and a peripheral input/output (I/O) controller 1022. The memory controller 1020 performs functions that enable the processor 1012 (or processors if there are multiple processors) to access a system memory 1024.),
wherein the at least one processor is configured to execute the computer-executable instructions to cause the emitter to (Law [0149] At least some of the above described example methods and/or systems are implemented by one or more software and/or firmware programs running on a computer processor.):
transmit operational data from the emitter to a receiver via a communications link connecting the emitter and the receiver (Law [0016] A controller receives signals (e.g., input signals) indicative of process measurements made by the field devices and/or other information pertaining to the field devices, uses this information to implement a control routine, and generates control signals (e.g., output signals) that are sent over the buses or other communication lines to the field devices to control the operation of the process.); and
receive an adjustment control message from the receiver, the adjustment control message indicating a current variance between a first time at which the receiver expected to receive data transmitted by the emitter and a second time at which the receiver received the data transmitted by the emitter (Law [0042] FIG. 2 shows the example process control system 100 of FIG. 1 including the controller 104 operating a control loop 202. The process components within FIG. 2 include two sets of feedback loops. The first feedback loop includes the field devices 112a and 112b. The second feedback loop includes the field devices 116a and 116b.
[0046] The I/O scheduler 180 and/or the controller 104 manages the timing of the input signals originating from the sensors 112b and 116b. The I/O scheduler 180 forwards the input signals to the control loop 202 during each scheduled time period of the control loop 202.
[0061] FIG. 4A is a timing diagram 400 of the example control loop 202 of FIG. 2. The input signals 430-436 originate from the same field device.
[0062] The timing diagram 400 includes the scheduled time period 422a, which is a specified, predetermined, and/or scheduled time period for the control loop 202 to receive the first input signal 430.
[0063] the first input signal 430 is received during the scheduled time period 422a. However, the second, third, and fourth input signals 432, 434, and 436 are not received during the scheduled time periods 422b-d.
[0048] when the I/O scheduler 180 does not receive input signals during the respective scheduled time periods, the I/O scheduler 180 and/or the controller 104 calculates the time difference between the time at which the input signal was received and its respective scheduled time period (e.g., the beginning or middle of its scheduled time period).
[0048] The I/O scheduler 180 and/or the controller 104 then sends a timing adjustment message to the I/O data acquisition module 190 to adjust the timing of subsequent input signals from the same field device so that the I/O scheduler 180 receives the input signals during the appropriately scheduled time period(s).
[0068] As a result of receiving the timing adjustment message, the I/O data acquisition module 190 adjusts its timing for requesting subsequent input signals from the field device.); and
transmit subsequently transmitted operational data based on the adjustment control message (Law [0048] The I/O scheduler 180 and/or the controller 104 then sends a timing adjustment message to the I/O data acquisition module 190 to adjust the timing of subsequent input signals from the same field device so that the I/O scheduler 180 receives the input signals during the appropriately scheduled time period(s).
[0068] As a result of receiving the timing adjustment message, the I/O data acquisition module 190 adjusts its timing for requesting subsequent input signals from the field device. ).
Law does not explicitly teach determine a first transmission offset; apply the first transmission offset to operational data transmitted from the emitter to a receiver; apply a first adjusted transmission offset to subsequently transmitted operational data.
Han in the same or similar field of endeavor teaches determine a first transmission offset, apply the first transmission offset to operational data transmitted from the emitter to a receiver (Han [0013] transmitting, by a remote device, a Time Sensitive Networking (TSN) traffic pattern to a base station; and configuring scheduling of TSN transmissions between the remote device and the base station based on a TSN traffic configuration; wherein the TSN traffic pattern comprises a periodicity value and a time offset value.
[0016] the TSN traffic configuration is a Semi-Persistent Scheduling/Configured Grant (SPS/CG) configuration.
[0153] Upon receiving the report of TSN traffic pattern from the UE, the gNB converts the arbitrary TSN traffic pattern (periodicity & offset) to symbol-level based periodicity and offset, and configures the UE. In some embodiments, the gNB converts the arbitrary periodicity and offset to symbol-level periodicity configuration and offset configuration, and indicates to UE.),
apply a first adjusted transmission offset to subsequently transmitted operational data (Han [0018] adjusting the SPS/CG configuration for subsequent TSN transmissions to compensate an accumulated error.
[0019] re-configuring scheduling of communication between the remote device and the base station based on adjusted SPS/CG configuration having an updated time offset configuration.
[0021] receiving, by the remote device, an explicit signaling indicating adjustment of the SPS/CG configuration.).
By modifying Law’s teachings of transmit operational data from the emitter to a receiver via a communications link connecting the emitter and the receiver
with Han’s teachings of determine a first transmission offset, apply the first transmission offset to operational data transmitted from the emitter to a receiver,
the modification results in determine a first transmission offset, apply the first transmission offset to operational data transmitted from the emitter to a receiver via a communications link connecting the emitter and the receiver.
By modifying Law’s teachings of transmit subsequently transmitted operational data based on the adjustment control message
with Han’s teachings of apply a first adjusted transmission offset to subsequently transmitted operational data,
the modification results in apply a first adjusted transmission offset, determined based on the adjustment control message, to subsequently transmitted operational data.
It would have been prima facie obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified Law with Han’s above teachings. The motivation is improving timeliness and availability of the communication service (Han [0011]).
Regarding claim 13, Law in view of Han teaches The emitter of claim 8.
Law teaches further comprising: an optical line card configured to communicate with the
receiver via an optical communications link (Law [0003] Each of these field devices is typically coupled to the process controller via one or more I/O cards and a respective communication path (e.g., a two-wire cable, a wireless link, or an optical fiber)).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Law in view of Han as applied to claim 8 above, and further in view of Leclerc.
Regarding claim 11, Law in view of Han teaches The emitter of claim 8.
Although Han teaches wherein the at least one processor is configured to execute the
computer-executable instructions to cause the emitter to: generate the first adjusted transmission offset by updating the first transmission offset by time shifting indicated by the adjustment control message (Han [0018] adjusting the SPS/CG configuration for subsequent TSN transmissions to compensate an accumulated error.
[0019] re-configuring scheduling of communication between the remote device and the base station based on adjusted SPS/CG configuration having an updated time offset configuration.
[0169] Explicit adjustment may be performed by gNB using DCI to indicate SPS/CG pattern adjustment. The explicit signaling may comprise: [0170] i). first information to indicate enabling and disabling of Downlink Control Information (DCI) monitoring; and [0171] ii). second information to indicate shifting of the SPS/CG configuration in time domain.),
It would have been prima facie obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified Law as modified by Han with Han’s above teachings. The motivation is improving timeliness and availability of the communication service (Han [0011]).
Law in view of Han does not explicitly teach the time shifting is in unit of clock cycles.
Leclerc in the same or similar field of endeavor teaches the time shifting is in units of clock cycles (Leclerc [0013] In response to a deterministic packet arriving during an actual clock cycle, circuitry can compare the actual clock cycle to a planned clock cycle for reception of the deterministic packet and corrective actions can be performed to resolve any discrepancies.).
By modifying Han’s teachings of wherein the at least one processor is configured to execute the
computer-executable instructions to cause the emitter to: generate the first adjusted transmission offset by updating the first transmission offset by time shifting indicated by the adjustment control message
with Leclerc’s teachings of the time shifting is in units of clock cycles,
the modification results in
wherein the at least one processor is configured to execute the computer-executable instructions to cause the emitter to: generate the first adjusted transmission offset by updating the first transmission offset by a number of clock cycles indicated by the adjustment control message.
It would have been prima facie obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified Law as modified by Han with Leclerc’s above teachings. The motivation is reducing latency (Leclerc [0010]).
Claim 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Law in view of Han as applied to claim 8 above, and further in view of Kitamoto.
Regarding claim 12, Law in view of Han teaches The emitter of claim 8.
Law in view of Han does not explicitly teach wherein: the adjustment control message includes
one of a dedicated signal generated to transfer variance information, or a non-dedicated signal including the variance information.
Kitamoto in the same or similar field of endeavor teaches wherein: the adjustment control message includes one of a dedicated signal generated to transfer variance information, or a non-dedicated signal including the variance information (Kitamoto page 5, the time difference allowable range confirming means 15 confirms whether or not the time difference is within the allowable range, and the confirmation result is transmitted by the confirmation result transmitting means 16. The confirmation result data is transmitted to the time correction computer 2.).
It would have been prima facie obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified Law as modified by Han with Kitamoto’s above teachings. The motivation is time synchronization between computers connected to each other via a communication line (Kitamoto page 1).
Claim(s) 14-15 and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Law in view of US 20190124006 A1 (hereinafter Thubert).
Regarding claim 14, Law teaches A communication system comprising (Law [0042] FIG. 2 shows
the example process control system 100 of FIG. 1.):
a controller including a processor and a memory storing computer-executable instructions,
wherein the controller is configured to be coupled to an emitter and a receiver, and wherein the processor is configured to execute the computer-executable instructions to cause the controller to (Law [0042] FIG. 2 shows the example process control system 100 of FIG. 1 including the controller 104
[0002] A process controller receives signals indicative of process measurements made by the field devices and/or other information pertaining to the field devices, uses this information to implement a control routine, and generates control signals that are sent over buses or other communication lines to the field devices to control the operation of the process.
[0143] FIG. 10 is a block diagram of an example processor system 1010 that may be used to implement the example methods and apparatus described herein.
[0144] As shown in FIG. 10, the processor system 1010 includes a processor 1012.
[0145] The processor 1012 of FIG. 10 is coupled to a chipset 1018, which includes a memory controller 1020 and a peripheral input/output (I/O) controller 1022. The memory controller 1020 performs functions that enable the processor 1012 (or processors if there are multiple processors) to access a system memory 1024.
[0149] At least some of the above described example methods and/or systems are implemented by one or more software and/or firmware programs running on a computer processor.
Note: process controller is the controller, also the receiver. field device is the emitter.):
receive, from the receiver, information indicating an operational variance between a first time at which a frame transmitted by the emitter arrived at the receiver, and a second time at which the frame transmitted by the emitter was schedule to arrive at the receiver (Law [0042] FIG. 2 shows the example process control system 100 of FIG. 1 including the controller 104 operating a control loop 202. The process components within FIG. 2 include two sets of feedback loops. The first feedback loop includes the field devices 112a and 112b. The second feedback loop includes the field devices 116a and 116b.
[0046] The I/O scheduler 180 and/or the controller 104 manages the timing of the input signals originating from the sensors 112b and 116b. The I/O scheduler 180 forwards the input signals to the control loop 202 during each scheduled time period of the control loop 202.
[0061] FIG. 4A is a timing diagram 400 of the example control loop 202 of FIG. 2. The input signals 430-436 originate from the same field device.
[0062] The timing diagram 400 includes the scheduled time period 422a, which is a specified, predetermined, and/or scheduled time period for the control loop 202 to receive the first input signal 430.
[0063] the first input signal 430 is received during the scheduled time period 422a. However, the second, third, and fourth input signals 432, 434, and 436 are not received during the scheduled time periods 422b-d.
[0048] when the I/O scheduler 180 does not receive input signals during the respective scheduled time periods, the I/O scheduler 180 and/or the controller 104 calculates the time difference between the time at which the input signal was received and its respective scheduled time period (e.g., the beginning or middle of its scheduled time period). ); and
transmit an updated communication schedule to the emitter and the receiver (Law [0048] The I/O scheduler 180 and/or the controller 104 then sends a timing adjustment message to the I/O data acquisition module 190 to adjust the timing of subsequent input signals from the same field device so that the I/O scheduler 180 receives the input signals during the appropriately scheduled time period(s).
[0068] As a result of receiving the timing adjustment message, the I/O data acquisition module 190 adjusts its timing for requesting subsequent input signals from the field device.
[0039] As a result of the new field device, the I/O scheduler 180 and/or the controller 104 updates the timing of the scheduled time periods to receive input signals to correspond to the changes in the control loop.).
Law does not explicitly teach transmit a communication schedule to the emitter and the receiver, wherein the communication schedule designates periods for communication between the emitter and the receiver via a deterministic-compliant communications link.
Thubert in the same or similar field of endeavor teaches transmit a communication schedule to the emitter and the receiver, wherein the communication schedule designates periods for communication between the emitter and the receiver via a deterministic-compliant communications link (Thubert [0028] Further, deterministic networking can establish stringent deterministic constraints based on defining a transmission schedule relative to: (1) a period of time “T”; (2) a maximum packet size “F”; and a maximum number of data packets “N” that can be transmitted on a deterministic link within the period of time “T”. Hence, a deterministic network interface circuit can transmit on a deterministic link, at a scheduled transmission time within the period of time “T”, a maximum number of “N” data packets having a maximum size “F”.
[0030] FIGS. 1A-1J illustrate one or more host devices 10, 10′, each comprising a processor circuit 12 configured for executing a transport layer 14 for providing deterministic transport of transport layer packets 16 across multiple deterministic links 18 in an example deterministic data network 20. The deterministic data network 20 also can include a network manager device 24 configured for controlling establishment of the deterministic links 18, by the deterministic network interface circuits 22, according to prescribed deterministic constraints established and maintained by the network manager device 24. In particular, the network manager device 24 can send instructions to each of the deterministic network interface circuits 22 for establishment of a deterministic link 18 with a peer deterministic network interface circuit (i.e., peer deterministic interface circuits) 22 according to the above-described deterministic constraints, including for example a transmission time “t_TSN” according to a repeating schedule, a prescribed transmission period of time “T”, and a maximum number of “N” data packets having a maximum size “F” that can be transmitted during the transmission time period “T”.
Note: network manager device 24 is the controller.).
It would have been prima facie obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified Law with Thubert’s above teachings. The motivation is correcting latency (Thubert [0001]).
Regarding claim 15, Law in view of Thubert teaches The communication system of claim 14.
Law teaches wherein: the updated communication schedule is based on the information
indicating the operational variance (Law [0046] The I/O scheduler 180 and/or the controller 104 manages the timing of the input signals originating from the sensors 112b and 116b. The I/O scheduler 180 forwards the input signals to the control loop 202 during each scheduled time period of the control loop 202.
[0061] FIG. 4A is a timing diagram 400 of the example control loop 202 of FIG. 2. The input signals 430-436 originate from the same field device.
[0062] The timing diagram 400 includes the scheduled time period 422a, which is a specified, predetermined, and/or scheduled time period for the control loop 202 to receive the first input signal 430.
[0063] the first input signal 430 is received during the scheduled time period 422a. However, the second, third, and fourth input signals 432, 434, and 436 are not received during the scheduled time periods 422b-d.
[0048] when the I/O scheduler 180 does not receive input signals during the respective scheduled time periods, the I/O scheduler 180 and/or the controller 104 calculates the time difference between the time at which the input signal was received and its respective scheduled time period (e.g., the beginning or middle of its scheduled time period).
[0048] The I/O scheduler 180 and/or the controller 104 then sends a timing adjustment message to the I/O data acquisition module 190 to adjust the timing of subsequent input signals from the same field device so that the I/O scheduler 180 receives the input signals during the appropriately scheduled time period(s).
[0068] As a result of receiving the timing adjustment message, the I/O data acquisition module 190 adjusts its timing for requesting subsequent input signals from the field device.).
Regarding claim 17, Law in view of Thubert teaches The communication system of claim 14.
Law does not explicitly teach wherein: the controller transmits the communication schedule via
a second communications link different from the deterministic-compliant communications link.
Thubert teaches wherein: the controller transmits the communication schedule via a second
communications link different from the deterministic-compliant communications link (Thubert [0030] the network manager device 24 can send instructions to each of the deterministic network interface circuits 22 for establishment of a deterministic link 18 with a peer deterministic network interface circuit (i.e., peer deterministic interface circuits) 22 according to the above-described deterministic constraints, including for example a transmission time “t_TSN” according to a repeating schedule, a prescribed transmission period of time “T”, and a maximum number of “N” data packets having a maximum size “F” that can be transmitted during the transmission time period “T”.
[0041] the non-deterministic data connection could exist within the physical data network (e.g., LAN and/or WAN) that is used to deploy the deterministic data network 20, or deterministic data network 20′. one or more of the 10, 10′, 10″, 24, 28, and/or 38 (e.g., the host devices 10, 10′ and/or 10″) can include both the device interface circuit 52 for non-deterministic communications (e.g., with the network manager device 24) and plural deterministic network interface circuits 22 for deterministic communications as described herein.).
It would have been prima facie obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified Law as modified by Thubert with Thubert’s above teachings. The motivation is correcting latency (Thubert [0001]).
Regarding claim 18, Law in view of Thubert teaches The communication system of claim 17.
Thubert teaches wherein: the controller transmits the schedule via a dedicated control link (Thubert [0030] the network manager device 24 can send instructions to each of the deterministic network interface circuits 22 for establishment of a deterministic link 18 with a peer deterministic network interface circuit (i.e., peer deterministic interface circuits) 22 according to the above-described deterministic constraints, including for example a transmission time “t_TSN” according to a repeating schedule, a prescribed transmission period of time “T”, and a maximum number of “N” data packets having a maximum size “F” that can be transmitted during the transmission time period “T”. ).
It would have been prima facie obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified Law as modified by Thubert with Thubert’s above teachings. The motivation is correcting latency (Thubert [0001]).
Regarding claim 19, Law in view of Thubert teaches The communication system of claim 18.
Law teaches wherein: the controller is included in a same physical device as at least one of the
emitter or the receiver (Law [0042] FIG. 2 shows the example process control system 100 of FIG. 1 including the controller 104.
[0002] A process controller receives signals indicative of process measurements made by the field devices and/or other information pertaining to the field devices, uses this information to implement a control routine, and generates control signals that are sent over buses or other communication lines to the field devices to control the operation of the process.
[0143] FIG. 10 is a block diagram of an example processor system 1010 that may be used to implement the example methods and apparatus described herein.
[0144] As shown in FIG. 10, the processor system 1010 includes a processor 1012.
[0145] The processor 1012 of FIG. 10 is coupled to a chipset 1018, which includes a memory controller 1020 and a peripheral input/output (I/O) controller 1022. The memory controller 1020 performs functions that enable the processor 1012 (or processors if there are multiple processors) to access a system memory 1024.
[0149] At least some of the above described example methods and/or systems are implemented by one or more software and/or firmware programs running on a computer processor.
Note: process controller is the controller, also the receiver. field device is the emitter.).
Regarding claim 20, Law in view of Thubert teaches The communication system of claim 18.
Thubert teaches wherein: the deterministic-compliant communications link includes an optical
communications link (Thubert [0043] Any one of the devices 10, 10′, 10″, 24, 28, and/or 38 also can be configured for a different type of deterministic link 18 or data link 56, as appropriate (e.g., a wired or wireless link, an optical link, etc.).).
It would have been prima facie obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified Law as modified by Thubert with Thubert’s above teachings. The motivation is correcting latency (Thubert [0001]).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Law in view of Thubert as applied to claim 15 above, and further in view of Leclerc.
Regarding claim 16, Law in view of Thubert teaches The communication system of claim 15.
Although Law teaches wherein: the updated communication schedule is modified to account for
time difference between the emitter and the receiver (Law [0048] when the I/O scheduler 180 does not receive input signals during the respective scheduled time periods, the I/O scheduler 180 and/or the controller 104 calculates the time difference between the time at which the input signal was received and its respective scheduled time period (e.g., the beginning or middle of its scheduled time period).
[0048] The I/O scheduler 180 and/or the controller 104 then sends a timing adjustment message to the I/O data acquisition module 190 to adjust the timing of subsequent input signals from the same field device so that the I/O scheduler 180 receives the input signals during the appropriately scheduled time period(s).), Law in view of Thubert does not explicitly teach scheduling correction based on the clock drift.
Leclerc in the same or similar field of endeavor teaches scheduling correction based on the clock drift (Leclerc [0028] deterministic scheduler 410 compare the actual reception time of packets and the time intervals that are allocated for deterministic flows to detect clock shifts or inconsistencies and to manage corrective actions based on the detected clock shifts or inconsistencies.).
By modifying Law’s teachings of wherein: the updated communication schedule is modified to account for time difference between the emitter and the receiver with Leclerc’s teachings of scheduling correction based on the clock drift, the modification results in wherein: the updated communication schedule is modified to account for a drift between a clock used by the emitter and a second clock used by the receiver.
It would have been prima facie obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified Law as modified by Thubert with Leclerc’s above teachings. The motivation is reducing latency (Leclerc [0010]).
Allowable Subject Matter
Claims 9 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior arts of record for the claim 8 (parent claim of 9) is Law (US 20110054640 A1) and Han (US 20220304010 A1), the closest prior arts of record for the claim 9 is US 20130138800 A1 (hereinafter Gelter) and CN 101534222 A (hereinafter Zhang). Law teaches an emitter adjusting timing of transmission based on the control message from the receiver. Han teaches determining and applying transmission offset at the emitter for TSN traffic. Gelter teaches a talker determining an optimal presentation time with a listener based on the maximum latency. Zhang teaches delay variation measuring method including determining network transmission delay difference of the pair of the detection messages.
However the prior arts of record, in single or combination, does not teach, suggest or provide rational for “iteratively perform the following until a message is received from the receiver indicating that the communications link is ready for transmission of operational data:
transmit a setup probe to the receiver via the communications link;
receive a setup control message from the receiver indicating a setup variance between a third time at which the receiver expected to receive the setup probe, and a fourth time at which the receiver received the setup probe; and
adjust the first transmission offset based on the setup variance.”.
Claim 10 is allowed due to its dependency on claim 9.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David Z Sun whose telephone number is (571)270-0750. The examiner can normally be reached Monday-Friday 0800am-0500pm.
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/D.Z.S./Examiner, Art Unit 2418
/Moo Jeong/Supervisory Patent Examiner, Art Unit 2418
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