Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the filing of the Applicant Arguments/Remarks Made in an Amendment on 08/07/2026. Currently, claims 1-20 are pending in the application. Claims 4-7, 9-11 and 13-20 are withdrawn from Consideration.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al (US 20180226312 A1).
Regarding claim 1, Figure 2 of Kim discloses a semiconductor package, comprising:
a lower-layer structure including a substrate (110, [0031]);
a first chip (130) including bumps (132, [0038]) on an active surface thereof, the first chip being electrically connected to the substrate via the bumps;
an upper-layer (150, [0043]) structure including first molding material, the first molding material covering an inactive surface (upper surface of 130) of the first chip and surrounding a portion of a lateral surface of the first chip, the inactive surface of the first chip being opposite to the active surface (bottom surface of 130 at 132) of the first chip; and
a middle-layer (140, [0040]) structure including at least one interlayer, the middle-layer structure surrounding a remaining portion of the lateral surface of the first chip, the at least one interlayer including a second molding material different from the first molding material (considering 140 and 150 are different from the list of [0040] and [0043]), the middle-layer structure being between the lower-layer structure and the upper-layer structure and filling a space between the lower-layer structure and the upper-layer-structure,
wherein the upper-layer (150) structure is spaced apart from the lower-layer structure (110) by the middle-layer structure, along a direction from the lower-layer structure to the upper-layer structure.
Regarding claim 2, Figure 2 of Kim discloses that the semiconductor package as claimed in claim 1, wherein the first molding material (150, [0043]) includes a rigid material or a flexible material, and the second molding material (140) includes a flexible material ([0040]).
Regarding claim 3, Figure 2 of Kim discloses that the semiconductor package as claimed in in claim 2, wherein the second molding material (140, [0040]) covers the active surface of the first chip, and surrounds the remaining portion of the lateral surface of the first chip, the remaining portion of the lateral surface of the first chip being a portion excluding the portion of the lateral surface of the first chip (130).
Regarding claim 8, Figure 2 of Kim discloses that the semiconductor package as claimed in claim 2, wherein the upper-layer structure (150) has a first thickness, the middle-layer structure (140) has a second thickness, and a ratio of the first thickness to the second thickness is configured to control a warpage of the semiconductor package ([0042]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 12 is rejected under 35 U.S.C. 103 as being obvious over Kim et al (US 20180226312 A1) in view of KIM et al (US 20210066244 A1, hereinafter as “K4”).
Regarding claim 12, Figure 2 of Kim discloses that the semiconductor package as claimed in claim 2, wherein the first molding material (150) includes the flexible material ([0043]), the first chip (130) includes a plurality of first chips (two of 130 is shown).
Kim does not explicitly teach that the semiconductor package further includes: a plurality of second chips, stacked on the plurality of first chips, respectively, wherein the plurality of first chips and the plurality of second chips respectively have sizes and stacking forms different from one another to form a complex stacking structure.
However, K4 is a pertinent art which teaches a semiconductor package having high performance and miniaturization of packages implemented using a system in package (SIP) technology in which a plurality of semiconductor chips having various functions are embedded in a single package ([0003]). Figures 1-20 of K4 teach such packages wherein a plurality of second chips, stacked on a plurality of first chips, respectively, wherein the plurality of first chips and the plurality of second chips respectively have sizes and stacking forms different from one another to form a complex stacking structure.
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Kim with a plurality of second chips, stacked on the plurality of first chips, respectively, wherein the plurality of first chips and the plurality of second chips respectively have sizes and stacking forms different from one another to form a complex stacking structure according to the teaching of K4 in order to form a package with high performance and miniaturization of packages implemented using a system in package (SIP) technology in which a plurality of semiconductor chips having various functions are embedded in a single package ([0003] of K4).
Response to Arguments
Applicant’s arguments/amendments regarding the rejection of claims 1-3, 8 and 12, filed on 08/07/2026, have been fully considered but arguments are moot because newly added limitation to the claim (s) requires a new ground of rejection necessitated by amendments.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday to Friday from 8:00 AM to 5:00 PM (Eastern Time).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KHAJA AHMAD/
Primary Examiner, Art Unit 2813
