Prosecution Insights
Last updated: August 18, 2026
Application No. 18/399,354

TECHNOLOGIES FOR BACK SIDE MICRO-LED ASSEMBLIES

Final Rejection §103
Filed
Dec 28, 2023
Examiner
KHAN, IBRAHIM A
Art Unit
2628
Tech Center
2600 — Communications
Assignee
Intel Corporation
OA Round
2 (Final)
82%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
462 granted / 562 resolved
+20.2% vs TC avg
Moderate +12% lift
Without
With
+12.5%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
15 currently pending
Career history
579
Total Applications
across all art units

Statute-Specific Performance

§101
2.5%
-37.5% vs TC avg
§103
70.6%
+30.6% vs TC avg
§102
11.9%
-28.1% vs TC avg
§112
8.1%
-31.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 562 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION I. RESPONSE TO AMENDMENT Acknowledgment is made of the amendment filed 05/27/2026, in which:claims 1, 11-12, and 18 are amended; claims 10 and 9-20 are cancelled; new claims 21-23 are added; and the rejections of the claims are traversed. Claims 1-9 and 11-23 are currently pending and an Office Action on the merits follows. II. ALLOWABLE SUBJECT MATTER Claims 1-9 and 11-12, 18 and 23 are allowable. Claims 1-9 and 11-12 are allowable because the cited references do not disclose “wherein a plurality of transistors are defined at a front end-of-line (FEOL) portion of the integrated circuit die, wherein the micro-LED assembly is mounted on a back side of the integrated circuit die, wherein a plurality of through-silicon vias are defined in the integrated circuit die, wherein the plurality of through-silicon vias connect the plurality of transistors to the micro-LED assembly”. Claims 18 and 23 are allowable because the cited references do not disclose “wherein the means for converting electrical signals comprises a light- emitting diode (LED) assembly mounted on a side of the IHS opposite a side of the IHS facing the integrated circuit die”. Claims 21-22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 21 is objected because the cited prior art references do not disclose apparatus of claim 18, “wherein a plurality of through-silicon vias are defined in the integrated circuit die, wherein a plurality of through-integrated-heat-spreader vias are defined in the integrated heat spreader, wherein individual through-integrated-heat-spreader vias of the plurality of through-integrated-heat-spreader vias are connected to a corresponding through-silicon via of the plurality of through-silicon vias, and wherein the light-emitting diode assembly is electrically connected to the plurality of through-integrated-heat-spreader vias by solder balls.” Claim 22 is objected because the cited prior art references do not disclose “wherein the LED assembly is directly mounted on a top side of the IHS, wherein one or more integrated circuit dies are located on a bottom side of the IHS with only a thermal interface material between the IHS and the one or more integrated circuit dies. CLAIM REJECTIONS - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 , if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 1. Claims 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Pocock et al. US 20240385394 in view of Daeschner et al. US 20200313057. Consider claim 13. Pocock discloses an apparatus see fig. 1 microLED transmitter and receiver comprising: a substrate fig. 9 substrate 913; one or more integrated circuit dies mounted on the substrate fig. 9 IC 911 on substrate 913; a light-emitting diode (LED) assembly comprising a plurality of LEDs fig. 9 MicroLEDs are below the lenses 915 [0045] MicroLEDs and or PDs mounted to the chip. fig. 10 microLEDs 1014 ; Pocock does not disclose an integrated heat spreader (IHS) mounted on the substrate, the IHS thermally coupled to the one or more integrated circuit dies; and wherein the LED assembly is mounted on the IHS. Daeschner however, discloses an integrated heat spreader (IHS) mounted on the substrate[0045] lead frame 20 with interconnects 25 and frame 23 generally serves as an integrated heat transferor and may connect the Led device to a PCB board (the substrate), the IHS thermally coupled to the one or more integrated circuit dies; and wherein the LED assembly is mounted on the IHS [0045] see fig. 1a-1d LED mounted on top of the frame 20 which mounted to PCB which connects to other components such as ICs. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the micro LED assembly of Pocock to include an integrated heat spreader (IHS) mounted on the substrate, the IHS thermally coupled to the one or more integrated circuit dies; and wherein the LED assembly is mounted on the IHS, as taught by Daeschner, to emit electromagnetic radiation [0007] furthermore to emit high intensity light and enabling high speed operation. Consider claim 14. Pocock as modified by Daeschner discloses the apparatus of claim 13, further comprising: an optical receptacle Pocock [0010] The ferrule may be, for example, a multi-fiber push on (MPO) connector or an MTP connector or, for example, a similar connector. fig. 2 fig. 6 and fig. 9 which shows the ferrule of the optical fiber bundle aligned with the microLEDs mounted on the IHS Daeschner fig. 1a-1d [0045], wherein the optical receptacle is to align an optical plug to couple light from the LED assembly Pocock [0010] The ferrule may be, for example, a multi-fiber push on (MPO) connector or an MTP connector or, for example, a similar. fig. 2 fig. 6 and fig. 9 which shows the ferrule of the optical fiber bundle aligned with the microLEDs. Consider claim 15. Pocock as modified by Daeschner discloses the apparatus of claim 14, further comprising: the optical plug, wherein the optical plug is mated with the optical receptacle Pocock [0010] The ferrule may be, for example, a multi-fiber push on (MPO) connector or an MTP connector or, for example, a similar connector; and one or more optical fiber cores, wherein the one or more optical fiber cores terminate at the optical plug, wherein individual optical fiber cores of the one or more optical fiber cores are aligned to a corresponding LED of the LED assembly Pocock [0010] The ferrule may be, for example, a multi-fiber push on (MPO) connector or an MTP connector or, for example, a similar connector. fig. 2 fig. 6 and fig. 9 which shows the ferrule of the optical fiber bundle aligned with the microLEDs. Consider claim 16. Pocock as modified by Daeschner discloses the apparatus of claim 15, further comprising one or more microlenses to couple light between the plurality of LEDs and the one or more optical fiber cores see fig. 9 lenses 915 are on top of the microLEDs and below the ferrule 921 with optical fiber bundle. 2. Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Pocock et al. US 20240385394 in view of Daeschner et al. US 2020313057 and further in view of Jiang et al. US 20240038949. Consider claim 17. Pocock as modified by Daeschner discloses the apparatus of claim 13, wherein a plurality of transistors are defined [0047] active layer includes transistors for microLED driver circuits but does not disclose are defined at a front end-of-line (FEOL) portion of the integrated circuit die, wherein the micro-LED assembly is mounted on a back side of the integrated circuit die, wherein a plurality of through-silicon vias are defined in the integrated circuit die, wherein the plurality of through-silicon vias connect the plurality of transistors to the micro-LED assembly. Jiang however discloses are defined at a front end-of-line (FEOL) portion of the integrated circuit die, wherein the micro-LED assembly is mounted on a back side of the integrated circuit die, wherein a plurality of through-silicon vias are defined in the integrated circuit die, wherein the plurality of through-silicon vias connect the plurality of transistors to the micro-LED assembly [0021] FEOL devices layer include ICs fabricated by a FEOL operation. the device layer includes transistors. [0022] interconnection structure 120 connects light emitting element 132 and includes features fabricated by back end of line operation. [0026]the light emitting element includes microLED. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the micro LED assembly of Pocock as modified by Daeschner to include are defined at a front end-of-line (FEOL) portion of the integrated circuit die, wherein the micro-LED assembly is mounted on a back side of the integrated circuit die, wherein a plurality of through-silicon vias are defined in the integrated circuit die, wherein the plurality of through-silicon vias connect the plurality of transistors to the micro-LED assembly, as taught by Jiang, for improved temperature control of the light emitting package [0059]. RESPONSE TO ARGUMENTS Applicant's arguments have been fully considered but are not persuasive. Regarding claims 13-14 the Applicant argues (pages 10-12) that Pocock in view Daeschner does not disclose the features of the claims. Specifically the Applicant argues that the claims is directed to a particular arrangement outline by the claim language. The Applicant argues that neither Pocock nor Daeschner discloses this arrangement, alone or in combination. The Applicant argues that the claim requires an integrated heat spreader in relation to both the substrate and the IC die with the light emitting diode assembly mounted on that integrated heat spreader. The Applicant further argues that Daeschner discloses a lead frame 20 as the heat spreader but Daeschner’s lead frame structure in an LED package is not an integrated heat spreader mounted on a substrate and thermally couped to one or more integrated circuit dies as recited. The Applicant argues that the claims were interpreted as far broader than the claim language read in light of the specification. Regarding claim 14 the Applicant argues (page 13-14) that Pocock in view Daeschner does not disclose a receptacle mounted on the integrated heat spreader The Office however respectfully disagrees. Regarding claim 13 Pocock discloses an apparatus see fig. 1 microLED transmitter and receiver comprising: a substrate fig. 9 substrate 913; one or more integrated circuit dies mounted on the substrate fig. 9 IC 911 on substrate 913; a light-emitting diode (LED) assembly comprising a plurality of LEDs fig. 9 MicroLEDs are below the lenses 915 [0045] MicroLEDs and or PDs mounted to the chip. fig. 10 microLEDs 1014. Pocock does not disclose an integrated heat spreader (IHS) mounted on the substrate, the IHS thermally coupled to the one or more integrated circuit dies; and wherein the LED assembly is mounted on the IHS. Daeschner, [0020-0021] discloses an LED device in an LED assembly and used in devices like cameras cellphones, HUDs etc. Daeschner also discloses an integrated heat spreader (IHS) mounted on the substrate[0045] lead frame 20 with interconnects 25 and frame 23 generally serves as an integrated heat transferor and may connect the Led device to a PCB board (the substrate), the IHS thermally coupled to the one or more integrated circuit dies; and wherein the LED assembly is mounted on the IHS [0045] see fig. 1a-1d LED mounted on top of the frame 20 which mounted to PCB which connects to other components such as ICs. For clarification purposes, see [0066] where Daeschner discloses that a microcontroller (IC) has an LED array mounted on it. Therefore, Daeschner discloses the IHS thermally coupled to one or more integrated circuit dies and wherein the LED assembly is mounted on the HIS. Regrading claim 14 the Office disagrees. Pocock as modified by Daeschner disclose the contended limitation because the claim does not specify how or where, specifically, the optical receptacle is mounted on the IHS. In addition, as explained with regards to claim 13, the combination of Pocock and Daeschner disclose an IHS mounted on the substrate and LEDs mounted to the IHS (with no specific location). Therefore, the optical receptacle shown in Pocock’s fig. 2, 6, and 9 (is mounted on the substrate 913 and mounted on the IC 911 and lens 915 over microLEDS ) and which when combined with Daeschner is also mounted on the IHS. V.CONCLUSION THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to IBRAHIM A KHAN whose telephone number is (571)270-7998. The examiner can normally be reached on 10am-6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nitin Patel can be reached on 571-272-7677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. IBRAHIM A. KHAN Primary Examiner Art Unit 2628 /IBRAHIM A KHAN/ 06/24/2026Primary Examiner, Art Unit 2628
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Prosecution Timeline

Dec 28, 2023
Application Filed
Feb 27, 2026
Non-Final Rejection mailed — §103
Mar 30, 2026
Interview Requested
May 22, 2026
Examiner Interview Summary
May 22, 2026
Applicant Interview (Telephonic)
May 27, 2026
Response Filed
Jun 29, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
82%
Grant Probability
95%
With Interview (+12.5%)
2y 1m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 562 resolved cases by this examiner. Grant probability derived from career allowance rate.

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