Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In the response to this office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
INFORMATION DISCLOSURE STATEMENT
The information disclosure statement filed 02/22/2024, has been acknowledged and considered by the examiner. An initialed copy of the PTO-1449 is included in this correspondence.
II. CLAIM INTERPRETATION - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Claims 18-20 recite the limitation “means for converting electrical signals from the integrated circuit die to optical signals”, and has/have been interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112.
Since the claim limitation(s) invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, claim(s) 18-20 have been interpreted to cover the corresponding structure described in the specification that achieves the claimed function, and equivalents thereof.
A review of the specification shows that the following appears to be the corresponding structure described in the specification for the 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph limitation: “means for converting electrical signals from the integrated circuit die to optical signals” ([0025] microLED die 204 convert electrical signals sent form the circuitry on the front side of the IC die 106)… The optical signal is converted to an electrical signal at a photodetector die 205 “
If applicant wishes to provide further explanation or dispute the examiner’s interpretation of the corresponding structure, applicant must identify the corresponding structure with reference to the specification by page and line number, and to the drawing, if any, by reference characters in response to this Office action.
If applicant does not intend to have the claim limitation(s) treated under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112 , sixth paragraph, applicant may amend the claim(s) so that it/they will clearly not invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, or present a sufficient showing that the claim recites/recite sufficient structure, material, or acts for performing the claimed function to preclude application of 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
For more information, see MPEP § 2173 et seq. and Supplementary Examination Guidelines for Determining Compliance With 35 U.S.C. 112 and for Treatment of Related Issues in Patent Applications, 76 FR 7162, 7167 (Feb. 9, 2011).
CLAIM REJECTIONS - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention
1. Claims 1-4 and 18-19 are rejected under 35 U.S.C. 102 (a) (2) as being anticipated by Pocock et al. US 20240385394.
Consider claim 1. Pocock discloses an apparatus see fig. 1 microLED transmitter and receiver comprising:
an integrated circuit die fig. 9 IC 911; and
a micro-light-emitting diode (micro-LED) assembly comprising one or more micro-LEDs fig. 9 MicroLEDs are below the lenses 915 [0045] MicroLEDs and or PDs mounted to the chip. fig. 10 microLEDs 1014 ;
wherein the micro-LED assembly is mounted on the integrated circuit die [0045] MicroLEDs and or PDs mounted to the chip;
Consider claim 2. Pocock discloses the apparatus of claim 1, further comprising:
an optical receptacle mounted on the integrated circuit die, wherein the optical receptacle is to align an optical plug to couple light from the micro-LED assembly fig. 2 fig. 6 coupling optics blocks 511 and optical fibers are aligned [0031] and [0010] Additional alignment keying features may be added to the coupling optics block and ferrule to enable accurate passive alignment of the transmission medium to the micro LED/PD arrays. A second outer dam structure may be added to components outside of the coupling optics block, which could also aid in mechanically holding and aligning the optical transmission medium to the micro LED/PD assembly. [0043]
Consider claim 3. Pocock discloses the apparatus of claim 2, further comprising: the optical plug, wherein the optical plug is mated with the optical receptacle and [0010] The ferrule may be, for example, a multi-fiber push on (MPO) connector or an MTP connector or, for example, a similar connector; and one or more optical fiber cores, wherein the one or more optical fiber cores terminate at the optical plug and [0010] The ferrule may be, for example, a multi-fiber push on (MPO) connector or an MTP connector or, for example, a similar, wherein individual optical fiber cores of the one or more optical fiber cores are aligned to a corresponding micro-LED of the micro-LED assembly and [0010] The ferrule may be, for example, a multi-fiber push on (MPO) connector or an MTP connector or, for example, a similar. fig. 2 fig. 6 and fig. 9 which shows the ferrule of the optical fiber bundle aligned with the microLEDs.
Consider claim 4. Pocock discloses the apparatus of claim 3, further comprising one or more microlenses to couple light between the one or more micro-LEDs and the one or more optical fiber cores see fig. 9 lenses 915 are on top of the microLEDs and below the ferrule 921 with optical fiber bundle.
Consider claim 18. Pocock discloses an apparatus see fig. 1 microLED transmitter and receiver comprising:
a substrate fig. 9 substrate 913;
an integrated circuit die mounted on the substrate fig. 9 IC 911 on substrate 913;
and means for converting electrical signals from the integrated circuit die to optical signals fig. 9 MicroLEDs are below the lenses 915 [0045] MicroLEDs and or PDs mounted to the chip. fig. 10 microLEDs 1014 , wherein the means for converting electrical signals from the integrated circuit die to optical signals is positioned above the integrated circuit die and the substrate fig. 9 MicroLEDs are below the lenses 915 but above substrate 913 and IC 911.
Consider claim 19. Pocock discloses the apparatus of claim 18, wherein the means for converting electrical signals is mounted on the integrated circuit die fig. 9 MicroLEDs are below the lenses 915 but mounted on the IC 911.
CLAIM REJECTIONS - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 , if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 5 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Pocock et al. US 20240385394.in view of Pfister et al. US 20240118508.
Consider claim 5. Pocock discloses the apparatus of claim 1, but does not disclose wherein the one or more micro-LEDs comprise gallium and nitrogen.
Pfister however discloses wherein the one or more micro-LEDs comprise gallium and nitrogen [0007] microLED including material comprising at least an n type gallium and nitrogen containing region
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the micro LED assembly of Pocock to include wherein the one or more micro-LEDs comprise gallium and nitrogen, as taught by Pfister, to emit electromagnetic radiation [0007] furthermore to emit high intensity light and enabling high speed operation.
Consider claim 8. Pocock discloses the apparatus of claim 7, further comprising a circuit board, wherein the integrated circuit die is mounted on the circuit board fig. 9 package substrate 913, but does not disclose wherein the second integrated circuit die is mounted on the circuit board.
Pfister however discloses wherein the second integrated circuit die is mounted on the circuit board. fig. 1B optical interconnect are mounted between two ICs on the same circuit board. also see fig. 8.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the micro LED assembly of Pocock to include the second integrated circuit die is mounted on the circuit board., as taught by Pfister, to emit electromagnetic radiation [0007] furthermore to emit high intensity light and enabling high speed operation.
3. Claim 6-7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Pocock et al. US 20240385394 in view of Mohammad US 20250140766.
Consider claim 6. Pocock discloses the apparatus of claim 1, wherein the micro-LED assembly further comprises one or more photodetectors [0045] fig. 9 shows microLED assembly where the microLEDs and PDs (photodetectors) are mounted to the chip 911. also see [0047] fig. 10 IC chip 1011 includes microLEDs and PDs.
Pocock does not disclose that the PDs are photodiodes.
Mohammad however discloses using photodiodes to detect light [0033][0037] [0046] array of sensors including photodetectors or photodiodes. fig. 1B photodiode arrays 108 and 108-1
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the micro LED assembly of Pocock to include photodiodes, as taught by Mohammad, to use simple sensors that are not required to measure light intensity of capture frequency [0040] to measure on and off state of microLEDs [0046].
Consider claim 7. Pocock as modified by Mohammad discloses the apparatus of claim 6, further comprising:
a second integrated circuit die different from the integrated circuit die; a second micro-LED assembly, wherein the second micro-LED assembly comprises one or more micro-LEDs and one or more photodiodes See Mohammad fig. 1B which show two IC and fig. 2 shows the side via of a single chip package 100 is connected to 100-1 where 109 is connected to 107 via fiber optic elements 104, wherein the second micro-LED assembly is mounted on the second integrated circuit die; and an optical cable that optically couples the micro-LED assembly and the second micro-LED assembly. See Mohammad fig. 1B which show two IC and fig. 2 shows the side via of a single chip package 100 is connected to 100-1 where 109 is connected to 107 via fiber optic elements 104.
Motivation to combine is similar to motivation in claim 6.
Consider claim 9. Pocock as modified by Mohammad discloses the apparatus of claim 7, further comprising a first circuit board and a second circuit board different from the first circuit board, wherein the integrated circuit die is mounted on the first circuit board, wherein the second integrated circuit die is mounted on the second circuit board See Mohammad fig. 1B which show two IC and fig. 2 shows the side via of a single chip package 100 is connected to 100-1 where 109 is connected to 107 via fiber optic elements 104
Motivation to combine is similar to motivation in claim 6.
4. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Pocock et al. US 20240385394 in view of Jiang et al. US 20240038949.
Consider claim 10. Pocock discloses the apparatus of claim 1, wherein a plurality of transistors [0047] active layer includes transistors for microLED driver circuits
but does not disclose are defined at a front end-of-line (FEOL) portion of the integrated circuit die, wherein the micro-LED assembly is mounted on a back side of the integrated circuit die, wherein a plurality of through-silicon vias are defined in the integrated circuit die, wherein the plurality of through-silicon vias connect the plurality of transistors to the micro-LED assembly.
Jiang however discloses are defined at a front end-of-line (FEOL) portion of the integrated circuit die, wherein the micro-LED assembly is mounted on a back side of the integrated circuit die, wherein a plurality of through-silicon vias are defined in the integrated circuit die, wherein the plurality of through-silicon vias connect the plurality of transistors to the micro-LED assembly [0021] FEOL devices layer include ICs fabricated by a FEOL operation. the device layer includes transistors. [0022] interconnection structure 120 connects light emitting element 132 and includes features fabricated by back end of line operation. [0026]the light emitting element includes microLED.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the micro LED assembly of Pocock to include are defined at a front end-of-line (FEOL) portion of the integrated circuit die, wherein the micro-LED assembly is mounted on a back side of the integrated circuit die, wherein a plurality of through-silicon vias are defined in the integrated circuit die, wherein the plurality of through-silicon vias connect the plurality of transistors to the micro-LED assembly, as taught by Jiang, for improved temperature control of the light emitting package [0059].
5. Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Pocock et al. US 20240385394 in view of Jiang et al. US 20240038949 and further in view of Mohammad US 20250140766.
Consider claim 11. Pocock as modified by Jiang discloses the apparatus of claim 10, but does not disclose wherein the plurality of transistors are to modulate an amplitude of the one or more micro-LEDs using the plurality of through-silicon via see Jiang [0021-0022][0026] fig. 1 as a rate of at least one gigahertz.
Mohammad however discloses modulate an amplitude of the one or more micro-LEDs as a rate of at least one gigahertz [0144] wherein a state for each of the first microLEDs of the plurality of first microLEDs changes at a rate of 1 Ghz or more.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the micro LED assembly of Pocock to include modulate an amplitude of the one or more micro-LEDs as a rate of at least one gigahertz , as taught by Jiang, for optical interconnects with increased bandwidth [0003].
Consider claim 12. Pocock as modified by Jiang discloses the apparatus of claim 10, but does not disclose wherein the plurality of transistors are to modulate an amplitude of the one or more micro-LEDs using the plurality of through-silicon via see Jiang [0021-0022][0026] fig. 1 as a rate of at least one gigahertz.
Mohammad however discloses modulate an amplitude of the one or more micro-LEDs as a rate of at least five gigahertz [0144] wherein a state for each of the first microLEDs of the plurality of first microLEDs changes at a rate of 1 Ghz or more.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the micro LED assembly of Pocock to include modulate an amplitude of the one or more micro-LEDs as a rate of at least five gigahertz , as taught by Jiang, for optical interconnects with increased bandwidth [0003].
6. Claims 13-16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Pocock et al. US 20240385394 in view of Daeschner et al. US 20200313057.
Consider claim 13. Pocock discloses an apparatus see fig. 1 microLED transmitter and receiver comprising:
a substrate fig. 9 substrate 913;
one or more integrated circuit dies mounted on the substrate fig. 9 IC 911 on substrate 913;
a light-emitting diode (LED) assembly comprising a plurality of LEDs fig. 9 MicroLEDs are below the lenses 915 [0045] MicroLEDs and or PDs mounted to the chip. fig. 10 microLEDs 1014 ;
Pocock does not disclose an integrated heat spreader (IHS) mounted on the substrate, the IHS thermally coupled to the one or more integrated circuit dies; and wherein the LED assembly is mounted on the IHS.
Daeschner however, discloses an integrated heat spreader (IHS) mounted on the substrate[0045] lead frame 20 with interconnects 25 and frame 23 generally serves as an integrated heat transferor and may connect the Led device to a PCB board (the substrate), the IHS thermally coupled to the one or more integrated circuit dies; and wherein the LED assembly is mounted on the IHS [0045] see fig. 1a-1d LED mounted on top of the frame 20 which mounted to PCB which connects to other components such as ICs.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the micro LED assembly of Pocock to include an integrated heat spreader (IHS) mounted on the substrate, the IHS thermally coupled to the one or more integrated circuit dies; and wherein the LED assembly is mounted on the IHS, as taught by Daeschner, to emit electromagnetic radiation [0007] furthermore to emit high intensity light and enabling high speed operation.
Consider claim 14. Pocock as modified by Daeschner discloses the apparatus of claim 13, further comprising:
an optical receptacle Pocock [0010] The ferrule may be, for example, a multi-fiber push on (MPO) connector or an MTP connector or, for example, a similar connector. fig. 2 fig. 6 and fig. 9 which shows the ferrule of the optical fiber bundle aligned with the microLEDs mounted on the IHS Daeschner fig. 1a-1d [0045], wherein the optical receptacle is to align an optical plug to couple light from the LED assembly Pocock [0010] The ferrule may be, for example, a multi-fiber push on (MPO) connector or an MTP connector or, for example, a similar. fig. 2 fig. 6 and fig. 9 which shows the ferrule of the optical fiber bundle aligned with the microLEDs.
Consider claim 15. Pocock as modified by Daeschner discloses the apparatus of claim 14, further comprising:
the optical plug, wherein the optical plug is mated with the optical receptacle Pocock [0010] The ferrule may be, for example, a multi-fiber push on (MPO) connector or an MTP connector or, for example, a similar connector; and
one or more optical fiber cores, wherein the one or more optical fiber cores terminate at the optical plug, wherein individual optical fiber cores of the one or more optical fiber cores are aligned to a corresponding LED of the LED assembly Pocock [0010] The ferrule may be, for example, a multi-fiber push on (MPO) connector or an MTP connector or, for example, a similar connector. fig. 2 fig. 6 and fig. 9 which shows the ferrule of the optical fiber bundle aligned with the microLEDs.
Consider claim 16. Pocock as modified by Daeschner discloses the apparatus of claim 15, further comprising one or more microlenses to couple light between the plurality of LEDs and the one or more optical fiber cores see fig. 9 lenses 915 are on top of the microLEDs and below the ferrule 921 with optical fiber bundle.
Consider claim 20 is rejected for similar reasons to claim 13.
7. Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Pocock et al. US 20240385394 in view of Daeschner et al. US 2020313057 and further in view of Jiang et al. US 20240038949.
Consider claim 17. Pocock as modified by Daeschner discloses the apparatus of claim 13, wherein a plurality of transistors are defined [0047] active layer includes transistors for microLED driver circuits but does not disclose are defined at a front end-of-line (FEOL) portion of the integrated circuit die, wherein the micro-LED assembly is mounted on a back side of the integrated circuit die, wherein a plurality of through-silicon vias are defined in the integrated circuit die, wherein the plurality of through-silicon vias connect the plurality of transistors to the micro-LED assembly.
Jiang however discloses are defined at a front end-of-line (FEOL) portion of the integrated circuit die, wherein the micro-LED assembly is mounted on a back side of the integrated circuit die, wherein a plurality of through-silicon vias are defined in the integrated circuit die, wherein the plurality of through-silicon vias connect the plurality of transistors to the micro-LED assembly [0021] FEOL devices layer include ICs fabricated by a FEOL operation. the device layer includes transistors. [0022] interconnection structure 120 connects light emitting element 132 and includes features fabricated by back end of line operation. [0026]the light emitting element includes microLED.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the micro LED assembly of Pocock as modified by Daeschner to include are defined at a front end-of-line (FEOL) portion of the integrated circuit die, wherein the micro-LED assembly is mounted on a back side of the integrated circuit die, wherein a plurality of through-silicon vias are defined in the integrated circuit die, wherein the plurality of through-silicon vias connect the plurality of transistors to the micro-LED assembly, as taught by Jiang, for improved temperature control of the light emitting package [0059].
CONCLUSION
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IBRAHIM A KHAN whose telephone number is (571)270-7998. The examiner can normally be reached on 10am-6pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nitin Patel can be reached on 571-272-7677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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IBRAHIM A. KHAN
Primary Examiner
Art Unit 2628
/IBRAHIM A KHAN/ 2/25/2026Primary Examiner, Art Unit 2628