DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 5, 6, and 8-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by USPGPub 2020/0411587 to Pezeshki et al. (hereinafter “Pezeshki”).
Regarding claim 1, Pezeshki teaches an apparatus comprising:
an integrated circuit die (Fig. 4, 419 and Paragraph 49);
a micro-light-emitting diode (micro-LED) assembly comprising one or more micro-LEDs (Fig. 4, 421 and Paragraph 34); wherein the micro-LED assembly is mounted on the integrated circuit die; and
a glass interposer (Fig. 4, 41 and Paragraph 24 and 39), wherein one or more waveguides are defined in the glass interposer, wherein the one or more waveguides terminate at the micro-LED assembly.
Regarding claim 2, Pezeshki teaches that the micro-LED assembly (Fig. 5B, 521/523) is mounted on the glass interposer, wherein the integrated circuit die (Fig. 5B, 511a) is mounted on the micro-LED assembly.
Regarding claim 5, Pezeshki one or more mirrors (Fig. 4, 425 and Paragraph 49) are defined in the glass interposer, wherein the one or more waveguides are coupled to the one or more micro-LEDs by the one or more mirrors.
Regarding claim 6, Pezeshki teaches a cavity is defined in the glass interposer (Fig. 5B, 513), wherein the micro-LED assembly (fig. 5B, 521/532a) is disposed in the cavity of the glass interposer.
Regarding claim 8, Pezeshki teaches a plurality of through-glass vias (Fig. 4, 427; Fig. 5, 517are defined in the glass interposer, wherein the plurality of through-glass vias carry input signals, output signals, and power signals to or from the integrated circuit die (see Fig. 1 for I/O and power signal, Paragraph 48).
Regarding claim 9, Pezeshki teaches the micro-LED assembly comprises a base die (Fig. 5, 523), one or more micro-LED dies (Fig. 5, 521), and one or more photodiode dies (Fig. 5, not shown, Paragraphs 51 and 37).
Regarding claim 10, Pezeshki teaches that driver circuitry for the micro-LED assembly is located on the micro-LED assembly (Paragraph 56).
Regarding claim 11, Pezeshki teaches a second integrated circuit die (see Fig. 5A-5C, 511b); and
a second micro-LED assembly, wherein the second micro-LED assembly is mounted on the second integrated circuit die, wherein the one or more waveguides are configured to carry light between the micro-LED assembly and the second micro-LED assembly (Paragraph 51).
Regarding claim 12, Pezeshki teaches a circuit board (Fig. package substrate), wherein the glass interposer is mounted on the circuit board.
Regarding claim 13, Pezeshki teaches that the one or more micro-LEDs comprise gallium and nitrogen (Paragraph 42, etc.).
Regarding claim 14, Pezeshki teaches an apparatus comprising:
an integrated circuit die (Fig. 4, 419 and Paragraph 49);
a glass interposer (Fig. 4, 41 and Paragraph 24 and 39), wherein one or more waveguides are defined in the glass interposer; and
a micro-light-emitting diode (micro-LED) assembly comprising one or more micro-LEDs (Fig. 4, 421 and Paragraph 34);
wherein the micro-LED assembly is adjacent to the integrated circuit die and the glass interposer, wherein, in use, light from the one or more micro-LEDs is coupled to the one or more waveguides (Paragraph 49).
Regarding claim 15, Pereshki teaches the micro-LED assembly (Fig. 5B, 523) is mounted on the glass interposer (Fig. 5B, 513), wherein the integrated circuit die (Fig. 5B, 511a) is mounted on the micro-LED assembly.
Regarding claim 16, Pereshki teaches a plurality of through-glass vias (Fig. 4, 427) are defined in the glass interposer, wherein the plurality of through-glass vias carry input signals, output signals, and power signals to or from the integrated circuit die (see Fig. 1 for I/O and power signal, Paragraph 48).
Regarding claim 17, Pereshki teaches driver circuitry (Paragraph 51), wherein the driver circuitry is to modulate an amplitude of the one or more micro-LEDs at a rate of at least five gigahertz (Paragraph 38, 5 Gb/s).
Regarding claim 18, Pezeshki teaches an apparatus comprising:
a glass interposer (Fig. 4, 41 and Paragraph 24 and 39), wherein one or more waveguides are defined in the glass interposer;
an integrated circuit die (Fig. 4, 419 and Paragraph 49); and
means for converting electrical signals from the integrated circuit die to optical signals (Fig. 4, 421 and/or 423; Paragraph 49), wherein the means for converting electrical signals from the integrated circuit die to optical signals is adjacent to the glass interposer and the integrated circuit die.
Regarding claim 19, Pezeshki teaches that the means for converting electrical signals (Fig. 5B, 523) is mounted on the glass interposer (Fig. 5B, 513), wherein the integrated circuit die (Fig. 5B, 511a) is mounted on the means for converting electrical signals.
Regarding claim 20, Pezeshki teaches one or more mirrors (Fig. 4, 425 and Paragraph 49) are defined in the glass interposer, wherein the one or more waveguides are coupled to the means for converting electrical signals by the one or more mirrors.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Pezeshki ‘587 in view of Pezeshki et al (U.S. Pub 2021/0080664), hereinafter Pezeshki ‘664.
Regarding claim 3, Pezeshki ‘587 does not teach that the one or more waveguides are butt coupled to the one or more micro-LEDs.
Pezeshki ‘664 teaches a microLED that is butt coupled to a waveguide (Paragraph 56, etc.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention obvious to one of ordinary skill in the art at the time the invention was effectively filed to configure the microLED of Pezeshki ‘587 to be butt coupled to the waveguide as taught by Pezeshki ‘664 in order to achieve the predictable result of optimizing the coupling (Paragraph 56).
Claim 4 rejected under 35 U.S.C. 103 as being unpatentable over Pezeshki, in view of Le Maitre et al (USPGPub 2024/0213382).
Regarding claim 4, Pezeshki does not teach that the one or more waveguides are evanescently coupled to the one or more micro-LEDs.
Le Maitre teaches a waveguide coupled to a light source by evanescent coupling (Paragraph 157). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to couple the microLED and waveguide of Pezeshki by evanescent coupling as taught by Le Maitre in order to reduce light losses (Paragraph 157).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Pezeshki, in view of Wei et al (U.S. PGPub 2022/0065407).
Regarding claim 7, Pezeshki does not teach an index-matching material disposed within the cavity.
Wei teaches a microLED coupled to a waveguide, wherein a cavity space between the elements has an index matching material disposed within (Paragraph 40-41). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an index matching material disposed in the cavity of Pezeshki as taught by Wei in order to improve the coupling (Paragraph 40-41).
Conclusion
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/LISA M CAPUTO/Primary Patent Examiner, Art Unit 2874