DETAILED ACTION
INFORMATION CONCERNING RESPONSES
Response to Amendment
This Office Action is in response to applicant’s communication filed on October 1, 2025, in response to PTO Office Action mailed on May 1, 2025. The Applicant’s remarks and amendments to the claims and/or the specification were considered with the results that follow.
In response to the last Office Action, claims 1, 15, 17, and 20 have been amended. As a result, claims 1-22 are now pending in this application.
The objections to the drawings have been withdrawn due to the amendment filed October 1, 2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Due to Applicant’s amendments for claims 15-22 filed on October 1, 2025, the rejection based on 35 USC 101 has been withdrawn.
Applicant's arguments filed on October 1, 2025, in response to PTO Office Action mailed on May 1, 2025, have been fully considered and are persuasive. Hence, the rejection has been withdrawn. However, upon further review a new ground of rejection has been made in view of Vicente (Patent Number US 8,954,562 B2).
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
Claims 1, 3-4, and 6 are rejected under 35 U.S.C. 103(a) as being unpatentable over Dharmadhikari et al. (Publication Number US 2014/0165183 A1) in view of Vicente (Patent Number US 8,954,562 B2).
As per claim 1, Dharmadhikari et al. discloses “A computing system comprising: a first input / output (IO) module (system 100 with port 140; FIG. 1).” Dharmadhikari et al. discloses “a first computer system comprising a first processor (host CPU 110; FIG. 1), a first memory (Paragraph 0018), a first operating system (Paragraph 0019), [a first baseboard management controller (BMC)], a first network controller (the presence of network 150 indicates the presence of a network controller; FIG. 1).” Dharmadhikari et al. discloses “and a management network comprising a set of network endpoints (network 150 [FIG. 1] where there are start points and end points; Paragraph 0031), [wherein the first management network is a self-configuring network].”
Dharmadhikari et al. discloses “wherein each network endpoint has a first address, wherein each network endpoint is an internal device connected to the management network (the start point and end point of paths in unicast, multicast, and broadcast traffic may be defined by IP address, or a media access control (MAC) address, or any other suitable network address; Paragraph 0031), wherein the first operating system is interfaced with the [first BMC] through a first interface supported by the [first BMC] (switch 130 determines the proper destination of each of packets 210 and 220. For example, when packet 220 contains network management information, switch 130 sends the packet to BMC 220; Paragraph 0026), [wherein the first interface is a non-network interface].”
While Dharmadhikari et al. discloses a controller (in the form of a band management controller [Abstract]), Dharmadhikari et al. does not disclose “a first baseboard management controller (BMC),” “wherein the first management network is a self-configuring network,” or “wherein the first interface is a non-network interface.”
Vicente discloses “a first baseboard management controller (BMC) (Column 9, lines 20-23).”
Vicente discloses “wherein the first management network is a self-configuring network (the logic for autonomous (emphasis) self-promotion and demotion in the network is configured to weight the node's behavior; Claim 1).”
Vicente discloses “wherein the first interface is a non-network interface (BMC 350 has one connection to a Low Pin Count bus; FIG. 3; Column 9, lines 20-35).”
Dharmadhikari et al. and Tucker are analogous art in that they in the field of network connections.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Dharmadhikari et al. and Vicente to allow for a system to be reorganized for optimal performance and efficiency [Column 1, lines 56-58] particularly in systems capable of self-organization without human dependency [Column 2, lines 44-45].
As per claim 3, Dharmadhikari et al. discloses “The system of claim 1 (as disclosed by Dharmadhikari et al. and Vicente above), wherein each first address is a media access control (MAC) address (the start point and end point of paths in unicast, multicast, and broadcast traffic may be defined by IP address, or a media access control (MAC) address, or any other suitable network address; Paragraph 0031).”
As per claim 4, Dharmadhikari et al. discloses “The system of claim 3 (as disclosed by Dharmadhikari et al. and Vicente above), wherein each endpoint has a second address derived from the first address, wherein the second address is a link local address (the start point and end point of paths in unicast, multicast, and broadcast traffic may be defined by IP address, or a media access control (MAC) address, or any other suitable network address; Paragraph 0031).”
As per claim 6, Vicente discloses “The system of claim 1 (as disclosed by Dharmadhikari et al. and Vicente above), wherein the first network controller, the first IO module, and the first BMC are each an internal device connected to the management network (Column 9, lines 20-35).”
Claims 7-9, 11, 13-15, 17, 19, and 21-22 are rejected under 35 U.S.C. 103(a) as being unpatentable over Dharmadhikari et al. (Publication Number US 2014/0165183 A1) and Vicente (Patent Number US 8,954,562 B2) in view of Tucker (Patent Number US 7,689,675 B2).
As per claim 7, Dharmadhikari et al. and Vicente discloses “The system of claim 6 (as disclosed by Dharmadhikari et al. and Vicente above).”
However, Dharmadhikari et al. and Vicente do not disclose “further comprising: a second IO module” or “and a second computer system comprising a second processor and a second memory, a second operating system, a second BMC, a second network controller, wherein the first computer system and the second computer system are linked by a sideband communication channel, wherein the sideband communication channel supports the first computer system and the second computer system exchanging one or more addresses.”
Tucker discloses “further comprising: a second IO module (second console server [FIG. 24; Column 8, lines 56-67] along with second application and second operating system; Claim 1).” Tucker discloses “and a second computer system comprising a second processor and a second memory, a second operating system, a second BMC (BMC is disclosed by Dharmadhikari et al. in [FIG. 1] while Tucker is directed to the presence of a second module; FIG. 24; Column 8, lines 56-67; Claim 1), a second network controller, wherein the first computer system and the second computer system are linked by a sideband communication channel, wherein the sideband communication channel supports the first computer system and the second computer system exchanging one or more addresses (out-of-band access to devices [Claim 1]. Tucker is also directed to the presence of a second module; FIG. 24; Column 8, lines 56-67; Claim 1).”
Dharmadhikari et al. and Tucker are analogous art in that they in the field of network connections.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Dharmadhikari et al. and Vicente with elements of Tucker in order to control a variety of devices through a console server [Column 1, lines 53-54].
As per claim 8, Tucker discloses “The system of claim 7 (as disclosed by Dharmadhikari et al., Vicente, and Tucker above), wherein the second Ethernet controller, the second IO module, and the second BMC are each an internal device connected to the management network (second console server [FIG. 24; Column 8, lines 56-67] along with second application and second operating system; Claim 1).” As per claim 9, Dharmadhikari et al. discloses “The system of claim 8 (as disclosed by Dharmadhikari et al., Vicente, and Tucker above), wherein each first address is a media access control (MAC) address (Paragraph 0032).”
As per claim 11, Vicente discloses “The system of claim 7 (as disclosed by Dharmadhikari et al., Vicente, and Tucker above), wherein the first operating system is interfaced with the first BMC through a first interface supported by the first BMC (BMC 350 has one connection to a Low Pin Count bus; FIG. 3; Column 9, lines 20-35).”
Tucker discloses “wherein the second operating system is interfaced with the second BMC through a second interface supported by the second BMC (Tucker is directed to the presence of a second module; FIG. 24; Column 8, lines 56-67; Claim 1).”
As per claim 13, Tucker discloses “The system of claim 7 (as disclosed by Dharmadhikari et al., Vicente, and Tucker above), wherein the one or more addresses is an address of the first computer system, the second computer system, or address of both the first computer system and the second computer system (see IP Address Per Port setting controls; Column 4, lines 37-48).”
As per claim 14, Tucker discloses “The system of claim 7 (as disclosed by Dharmadhikari et al., Vicente, and Tucker above), wherein the first operating system comprises a management virtual machine and a virtual switch, wherein the second operating system comprises a teaming interface, the teaming interface interfacing with one or more teamed connections and one or more non- teamed connections (see the use of virtual serial port; Column 2, lines 37-46).”
As per claim 15, Dharmadhikari et al. discloses “A method of allocating addresses in a self-configuring management network, the method comprising: connecting a plurality of endpoints [of the self-configuring management network] (network 150 [FIG. 1] where there are start points and end points; Paragraph 0031).”
Dharmadhikari et al. discloses “exchanging a first address between a first endpoint of the plurality of endpoints and a second endpoint of the plurality of endpoints (the start point and end point of paths in unicast, multicast, and broadcast traffic may be defined by IP address, or a media access control (MAC) address, or any other suitable network address; Paragraph 0031).”
However, Dharmadhikari et al. does not disclose “of the self-configuring management network.”
Vicente discloses “of the self-configuring management network (the logic for autonomous (emphasis) self-promotion and demotion in the network is configured to weight the node's behavior; Claim 1).”
Dharmadhikari et al. and Tucker are analogous art in that they in the field of network connections.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Dharmadhikari et al. and Vicente to allow for a system to be reorganized for optimal performance and efficiency [Column 1, lines 56-58] particularly in systems capable of self-organization without human dependency [Column 2, lines 44-45].
However, Dharmadhikari et al. and Vicente do not disclose “determining a second address, the second address derivable from the first address, the second address associated with a first computer system” or “and transmitting the second address to a second computer system using a sideband communication channel such that the second computer system can communicate with one or more devices of the first computer system.” Tucker discloses “determining a second address, the second address derivable from the first address, the second address associated with a first computer system (second console server [FIG. 24; Column 8, lines 56-67] along with second application and second operating system; Claim 1).” Tucker discloses “and transmitting the second address to a second computer system using a sideband communication channel such that the second computer system can communicate with one or more devices of the first computer system (out-of-band access to devices [Claim 1]. Tucker is also directed to the presence of a second module; FIG. 24; Column 8, lines 56-67; Claim 1).”
Dharmadhikari et al. and Tucker are analogous art in that they in the field of network connections.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Dharmadhikari et al. and Vicente with elements of Tucker in order to control a variety of devices through a console server [Column 1, lines 53-54].
As per claim 17, Dharmadhikari et al. discloses “The method of claim 15 (as disclosed by Dharmadhikari et al., Vicente, and Tucker above), wherein the step of determining the second address comprises querying [a BMC using a non-network interface] to obtain the first address and thereby deriving the second address (the start point and end point of paths in unicast, multicast, and broadcast traffic may be defined by IP address, or a media access control (MAC) address, or any other suitable network address; Paragraph 0031).”
Vicente discloses “a BMC using a non-network interface (BMC 350 has one connection to a Low Pin Count bus; FIG. 3; Column 9, lines 20-35).”
As per claim 19, Tucker discloses “The method of claim 15 (as disclosed by Dharmadhikari et al., Vicente, and Tucker above), wherein determining the second address comprises accessing one or more scratchpad registers of one or more PCI switches (through the use information stored in memory circuit; Column 8, lines 25-56) and further comprising populating one or more scratchpad registers to exchange the first address for each endpoint of the plurality of endpoints using the sideband communication channel (out-of-band access to devices [Claim 1]. Tucker is also directed to the presence of a second module; FIG. 24; Column 8, lines 56-67; Claim 1).”
As per claim 21, Dharmadhikari et al. discloses “The method of claim 15 (as disclosed by Dharmadhikari et al., Vicente, and Tucker above) wherein configuring the plurality of endpoints is performed automatically without user configuration of any first addresses or second addresses (the start point and end point of paths in unicast, multicast, and broadcast traffic may be defined by IP address, or a media access control (MAC) address, or any other suitable network address; Paragraph 0031).”
As per claim 22, Dharmadhikari et al. discloses “The method of claim 15 (as disclosed by Dharmadhikari et al., Vicente, and Tucker above), wherein the sideband communication channel is a Peripheral Component Interconnect-based communication channel (Paragraph 0005).”
Claims 2, 5, 10, 12, 18, and 20 are rejected under 35 U.S.C. 103(a) as being unpatentable over Dharmadhikari et al. (Publication Number US 2014/0165183 A1), Vicente (Patent Number US 8,954,562 B2), and Tucker (Patent Number US 7,689,675 B2) in view of Su (Publication Number US 2021/0004242 A1).
As per claim 2, Dharmadhikari et al., Vicente, and Tucker disclose “The system of claim 1 (as disclosed by Dharmadhikari et al., Vicente, and Tucker above).” However, Dharmadhikari et al., Vicente, and Tucker do not disclose “wherein the first interface supported by the first BMC is a keyboard controller style (KCS) or Inter-Integrated Circuit (I2C) based Intelligent Platform Management Interface (IPMI), wherein each first address is a defined address.”
Su discloses “wherein the first interface supported by the first BMC is a keyboard controller style (KCS) or Inter-Integrated Circuit (I2C) based Intelligent Platform Management Interface (IPMI), wherein each first address is a defined address (Paragraph 0025).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Dharmadhikari et al., Vicente, and Tucker with elements of Su in order to in order to support a variety of microcontrollers [Paragraph 0025].
As per claim 5, Dharmadhikari et al., Vicente, and Tucker disclose “The system of claim 1 (as disclosed by Dharmadhikari et al., Vicente, and Tucker above).” However, Dharmadhikari et al., Vicente, and Tucker do not disclose “wherein each first address is a IPv6 link-local address (Paragraph 0007).”
Su discloses “wherein each first address is a IPv6 link-local address (Paragraph 0007).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Dharmadhikari et al., Vicente, and Tucker with elements of Su in order to in order to support a variety of microcontrollers [Paragraph 0025].
As per claim 10, Dharmadhikari et al., Vicente, and Tucker disclose “The system of claim 8 (as disclosed by Dharmadhikari et al., Vicente, and Tucker above).” However, Dharmadhikari et al., Vicente, and Tucker do not disclose “wherein each first address is a IPv6 link-local address.”
Su discloses “wherein each first address is a IPv6 link-local address (Paragraph 0007).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Dharmadhikari et al., Vicente, and Tucker with elements of Su in order to in order to support a variety of microcontrollers [Paragraph 0025].
As per claim 12, Dharmadhikari et al., Vicente, and Tucker disclose “The system of claim 11 (as disclosed by Dharmadhikari et al., Vicente, and Tucker above).” However, Dharmadhikari et al., Vicente, and Tucker do not disclose “wherein the first interface and the second interface are both KSC or I2C based IPMI interfaces.”
Su discloses “wherein the first interface and the second interface are both KSC or I2C based IPMI interfaces (Paragraph 0025).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Dharmadhikari et al., Vicente, and Tucker with elements of Su in order to in order to support a variety of microcontrollers [Paragraph 0025].
As per claim 16, Dharmadhikari et al. discloses “The method of claim 15 (as disclosed by Dharmadhikari et al., Vicente, and Tucker above), wherein the first address is a MAC address (the start point and end point of paths in unicast, multicast, and broadcast traffic may be defined by IP address, or a media access control (MAC) address, or any other suitable network address; Paragraph 0031).” However, Dharmadhikari et al., Vicente, and Tucker do not disclose “and the second address is a IPv6 link-local address.”
Su discloses “and the second address is a IPv6 link-local address (Paragraph 0007).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Dharmadhikari et al., Vicente, and Tucker with elements of Su in order to in order to support a variety of microcontrollers [Paragraph 0025].
As per claim 18, Dharmadhikari et al., Vicente, and Tucker discloses “The method of claim 17 (as disclosed by Dharmadhikari et al., Vicente, and Tucker above).” However, Dharmadhikari et al., Vicente, and Tucker do not disclose “wherein the BMC is queried by an operating system using a KCS or I2C based IPMI interface, the operating system running on one of the end points.”
Su discloses “wherein the BMC is queried by an operating system using a KCS or I2C based IPMI interface, the operating system running on one of the end points (Paragraph 0025).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Dharmadhikari et al., Vicente, and Tucker with elements of Su in order to in order to support a variety of microcontrollers [Paragraph 0025].
As per claim 20, Dharmadhikari et al. discloses “The method of claim 15 (as disclosed by Dharmadhikari et al., Vicente, and Tucker above).”
Dharmadhikari et al. discloses “and deriving a second address from each first address, wherein the first address is a MAC address (the start point and end point of paths in unicast, multicast, and broadcast traffic may be defined by IP address, or a media access control (MAC) address, or any other suitable network address; Paragraph 0031).”
Vicente discloses “further comprising configuring a fault tolerant computer using the self-configuring management network (the logic for autonomous (emphasis) self-promotion and demotion in the network is configured to weight the node's behavior; Claim 1).”
However, Dharmadhikari et al., Vicente, and Tucker do not disclose “and the second address is a IPv6 link-local address.”
Su discloses “and the second address is a IPv6 link-local address (Paragraph 0007).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Dharmadhikari et al., Vicente, and Tucker with elements of Su in order to in order to support a variety of microcontrollers [Paragraph 0025].
RELEVENT ART CITED BY THE EXAMINER
The following prior art made of record and relied upon is citied to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
The following references teach data transfer as they pertain to network connections:
U.S. PATENT NUMBERS:
2019/0028345 A1 – [Paragraph 0085]
2023/0313302 A1 – [Paragraph 0171]
CONCLUDING REMARKS
Conclusions
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/H.W.Y/Examiner, Art Unit 2181 December 3, 2025
/IDRISS N ALROBAYE/Supervisory Patent Examiner, Art Unit 2181