Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Other references: Pathirane (20110179255) – data protection controlling access for memory protection.
Claim Rejections – 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-10 ,12-14, and 16-20 are rejected under 35 U.S.C 103 as being unpatentable over Grocutt, (US 20210311884 A1) in view of Moyer, et. al ( US 20120215989 A1 ) and further in view of Koeberl (US 20150032996)
Regarding claim 1; Grocutt (US 20210311884 A1) teaches; A processor system, comprising: ( [0002] A data processing apparatus )
a first memory comprising a memory protection table including ( [0101] . . . The
processing circuitry 4 may include an instruction fetch unit 5 for fetching instructions from memory system 10 for processing by the processing circuitry and [0103] . . . A memory protection table 22 may be stored within the memory system, comprising a number of entries each defining access permissions for a corresponding address region.)
memory access permission information associated with a set of one or more worlds; ( [0157] . . . a memory management unit (MMU) 334 supporting address translation and memory access permission checking based on hierarchical page tables stored in memory, and a memory system and [0002] It may be desirable to define access permissions which control whether certain software processes are allowed to access certain regions of an address space and [0035] For example, a piece of software may require a greater number of distinct address regions to be defined with different access permissions than is supported in hardware in the number of protection entries supported by the MPU. In this case, at any given time at least some parts of the address space required to be accessed by that software will not currently have a corresponding memory protection entry defined for it. This would mean that an access to an address in a currently undefined region of the address space would trigger an exception which would then require software to step in and reconfigure the registers of the MPU, so as to overwrite the parameters previously defined for a different region with the parameters required for the region needed to be accessed now. If a later instruction then accesses the previously defined region which has been overwritten, this may then cause the MPU configuration to be switched back again. This constant switching of the contents of the MPU registers, needing an exception to trigger the switching each time, may greatly harm performance. Where “a software process” or “a piece of software is analogous to “world” or thread or workload or application that executes in a system with memory protection)
and a processor comprising: ( [0036] Another example can be where the processor needs to execute multiple pieces of software which are mutually distrustful, but which need to share data between them. Where a processor executes multiple “pieces of software” or multiple “worlds” or threads or workloads or applications. And [0004] processing circuitry to issue memory access requests specifying a target address identifying a location to be accessed in a memory system; and [0101] FIG. 1 schematically illustrates a data processing system 2 having processing circuitry 4 for performing data processing in response to instructions. For example the processing circuitry 4 may be a CPU, DSP, GPU or other processing element of a data processing system. The processing circuitry 4 may include an instruction fetch unit 5 for fetching instructions from memory system 10. Where “processing circuitry 4” may be a CPU which is a processor)
an execution core configured to run a first world; ([0045] The MPU may have static MPU register storage for storing at least one static memory protection entry. The at least one static memory protection entry may provide further definitions of address regions with specified access permissions, to supplement the permissions defined in the memory protection entries of the memory protection table which is stored in the memory system. Providing some configuration options to provide additional MPU regions defined in static register storage can be useful to keep interrupt latencies low and provide deterministic interrupt behaviour. And [0049] . . . Hence, a hit in the static MPU register storage when the request is allowed overrides any permissions set in the memory-based memory protection entries, but a hit in the static MPU register storage when the request is not allowed by the static entry can be overridden by other access permissions specified in a matching memory protection entry of the memory protection table. This approach can be useful to reduce the total number of regions which need to be defined to allow a first software process access to a specific sub-region of an address region accessed by a second software process Where the “memory protection table” is configured to allow a first software process to access a specific address region of memory, where “first software process” is analogous to “first world”.)
and a table-based memory protection (TMP) configured to: receive a first request to access memory content at a first target address from the first world; ( [0006] permission checking circuitry to check whether a memory access request issued by the processing circuitry satisfies access permissions specified in a memory protection table stored in the memory system, the memory protection table comprising a plurality of memory protection entries, each memory protection entry specifying: access permissions for a corresponding address region of variable size within an address space, and region identifying parameters for identifying a start address and an end address of the corresponding address region, wherein said MPU is configured to permit said variable size to be a number of bytes other than a power of 2; Where a memory protection table contains address regions within an address space. And a memory access request is issued to the permission checking circuitry to verify memory access permission. And [0007] MPU memory access circuitry to initiate at least one MPU memory access request for accessing the memory protection table from said memory system. And [0049] . . . Hence, a hit in the static MPU register storage when the request is allowed overrides any permissions set in the memory-based memory protection entries, but a hit in the static MPU register storage when the request is not allowed by the static entry can be overridden by other access permissions specified in a matching memory protection entry of the memory protection table. This approach can be useful to reduce the total number of regions which need to be defined to allow a first software process access to a specific sub-region of an address region Where the “first software process” is analogous to “first world” and its execution is generating “memory access requests” to the “memory protection table”. And a “specific sub region of an address region” is a “target address”)
access the memory access permission information from the memory protection table based on the first target address; ( [0006] permission checking circuitry to check whether a memory access request issued by the processing circuitry satisfies access permissions specified in a memory protection table stored in the memory system, the memory protection table comprising a plurality of memory protection entries, each memory protection entry specifying: access permissions for a corresponding address region of variable size within an address space, and region identifying parameters for identifying a start address and an end address of the corresponding address region,)
and determine whether the first world is allowed to access the memory content at the first target address based on the accessed memory access permission information. ( [0103] A memory protection unit (MPU) 20 is provided for checking based on the target address whether the memory access request is permitted to be serviced by the memory system 10. Access permissions for controlling whether the processing circuitry 4 is allowed to access a given address region may be defined in two ways. A memory protection table 22 may be stored within the memory system, comprising a number of entries each defining access permissions for a corresponding address region. The MPU 20 has MPU memory access circuitry 24 for initiating memory access requests to the memory system 10 in order to obtain information from the MPU table 22. The MPU memory access circuitry 24 has table lookup circuitry 26 for performing the comparisons needed to identify whether the MPU table 22 includes an entry for an address region comprising the target address specified by the memory access request received from the processing circuitry 4. The memory system 10 may store more than one MPU table, each table 22 associated with a respective software process. Where “software process” is analogous to “first world” and the memory access permission is determined by the processing circuitry 4 for a given address region.)
However Grocutt does not expressly disclose “a first memory comprising a memory protection table” or “an execution core” but these limitations are address by Moyer, et. al ( US 20120215989 A1 ) ( [0029] Data processing system 100 includes a first processor core 10 identified as CPU 0, a second processor core 12 identified as CPU N, an interconnect 20, a global MPU 30, a memory device 40, and a slave device 42. And [0012] FIG. 8 is a table illustrating permission information stored at a cache memory in accordance with a specific embodiment of the present disclosure. And [0064] The operation of the cache permission information flags can be better understood with reference to FIG. 8. FIG. 8 is a table 800 illustrating permission information stored in a cache memory in accordance with a specific embodiment of the present disclosure. The table 800 includes columns 801, 802, 803, and 804, and rows 810, 811, 812, 813, 814, and 815. The columns 801-803 represent the three permission information flags included in a cache line, such as a cache line of data cache 51 in the data processing system 100 of FIG. 1. And [0065] . . . During operation of data processing system 100 of FIG. 1, if an address associated with a memory access request is determined to be present and valid in a cache memory, the access can be allowed or the request can be denied based in part on the permission information flags associated with the cache line containing the requested information. Where a “table illustrating permission information” is analogous to a “memory protection table”. And the table is store in “cache memory” which is a “first memory”. And first and second processor cores, 10 and 12 are analogous to “execution core”. ).
locally store; wherein the locally stored (eg., 0025 - permission information maintained in a local MPU included at the processor core.; 0029 - local MPU 60 Fig. 1)
wherein the locally stored memory access permission information includes an indication of at least one of read access permission, write access permission, or associated with the memory content at the first target address (eg., 0064- FIG. 8 is a table 800 illustrating permission information stored in a cache memory; 0065 - 0066- rows 810-815 illustrate permissible combinations of the flags, and the column 804 provides a description of allowed accesses; 0067 - A cache line having this particular combination of flags can be both read and written by a supervisor level request, but cannot be read or written by a user level request).
Grocutt and Moyer are analogous art because they are from the same field of endeavor of memory for data protection using memory protection tables.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify Grocutt to include “disclose “a first memory comprising a memory protection table” or “an execution core”. Modifying Grocutt as taught by Moyer would provide the benefits memory protection to ( [0003] Data processing systems often include one or more memory protection units (MPUs) to regulate access to memory devices. A MPU can intercept memory access requests issued by a device and determine whether the requesting device has requisite authority to access the memory. A MPU can be configured to grant or deny access to individual address regions by associating each region with corresponding access privileges using descriptors. In systems with multiple processor cores, each processor core can have its own local MPU that controls memory accesses initiated by that core using one or more local descriptors. In addition, a global MPU may grant or deny accesses initiated by each of the multiple processor cores, and other bus masters, using one or more global descriptors ) See Moyer ([0029], [0012] [0064] & [0065]. )
Grocutt and Moyer do not disclose, but Koeberl discloses
execute access permission (eg., 0042 Fig. 2A - region's base address 203 and region's length 205 and access permissions 207 (e.g., read, write, or execute). The region base address 203, region length 205 and region permissions 207 can be stored in a set of one or more registers)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify Grocutt and Moyer, with Koeberl, providing the benefit of execution-aware memory protection architectures (see Koeberl, 0001) enforces memory access control by organizing real, physical memory into a number of memory regions with associated access permissions. MPUs can be used for reliability, providing a mechanism to detect errors ranging from programming bugs to hardware failures. MPUs can also have security applications (0025).
Regarding claim 2, Grocutt teaches; wherein the TMP is configured to pass the first memory access request to the first memory or a second memory in response to the TMP determining that the first world is allowed to access the memory content at the first target address. ( [0004] processing circuitry to issue memory access requests specifying a target address identifying a location to be accessed in a memory system; Where the processing circuit issues a memory access request specifying a target address . And [0006] permission checking circuitry to check whether a memory access request issued by the processing circuitry satisfies access permissions specified in a memory protection table stored in the memory system. Where “permission checking circuitry” checks permission in the “memory protection table, which is analogous to TMP. And [0007] MPU memory access circuitry to initiate at least one MPU memory access request for accessing the memory protection table from said memory system. Where the circuitry initiates (sends) the memory access request to memory)
Regarding claim 3, Grocutt teaches; wherein the processor system comprises a cache, and wherein the memory content at the first target address is copied into the cache. ( [0054] In response to the memory access request issued by the processing circuitry, the MPU memory access circuitry may determine whether to initiate the at least one MPU memory access request depending on whether the target address is within the corresponding address region specified for any memory protection entry stored in the MPU cache. And [0103] . . . MPU cache storage 32 is provided within the MPU for caching selected entries of the MPU table(s) from the memory system 10. Where the MPU is a type of “processor system” and has a cache, 32, and the target address may be stored in the MPU cache.
Regarding claim 4, Grocutt teaches; wherein: the execution core is further configured to run a second world; and the TMP is configured to: receive a second request to access the memory content at the first target address from the second world; and determine whether the second world is allowed to access the memory content at the first target address based on the accessed memory access permission information. ( [0062] . . . Alternatively, in some cases the table may be identified using a combination of a base address and a size. This could be useful if the memory protection tables to be accessed by two different software processes partially overlap, so that the shared part of the memory protection table could be stored at addresses starting at the base address and then the part of the memory protection table only to be used for one particular software process could be located at a subsequent portion of 3553the address space, so that switching between the different memory protection tables accessed by the different pieces of software can be carried out simply by changing the size indication to indicate how large the active memory protection table is. Where “two different software processes” is analogous to a “first world” and a “second world”. And where “memory protection tables” are analogous to TMP. And where address space may be shared by “shared part of the memory protection table”.
However, Grocutt does not expressly disclose “execution core”, but these limitations are addressed by limitations are address by Moyer ( [0029] Data processing system 100 includes a first processor core 10 identified as CPU 0, a second processor core 12 identified as CPU N, an interconnect 20, a global MPU 30, a memory device 40, and a slave device 42. Where core 10 and core 12 are analgous to “execution core” and having a first and second core 10 and 12 would permit a first and second world or software to execute on them.).
Grocutt and Moyer are analogous art because they are from the same field of endeavor of memory for data protection using memory protection tables.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify Grocutt to include “an execution core”) See Moyer ([0029])
Regarding claim 5, Grocutt teaches; wherein the TMP is configured to pass the second memory access request to the cache for accessing the memory content by the second world in response to determining that the second world is allowed to access the memory content at the first target address. ( [0049] Alternatively, for memory access requests which hit in the static memory protection entry but fail the access permissions in that static memory protection entry, the access permissions may be permitted to be overridden by access permissions specified by a matching memory protection entry within the memory protection table stored in the memory system (the matching memory protection entry comprising an entry for which the corresponding address region includes the target address). Hence, a hit in the static MPU register storage when the request is allowed overrides any permissions set in the memory-based memory protection entries, but a hit in the static MPU register storage when the request is not allowed by the static entry can be overridden by other access permissions specified in a matching memory protection entry of the memory protection table. This approach can be useful to reduce the total number of regions which need to be defined to allow a first software process access to a specific sub-region of an address region accessed by a second software process. For example, the static MPU entry could be set for the wider address region to permit the second software process to access that region but deny the first software process access. A memory-based memory protection entry covering a smaller address region within the wider region could then be specified only for the subrange which is allowed to be accessed by the first software. This can avoid the need for providing separate entries for the parts of the wider range either side of the subrange accessed by the first software, preserving other static memory protection entries for other purposes or enabling a reduction in the total size of the memory protection table.. Where a “second software process” is analogous to a “second world”. And the MPU / “memory protection table” permits a second software process to access a memory region. And [0050] Each static memory protection entry may be associated with an unused indication indicative of whether the static memory protection entry is an unused static memory protection entry. When a given static memory protection entry is indicated as an unused static memory protection entry, the MPU may cache a memory protection entry from the memory protection table in a portion of the static MPU register storage which corresponds to the given static memory protection entry. Hence, when software does not need as many static memory protection entries as are supported in hardware, then a portion of the hardware register storage can be reused as a cache to enable local storage of a memory protection entry from the memory protection table, so that entry can be accessed faster than if it had to be fetched from the memory system. This can improve performance. When the given static memory protection entry is marked as unused, then which particular memory protection entry is cached in the static MPU register storage can vary from time to time dependent on the cache replacement policy even if the processing circuitry has not performed any MPU parameter configuration operations. Where the “memory protection entry” may be stored in cache to permit memory access )
Regarding claim 6; Grocutt teaches; wherein the TMP is configured to deny the second memory access request in response to determining that the second world is not allowed to access the memory content at the first target address. ([0042] . . . If it is subsequently determined that the permissions are not satisfied then data returned by the access to memory would not be forwarded to the processing circuitry. Where when permissions are not statisfied, the data is not forwarded to the processing circuitry which is to deny a memory access. And [0044] For each memory protection entry, the MPU may permit the start address and the end address of the corresponding address region And [0049] . . . For example, the static MPU entry could be set for the wider address region to permit the second software process to access that region but deny the first software process access. Where each memory protection entry may permit (or deny) a start and end address. And a software process, or first world, may be denied access to an address region.)
Regarding claim 7; Grocutt teaches; wherein the TMP is further configured to: access memory access permission information from the memory protection table based on the second request; and determine whether the second world is allowed to access the memory content at the first target address based on the accessed memory access permission information associated with the second request. ( [0147] To address this issue, at the time of the exception, in addition to recording the address of the space reserved on the stack for the floating point registers, the exception handling logic associated with the processing circuitry 4 may also record MPU checking information for enabling hardware during execution of the second software process to verify whether the address of the reserved space on the stack satisfies access permissions defined in a corresponding entry of the MPU table 22 which was used during execution of the first software. Where the second software process is analogous to a second world, and there is a verification process to verify permissions defined in the MPU entry which is analogous to TMP)
Regarding claim 8, Grocutt teaches; wherein the TMP is configured to pass the second memory access request to the cache for accessing the memory content by the second world in response to determining that the second world is allowed to access the memory content at the first target address. ( [0052] The MPU may comprise MPU cache storage to cache at least one memory protection entry of the memory protection table. And [0053] Hence, MPU cache storage is provided to cache at least one memory protection entry of the memory protection table. The MPU memory access circuitry may use a cache replacement policy (e.g. least recently used, round robin, etc.) to determine which set of memory protection entries from the memory protection table are cached in the MPU cache storage at a given time. This means the MPU cache storage can be updated even if the processing circuitry has not executed any MPU parameter configuration operation, Where a memory protection entry can be cached for use. And [0090] In some implementations the apparatus may have entry storage to store at least one entry. The entry storage could be an entry cache to cache at least one entry of the control table previously obtained from the memory system, and/or static register storage to store at least one further entry configurable by a static entry parameter configuration operation (where each further entry specifies control information for a corresponding address region of variable size within the address space for which limits are identified by a first limit address and one of a second limit address and size). Where a second limit address could be for a second memory access request. )
Regarding claim 9, Grocutt teaches; wherein the TMP is configured to deny the second memory access request in response to determining that the second world is not allowed to access the memory content at the first target address.( [0146] However, when an address is reserved for saving the floating point registers, this may be an address in the stack data structure accessible to the first software process which was executing before the exception happened. By the time that the floating registers are actually saved to the reserved space in the stack the permission checking circuitry 40 of the MPU 20 may need to check whether the memory access to save the floating point state to the reserve space in the stack is permitted, however as the active table identifier register 28 may have been reconfigured for use by the second software process, the MPU 20 may no longer have access to the MPU table which was used by the first software which defines whether the first software is allowed to save state to that region on the stack. Where the second software process is a second world, and where the second software process not having access to the MPU table is to deny the second world access to a request. And [0129] On the other hand, if at step 138 the table lookup circuitry 26 determines that there is a miss in the memory based MPU table 22 for the target address, then no address region corresponds to the target address is currently defined in the memory protection table and so a miss is signalled. In response to a miss in the memory protection table, different options are available for handling the memory access request. In some cases the request could simply be rejected and a fault could be signalled. Alternatively a set of default attributes could be defined which are intended to handle any memory access request which does not have a specific memory protection entry defined in either the static MPU register storage 36 or the memory pro;oltection table 22 in memory. Hence, in the event of a miss in the memory protection table 22, the memory access request could be checked against the default attributes and then whether or not the memory access request is permitted or rejected by the MPU 20 could be determined by the default attributes. Where a memory access request may be permitted or rejected (denied) based upon the configuration of the memory protection table MPU 22.).
Regarding claim 10, Grocutt teaches; wherein the TMP is configured to deny the first memory access request in response to determining that the first world is not allowed to access the memory content at the first target address. ( [0044] For each memory protection entry, the MPU may permit the start address and the end address of the corresponding address region And [0049] . . . For example, the static MPU entry could be set for the wider address region to permit the second software process to access that region but deny the first software process access. Where each memory protection entry may permit (or deny) a start and end address. And a software process, or first world, may be denied access to an address region.).
Regarding claim 12, Grocutt teaches; wherein the processor further comprises a physical memory protection (PMP) . ( [0042] Each memory protection entry corresponds to a given address region of the address space. In some implementations the address space may be a physical address space. Hence, the memory protection table may be queried based on physical addresses specified by the memory access request issued by the processing circuitry, where the physical addresses directly correspond to corresponding locations accessed in the memory system. This may be suitable for real time applications as by avoiding address translation this can make access to memory faster as it may be possible to perform access to memory in parallel with the access to memory protection table. If it is subsequently determined that the permissions are not satisfied then data returned by the access to memory would not be forwarded to the processing circuitry. Where a physical address space may be implemented to determine if memory accesses are permitted, which is analogous to having a physical memory protection)
configured to: be programmed to include memory access permission information for the first world with respect to a first memory address range; ( [0002] A data processing apparatus may have processing circuitry for performing data processing operations. The processing circuitry may issue memory access requests specifying a target address identifying a location to be accessed in a memory system. It may be desirable to define access permissions which control whether certain software processes are allowed to access certain regions of an address space Where a software process is analogous to first world and cessing a certain region of address space is a first memory address range.)
receive a second request to access memory content at a second target address within the first memory address range from the first world; ( [0049] . . . A memory-based memory protection entry covering a smaller address region within the wider region could then be specified only for the subrange which is allowed to be accessed by the first software. This can avoid the need for providing separate entries for the parts of the wider range either side of the subrange accessed by the first software, preserving other static memory protection entries for other purposes or enabling a reduction in the total size of the memory protection table Where a subrange may be accessed by the first software. Where a subrange is analogous to a second target address. )
and determine whether the first world is allowed to access the memory content at the second target address based on the programmed memory access permission information. ( [0049] . . . This approach can be useful to reduce the total number of regions which need to be defined to allow a first software process access to a specific sub-region of an address region accessed by a second software process Where allowing a first software access to a sub region is analogous to determining whether the first world is allowed access to memory of the second targeted address )
Regarding claim 13, Grocutt teaches; further comprising: a processing entity; ( [0103] A memory protection unit (MPU) 20 is provided for checking based on the target address whether the memory access request is permitted to be serviced by the memory system 10. Access permissions for controlling whether the processing circuitry 4 is allowed to access a given address region may be defined in two ways. Where processing circuitry 4 is a processing entity)
and an input/output table-based memory protection (IOTMP) configured to: receive a second request to access memory content at a second target address from the processing entity; ( [ 0103] . . . A memory protection table 22 may be stored within the memory system, comprising a number of entries each defining access permissions for a corresponding address region. The MPU 20 has MPU memory access circuitry 24 for initiating memory access requests to the memory system 10 in order to obtain information from the MPU table 22. The MPU memory access circuitry 24 has table lookup circuitry 26 for performing the comparisons needed to identify whether the MPU table 22 includes an entry for an address region comprising the target address specified by the memory access request received from the processing circuitry 4. Where a memory protection table 22 is analogous to an input/output table based memory protection (IOTMP) and memory access requests are received from the processing circuitry 4)
access memory access permission information from the memory protection table based on the second target address; and determine whether the processing entity is allowed to access the memory content at the second target address based on the accessed memory access information associated with the second target address. ()
( [0139] At step 174 the lookup circuitry 26 determines whether the query address is within the limits defined for the corresponding address region for the single remaining candidate entry. Hence, if the second limit is specified through an address then the lookup circuitry determines whether the query address lies between the first and second limit addresses (whether or not the first and second limit addresses are considered part of the corresponding address region or whether one of these addresses may be considered outside the corresponding address region may be an implementation-independent choice). On the other hand, if a size is used to define the second limit then the lookup circuitry may add or subtract the size to or from the first limit address to determine the second limit address and then again determine whether the query address lies between the first and second limits. If the query address is within the limits defined for the region corresponding to the single remaining entry, then at step 176 a hit is detected in the memory protection table. The attributes specified in the single remaining entry can then be returned and used to control a given operation performed by a processing component. For example for the MPU example shown above the operation performed using the hit entry may be the checking of the access permissions at step 132 of FIG. 6. Where second limit address and second target address are analogous and the lookup circuitry is determining if the request is within the first and second targeted addresses and the access permissions for within the address limits are checked. )
Regarding claim 14, Grocutt teaches; wherein the processing entity comprises a debug unit. ( [0046] . . . The MPU parameter configuration operation may also be an operation performed by the processing circuitry as requested by a debugger or other entity external to the processing circuitry. Where the a debugger is a debug unit. )
Regarding claim 16, Grocutt teaches; wherein the IOTMP is configured to pass the second memory access request to the first memory or a second memory in response to the IOTMP determining that the processing entity is allowed to access the memory content at the second target address. ( [0103] A memory protection unit (MPU) 20 is provided for checking based on the target address whether the memory access request is permitted to be serviced by the memory system 10. Access permissions for controlling whether the processing circuitry 4 is allowed to access a given address region may be defined in two ways. A memory protection table 22 may be stored within the memory system, comprising a number of entries each defining access permissions for a corresponding address region. Where a memory protection table 22 is analogous to an IOTMP. And checking, based upon a targeted address, whether a memory access request is permitted is analogous to determining that the processing entity is allowed to access at the second targeted address.)
Regarding claim 17, Grocutt teaches; wherein the IOTMP is configured to deny the second memory access request in response to determining that the processing entity is not allowed to access the memory content at the second target address. ( [0091] Where at least one control table entry is stored in the entry storage, then the table lookup circuitry may check whether the query address corresponds to at least one entry stored in the entry storage and determine whether to perform the binary search procedure depending on whether the query address corresponds to any entry stored in the entry storage. . . . the search of the table within memory may only be required if the parameters for the matching statically configured entry indicate that the memory access is not permitted, but the binary search procedure may be omitted when there is a hit in a statically configured entry which indicates that the memory access is permitted) Where table lookup circuitry is checking a query address is analogous to the IOTMP configured to determine if processing is allowed, And where indicating a memory access is not permitted is denying a memory access request. )
Regarding claim 18, Grocutt teaches; further comprising:
a bus; ( [0097] . . . this means that memory access requests specifying a narrower target portion of data can be used which may permit more efficient memory bandwidth usage because this could preserve space in buffers within the memory system or preserve wires on a bus unused for the memory access request, which could then be reused for other memory accesses, improving the overall efficiency of the memory system. )
a processing entity; ( [0018] FIG. 1 schematically illustrates an example of a data processing apparatus having an MPU; )
a second memory;
and an input/output table-based memory protection (IOTMP) configured to: ([ 0103] . . . A memory protection table 22 may be stored within the memory system, comprising a number of entries each defining access permissions for a corresponding address region. The MPU 20 has MPU memory access circuitry 24 for initiating memory access requests to the memory system 10 in order to obtain information from the MPU table 22. The MPU memory access circuitry 24 has table lookup circuitry 26 for performing the comparisons needed to identify whether the MPU table 22 includes an entry for an address region comprising the target address specified by the memory access request received from the processing circuitry 4. Where a memory protection table 22 is analogous to an input/output table based memory protection (IOTMP) and memory access requests are received from the processing circuitry 4)
receive a second request to access memory content in the second memory at a second target address from the processing entity via the bus; ( [0080] . . . triggers a memory access request for obtaining the second limit address or the size from the memory system. Where “second limit address” is a second target address.)
access memory access permission information from the memory protection table based on the second target address via the bus; and determine whether the processing entity is allowed to access the memory content at the second target address based on the memory access permission information associated with the second target address ( [0099] While the technique discussed above can be used for any type of control table supporting variable size address regions defined by a first limit address and second limit address or size as discussed above, it can be particularly useful for a memory protection table for which each entry specifies access permissions for the corresponding address region of an address space and the operation performed based on the information in the control table comprises checking of whether a memory access request specifying the query address satisfies the access permissions in a corresponding entry for a region including the query address. Where the second limit address is a second target address. And checking of whether a memory access request specifying the query address satisfies the access permissions is analogous to determining whether the processing entity is allowed to access the meory content of the second targeted address. )
Hoever Grocutt does not expressly disclose; “ a bus” or “a second memory” but this limitations are taught by Moyers; ( [0017] . . . In addition, the data processing system can include a global MPU that can enforce a memory access policy in response to memory access requests issued by any processor core or any bus master. And [0029] . . . and a bus interface unit (BIU) 80. Where The but interface unit 80, interfaces with a bus. And [0072] The method 1000 begins at block 1010 where a memory access request including a memory address is provided to a memory protection unit. For example, the processor core 10 of data processing system 100 of FIG. 1 can issue a request to access the memory device 40 or the slave device 42. Where the slave device is a second memory.)
Grocutt and Moyer are analogous art because they are from the same field of endeavor of memory for data protection using memory protection.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify Grocutt to include “a bus” or “ a second memory”. See Moyer ( [0017] & [0029]).
Regarding claim 19, Grocutt teaches; A method of providing memory protection, comprising: ( [0008] At least some examples provide a method comprising: )
receiving a first request to access memory content at a target address from a first world running on a processor execution core of a processor; ( [0009] issuing a memory access request specifying a target address identifying a location to be accessed in a memory system; [0004] processing circuitry used to issue memory access requests. )
the first request being received by a table-based memory protection (TMP) of the processor [0006] permission checking circuitry to check whether a memory access request issued by the processing circuitry satisfies access permissions specified in a memory protection table stored in the memory system, the memory protection table comprising a plurality of memory protection entries, each memory protection entry specifying: access permissions for a corresponding address region of variable size within an address space, and region identifying parameters for identifying a start address and an end address of the corresponding address region, wherein said MPU is configured to permit said variable size to be a number of bytes other than a power of 2. And [0103] . . . A memory protection table 22 may be stored within the memory system, comprising a number of entries each defining access permissions for a corresponding address region.)
accessing memory access permission information by the TMP from a memory protection table stored in a first memory based on the target address; ( [0010] checking whether the memory access request satisfies access permissions specified in a memory protection table comprising a plurality of memory protection entries, each memory protection entry specifying: access permissions for a corresponding address region of variable size within an address space, and region identifying parameters for identifying a start address and an end address of the corresponding address region, wherein said variable size is permitted to be a number of bytes other than a power of 2; )
and determining by the TMP whether the first world is allowed to access the memory content at the target address based on the accessed memory access permission information. ( [0049] . . . This approach can be useful to reduce the total number of regions which need to be defined to allow a first software process access to a specific sub-region of an address region. Where first world is analogous to first software process that is allowed access to an address region)
However Grocutt does not expressly disclose “an execution core” but these limitations are address by Moyer, ( [0029] Data processing system 100 includes a first processor core 10 identified as CPU 0, a second processor core 12 identified as CPU N, an interconnect 20, a global MPU 30, a memory device 40, and a slave device 42. And [0012] FIG. 8 is a table illustrating permission information stored at a cache memory in accordance with a specific embodiment of the present disclosure. And [0064] The operation of the cache permission information flags can be better understood with reference to FIG. 8. FIG. 8 is a table 800 illustrating permission information stored in a cache memory in accordance with a specific embodiment of the present disclosure. The table 800 includes columns 801, 802, 803, and 804, and rows 810, 811, 812, 813, 814, and 815. The columns 801-803 represent the three permission information flags included in a cache line, such as a cache line of data cache 51 in the data processing system 100 of FIG. 1. And [0065] . . . During operation of data processing system 100 of FIG. 1, if an address associated with a memory access request is determined to be present and valid in a cache memory, the access can be allowed or the request can be denied based in part on the permission information flags associated with the cache line containing the requested information. Where a “table illustrating permission information” is analogous to a “memory protection table”. And the table is store in “cache memory” which is a “first memory”. And first and second processor cores, 10 and 12 are analogous to “execution core”. ).
Locally store; wherein the locally stored (eg., 0025 - permission information maintained in a local MPU included at the processor core.; 0029 - local MPU 60 Fig. 1)
wherein the locally stored memory access permission information includes an indication of at least one of read access permission, write access permission, or associated with the memory content at the first target address (eg., 0064- FIG. 8 is a table 800 illustrating permission information stored in a cache memory; 0065 - 0066- rows 810-815 illustrate permissible combinations of the flags, and the column 804 provides a description of allowed accesses; 0067 - A cache line having this particular combination of flags can be both read and written by a supervisor level request, but cannot be read or written by a user level request).
Grocutt and Moyer are analogous art because they are from the same field of endeavor of memory for data protection using memory protection tables.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify Grocutt to include “an execution core”. See Moyer ( [0029]).
Grocutt and Moyer do not disclose, but Koeberl discloses
execute access permission (eg., 0042 Fig. 2A - region's base address 203 and region's length 205 and access permissions 207 (e.g., read, write, or execute). The region base address 203, region length 205 and region permissions 207 can be stored in a set of one or more registers)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify Grocutt and Moyer with Koeberl, providing the benefit of execution-aware memory protection architectures (see Koeberl, 0001) enforces memory access control by organizing real, physical memory into a number of memory regions with associated access permissions. MPUs can be used for reliability, providing a mechanism to detect errors ranging from programming bugs to hardware failures. MPUs can also have security applications (0025).
Regarding claim 20, Grocutt teaches; further comprising passing the first memory access request to the first memory or a second memory in response to determining that the first world is allowed to access the memory content at the target address. ( [0123] . . . [0123] Alternatively, in the case where there is a hit in the static MPU register storage and the memory access request satisfies the access permission specified by that matching static MPU entry, then the MPU memory access may be suppressed so that there is no access to the memory protection table 22, . . .. For example region 102-1 represented by the static MPU entry could restrict access to the higher privilege process, so addresses within the subrange 100-2 accessed by less privileged code would fail to satisfy the access permissions specified by the static MPU entry, but could pass permission checks implemented based on the corresponding memory-based MPU entry relating to region 100-2. Where for a memory access request that satisfies access permission, the permission check could be passed on the memory-base MPU entry, which is analogous to passing a memory access request in determining the first world is allowed access. )
Regarding claim 21, Grocutt teaches; further comprising writing the memory content at the target address to a cache. ([0081] In some implementations there may be a cache in the memory system between the table lookup circuitry and the memory containing the control table. The table lookup circuitry makes a request to the cache, and if the request cannot be satisfied by the cache, the cache may in response make a request to the memory to retrieve the requested data. In some embodiments the cache may request more data than was originally requested, for example it may request enough data to fill a whole cache line. Hence when the table lookup circuitry performs a request to the cache for just the first limit address, the cache may perform a request to memory for a cache line that includes both the first limit address and the second limit address or the size. It will be appreciated that even though the cache is requesting both the first limit address and second limit address or the size, the table lookup circuitry may only need to receive and compare against, the first limit address (except for the single candidate entry identified following the final search window narrowing step), and hence the power used and circuit complexity is reduced. Where “fill a whole cache line” is writing to a cache and “ cache for just the first limit address” is analogous of to target address to a cache. )
Regarding claim 22, Grocutt teaches; further comprising: receiving, by the TMP, a second request to access the memory content at the target address from a second world running on the processor execution core; ( [0049] Alternatively, for memory access requests . . . the static MPU entry could be set for the wider address region to permit the second software process to access that region. Where “second software” is analogous to second world and where “address region” is analogous to “target address” and where “memory access request” is analogous to second request access. )
and determining, by the TMP, whether the second world is allowed to access the memory content at the target address based on the accessed memory access permission information. ( [0049] Alternatively, for memory access requests which hit in the static memory protection entry but fail the access permissions in that static memory protection entry, the access permissions may be permitted. Where “access permissions may be permitted” is analogous to determining an allowed access. And [0049] . . . This approach can be useful to reduce the total number of regions which need to be defined to allow a first software process access to a specific sub-region of an address region accessed by a second software process. For example, the static MPU entry could be set for the wider address region to permit the second software process to access that region And where a sub-region of an address region accessed by a second software process is analogous to the second world is allow access at the target address.)
Regarding claim 23, Grocutt teaches; further comprising passing, by the TMP, the second memory access request to the cache for accessing the memory content by the second world in response to the TMP determining that the second world is allowed to access the memory content at the target address. ( [0049] . . . For example, the static MPU entry could be set for the wider address region to permit the second software process to access that region but deny the first software process access. Where a second software process is analogous to second world. And “permit the second software process to access” is analogous to second world is allowed access.)
However Grocutt does not expressly disclose: “ passing by the TMP, the second memory access request to the cache for accessing the memory”, but these limitations are addressed by Moyer ([0017] . . . In another embodiment, the comprehensive memory access policy can be implemented by the local MPU based on not only local access permission information, but also upon global access permission information stored at a local cache memory, where the global access permission information was previously provided by a global MPU in response to a cache line fill operation. Where “global access permission information” is analogous to memory access request. And storing access permission information in a local cache memory in response to a cache fill line operation is analogous to passing the memory access request to the cache for accessing memory. And [0024] . . . For another example, a first region descriptor within a first MPU can be configured to permit supervisor-write accesses to a large region of memory, while a second region descriptor at a different MPU can be configured to disallow supervisor-write accesses to a portion of the larger region. Where a second regions descriptor at a different MPU is analogous to passing the second memory access request.)
Grocutt and Moyer are analogous art because they are from the same field of endeavor of memory for data protection using memory protection tables.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify Grocutt to include “passing the second memory access request to the cache for accessing the memory” (See Moyer ([0017] & [0024])
Regarding claim 24, Grocutt teaches; further comprising: accessing, by the TMP, memory access permission information from the memory protection table based on the second memory access request; ([0015] permission checking program logic to check whether a memory access request issued by the processing program logic satisfies access permissions specified in a memory protection table comprising a plurality of memory protection entries, each memory protection entry specifying: access permissions for a corresponding address region of variable size within said simulated address space, and region identifying parameters for identifying a start address and an end address of the corresponding address region, wherein said MPU program logic is configured to permit said variable size to be a number of bytes other than a power of 2; Where memory access requests are checked if they satisfy access permissions specified in a memory protection table. And [0103] A memory protection unit (MPU) 20 is provided for checking based on the target address whether the memory access request is permitted to be serviced by the memory system 10. Access permissions for controlling whether the processing circuitry 4 is allowed to access a given address region may be defined in two ways. A memory protection table 22 may be stored within the memory system, comprising a number of entries each defining access permissions for a corresponding address region. The MPU 20 has MPU memory access circuitry 24 for initiating memory access requests to the memory system 10 in order to obtain information from the MPU table 22. Where the memory protection unit 20, has a memory protection table 22. And [0049] . . . for example, the static MPU entry could be set for the wider address region to permit the second software process to access that region. Where the second software process is analogous to second world.
and determining, by the TMP, whether the second world is allowed to access the memory content at the first target address based on the accessed memory access permission information associated with the second memory access request. [0062] The table identifier of the active memory protection table could be represented in different ways. In one example the table identifier may be identified using a base address alone. Alternatively, in some cases the table may be identified using a combination of a base address and a size. This could be useful if the memory protection tables to be accessed by two different software processes partially overlap, so that the shared part of the memory protection table could be stored at addresses starting at the base address and then the part of the memory protection table only to be used for one particular software process could be located at a subsequent portion of the address space, so that switching between the different memory protection tables accessed by the different pieces of software Where a portion of address space can shared between different pieces of software which is analogous to a second world accessing content at a first target address. And [0062] . . . Hence, a base address register may be provided to store a base address of an active memory protection table to be accessed by the MPU memory access circuitry in response to the memory access request issued by the processing circuitry. And where the determination to share a first target address with a second world is done by memory access circuitry in response to a memory access request. )
Regarding claim 25, Grocutt teaches; further comprising: programming a physical memory protection (PMP) to include memory access permission information for the first world with respect to a first memory address range; ( [0030] . . . Each page table entry specifies the access permissions for a corresponding page of the address space, and often will also specify an address translation mapping for mapping a target address in a first address space (e.g. a virtual address space) to a corresponding page of addresses in a second address space (e.g. a physical address space). Where memory protection using access permissions for both a virtual and physical address space. And [0102] . . . Each memory access request may specify a target address of the location to be accessed. In this example the target address is a physical address directly specifying the location to be accessed, so no address translation is required. Where “each memory access request”, which could be from a first world or a second world, would target a physical address. )
receiving, at the PMP, a second request to access memory content at a second target address within the first memory address range from the first world; ( [0030] . . . An MMU can be useful for processors designed to handle relatively high performance workloads, for which it may be acceptable to set controls over access to many different address regions, e.g. such control may be at a 4 Kbyte granularity, and for which arbitrary mappings of address translations from any page in the first address space to any arbitrary page in the second address space may be required in order to handle accesses triggered by a number of different software processes which use the same virtual address but need to be mapped to different physical addresses used by the memory system. Where a second address space within the first address space may handle accesses by a number of different software processes, like a second world.
and determining, at the PMP, whether the first world is allowed to access the memory content at the second target address based on the programmed memory access permission information. ( [0042] Each memory protection entry corresponds to a given address region of the address space. In some implementations the address space may be a physical address space. Hence, the memory protection table may be queried based on physical addresses specified by the memory access request issued by the processing circuitry, where the physical addresses directly correspond to corresponding locations accessed in the memory system. Where the memory protection table may be queried based upon a physical address space, where the query is a step in the process of checking memory access requests. And [0049] . . . This approach can be useful to reduce the total number of regions which need to be defined to allow a first software process access to a specific sub-region of an address region accessed by a second software process. Where a first software process, or first world, can added an address region accessed by a second software process which is analogous to a second target address.)
Claims 11 is rejected under 35 U.S.C 103 as being unpatentable over Grocutt, (US 20210311884 A1) in view of Moyer, et. al ( US 20120215989 A1 ) and Koeberl (US 20150032996) as applied in rejection of claims 1, 2 and 3 above and further in view of Pathirane, et al. ( US 20110179255 A1).
Regarding claim 11, Grocutt teaches; “ wherein the processor further comprises a tightly coupled memory (TCM), and wherein the second memory comprises the TCM. “ ( [0052] The MPU may comprise MPU cache storage to cache at least one memory protection entry of the memory protection table. The MPU cache storage could be the static MPU register storage in cases when entries are marked as unused as discussed above. However, it can also be useful to provide dedicated MPU cache storage provided to cache entries from the memory protection table, which acts as a cache regardless of how the static memory protection entries (if provided) have been configured. The MPU cache storage could be implemented using a further set of registers within the MPU, similar to the static MPU register storage, or could be implemented using a different type of data storage such as SRAM. In some cases the static MPU register storage and the MPU cache storage may be part of the same storage structure, with some parts partitioned for use as the cache storage and other parts partitioned to store the statically configured memory protection entries. Where a MPU cache or SRAM or static MPU register storage are analogous to tightly coupled memory for a first memory and [0103] . . . The memory system 10 may store more than one MPU table, each table 22 associated with a respective software process. An active table identifier, identifying which particular MPU table is to be accessed using the MPU memory access circuitry 24, is stored in an active table identifier register (or group of registers) 28. For example the active table identifier register 28 may specify a base address 30 of the currently active MPU table, and could also optionally specify a size of the active table. MPU cache storage 32 is provided within the MPU for caching selected entries of the MPU table(s) from the memory system 10, so that if the same entry is needed again then it can be accessed faster. For example the MPU cache storage may comprise a set of registers for locally storing entries of an MPU table with reduced access latency compared to the backing store for the MPU table 22 in memory system 10. Where memory system 10 is a second memory which stores a memory protection table 22, and each table has a group of registers 28 and have a MPU cache storage 32. )
However Grocutt in view of Koeberl does not expressly disclose “ the processor further comprises a tightly coupled memory (TCM)” however these limitations are addressed by Pathirane, et. al (US 20110179255 A1). ( [0019] It will be appreciated that the effect of the partial reset can vary and in particular which functional units are subject to the partial reset can vary between different implementations of the present technique. Examples of functional blocks which are not reset by the partial reset include a register bank, a cache memory, and a memory control unit (such as a memory management unit or a memory protection unit). Where functional blocks include aa memory protection unit. And [0043] Also, provided within the processor 4 are a cache memory 40, a hard error cache 42 and a memory management unit 44 together with a tightly coupled memory 46. The cache memory 40 stores data and instruction values which are supplied to the processing core 22. The hard error cache 42 stores corrected values which have had hard errors identified in them within the values stored within the off-processor memory system, such that the corrected versions of these data values or instructions are supplied directly from the hard error cache 42 when they are reused rather than being refetched in erroneous form from the memory system and subject to error correction. The memory management unit 44 stores page table values for controlling access to the memory, such as mappings between virtual and physical memory, protection attributes and the like. The tightly coupled memory 46 stores a block of data values, such as providing a scratch pad memory for high speed local use by the processing core 22. Where within the processor there are cache memory 40 and tightly coupled memory 46. And where the memory management unit, MMU 44, control access to the memory like protection attributes.)
Grocutt and Koeberl and Pathirane are analogous art because they are from the same field of endeavor of memory managemet including memory protection..
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify Grocutt and Asanovic and Koeberl to include “ the processor further comprises a tightly coupled memory (TCM)”) See Pathirane ([0019] & [0043]).
Claim 15 rejected under 35 U.S.C 103 as being unpatentable over Grocutt, (US 20210311884 A1) in view of Moyer, et. al. ( US 20120215989 A1 ) and Koeberl (US 20150032996) as applied in the rejection of claims 1 and 13 and above, and further in view of Bates, et. al ( US 20080229032 A1).
Regarding claim 15, Grocutt does not expressly teach; wherein the processing entity comprises a direct memory access (DMA). However regarding these limitations, Bates et. al. (US 20070260415 A1) teaches ( [0024] Each SPE is made includes an SPU (SPU0 . . . SPUg). Each SPU in an SPE group has its own local storage area LS and a dedicated memory flow controller MFC that includes an associated memory management unit MMU that can hold and process memory-protection and access-permission information. Where a processing system, synergistic processor unit, SPU, includes a MMU and process memory protection and access permissions. And [0025] The PPEs may be 64-bit PowerPC Processor Units (PPUs) with associated caches. A CBEA-compliant system includes a vector multimedia extension unit in the PPE. The PPEs are general-purpose processing units, which can access system management resources (such as the memory-protection tables, for example). Where the PPE/PPU may have a memory protection table. And [0022] Each PPE group includes a number of PPEs PPE_0 . . . PPE_g SPE. In this example a group of SPEs shares a single cache SL1. The cache SL1 is a first-level cache for direct memory access (DMA) transfers between local storage and main storage. Each PPE in a group has its own first level (internal) cache L1. In addition the PPEs in a group may share a single second-level (external) cache L2. While caches are shown for the SPE and PPE in FIG. 1, they are optional for cell processors in general and CBEA in particular. Where the PPE group has a direct memory access (DMA) And [0033] An SPU program references its local storage domain using a local address. However, privileged software can allow the local storage domain of the SPU to be aliased into main storage domain by setting the D bit of the MFC_SR1 to `1`. Each local storage area is assigned a real address within the main storage domain. (A real address is either the address of a byte in the system memory, or a byte on an I/O device.) This allows privileged software to map a local storage area into the effective address space of an application to allow DMA transfers between the local storage of one SPU and the local storage of another SPU. Where “privileged” or protected software is allowed DMA transfers to effective address space.)
Grocutt and Koeberl with Moyer and Bates are analogous art because they are from the same field of endeavor of memory access and control. Each references are dealing with memory protection using tables and have direct memory access (DMA) components.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify Grocutt and Moyer and Koeberl to include a direct memory access DMA; where modifying Grocutt and Moyer as taught by Bates would provide the benefits of facility of operating a DMA on protected memory. (See Bates [0022] [0024] [0025] & [00 33]).
Response to Arguments
Applicant's arguments filed 12/5/2025 have been fully considered but they are not persuasive.
For claims 1 and 19, Applicant argues that that the cited references do not disclose the amended limitations. The Office disagrees.
In the present OA, the updated combination of references render the amended limitations as obvious.
Specifically, Grocutt and Moyer do not disclose, but Koeberl discloses
execute access permission (eg., 0042 Fig. 2A - region's base address 203 and region's length 205 and access permissions 207 (e.g., read, write, or execute). The region base address 203, region length 205 and region permissions 207 can be stored in a set of one or more registers)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify Grocutt and Moyer with Koeberl, providing the benefit of execution-aware memory protection architectures (see Koeberl, 0001) enforces memory access control by organizing real, physical memory into a number of memory regions with associated access permissions. MPUs can be used for reliability, providing a mechanism to detect errors ranging from programming bugs to hardware failures. MPUs can also have security applications (0025).
Applicant’s arguments for dependent claims are based on their respective base independent claims 1 and 19, which are addressed above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/GAUTAM SAIN/Primary Examiner, Art Unit 2135