DETAILED ACTION
This is in response to communication filed on 7/9/2026.
Status of Claims
Claims 1 – 10, 12 – 16, and 18 – 22 are pending, of which claims 1, 10, and 16 are in independent form.
Claim Objections
In light of applicant’s amendments to the claims, the examiner withdraws the previous objection to the claims.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Machine Translation of Japanese Patent Application JP 3614065 B2 (hereinafter referred to as JP ‘065).
Referring to claim 1, JP ‘065 discloses “A device” (Fig. 8) “comprising: a processing circuit configured to perform an operation to produce an output result having a predetermined output format” ([0005] – [0006] perform multiplication of signed integers, multiplication result being a signed integer), “with a first operand having a first number format and a second operand having a second number format by directly using the first operand in the first number format and the second operand in the second number format to produce an output result” (Fig. 8 and [0075] - [0080] signed or unsigned data multiplied directly and an output produced. Signed data will be one of positive or negative “number format”), “wherein the first number format and the second number format correspond to different number formats of a plurality of number formats” ([0075] - [0080] signed or unsigned data multiplied directly and an output produced. Signed data will be one of positive or negative “number format.” The case of multiplicand data and multiplier data being of opposite signs are covered by JP ‘065 teachings) “that each have a same bit width” ([0070] multiplicand X and multiplier Y are same bit width), and “the predetermined output format corresponds to the first number format or the second number format” ([0005] the multiplication result may have a negative sign. As is understood, the output will be one of a positive or negative integer).
As per claim 2, JP ‘065 discloses “the processing circuit is configured to perform the operation for each of a plurality of possible combinations of the plurality of number formats for the first operand and the second operand” ([0075] - [0080] signed or unsigned data multiplied directly and an output produced. Signed data will be one of positive or negative “number format.” Each possibility of negative*negative, negative*positive, positive*negative, and positive*positive are covered by JP ‘065 teachings).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 – 5, 10, 12, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over JP ‘065 in view of Henry et al., U.S. Patent Application 2019/0042244 (hereinafter referred to as Henry).
As per claim 3, JP ‘065 does not appear to explicitly disclose “the processing circuit includes circuitry, for each of the plurality of possible combinations, to perform the operation.”
However, Henry discloses “the processing circuit includes circuitry, for each of the plurality of possible combinations, to perform the operation” ([0138] "The execution units 862 may perform various operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions").
JP ‘065 and Henry are analogous art because they are from the same field of endeavor, which is processing using various types of data.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of JP ‘065 and Henry before him or her, to modify the teachings of JP ‘065 to include the teachings of Henry so that the device includes circuitry for each combination.
The motivation for doing so would have been to provide a more efficient system that includes dedicated circuitry for each combination. The dedicated circuitry provides better efficiency than utilizing a single execution circuit because the different data precisions would be handled without requiring any changes/transformations/conversion.
Therefore, it would have been obvious to combine Henry with JP ‘065 to obtain the invention as specified in the instant claim.
As per claim 4, JP ‘065 does not appear to explicitly disclose “the processing circuit includes instruction sets, for each of the plurality of possible combinations, to perform the operation.”
However, Henry discloses “the processing circuit includes instruction sets, for each of the plurality of possible combinations, to perform the operation” ([0148] "The cores 902A-N may be homogenous or heterogeneous in terms of architecture instruction set; that is, two or more of the cores 902A-N may be capable of execution the same instruction set, while others may be capable of executing only a subset of that instruction set or a different instruction set").
JP ‘065 and Henry are analogous art because they are from the same field of endeavor, which is processing using various types of data.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of JP ‘065 and Henry before him or her, to modify the teachings of JP ‘065 to include the teachings of Henry so that the device includes multiple instruction sets.
The motivation for doing so would have been to provide a more efficient system that includes dedicated instruction sets for each combination. The dedicated instruction sets can be optimized for each combination of formats.
Therefore, it would have been obvious to combine Henry with JP ‘065 to obtain the invention as specified in the instant claim.
As per claim 5, JP ‘065 discloses operands “that use the first number format and the second number format” ([0075] - [0080] signed or unsigned data multiplied directly and an output produced. Signed data will be one of positive or negative “number format.” Each possibility of negative*negative, negative*positive, positive*negative, and positive*positive are covered by JP ‘065 teachings).
JP ‘065 does not appear to explicitly disclose “the processing circuit is further configured to decode the operation into micro-operations that use the first number format and the second number format.”
However, Henry discloses “the processing circuit is further configured to decode the operation into micro-operations” (Fig. 1 and [0056] At reference 102, an instruction is decoded. The instruction specifies at least two operands. [0137] The decode unit 840 (or decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions).
JP ‘065 and Henry are analogous art because they are from the same field of endeavor, which is processing using various types of data.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of JP ‘065 and Henry before him or her, to modify the teachings of JP ‘065 to include the teachings of Henry so that a decoder decodes an operation into micro-operations for processing the first operand in the first number format and the second operand in the second number format to produce an output result.
The motivation for doing so would have been to utilize well-known instruction decoders, which interpret instructions and provide control signals for the processing circuits to execute the desired task. This allows for instruction code to be more user/human friendly while still controlling the processing circuits correctly.
Therefore, it would have been obvious to combine Henry with JP ‘065 to obtain the invention as specified in the instant claim.
Referring to claim 10, JP ‘065 discloses “A system” (Fig. 8) “comprising:” “a processing circuit configured to receive, for an operation to produce an output result having a predetermined output format” ([0005] – [0006] perform multiplication of signed integers, multiplication result being a signed integer), “a first operand” “having a first number format and a second operand having a second number format, wherein the first number format and the second number format correspond to different number formats” ([0075] - [0080] signed or unsigned data multiplied directly and an output produced. Signed data will be one of positive or negative “number format.” The case of multiplicand data and multiplier data being of opposite signs are covered by JP ‘065 teachings) “that each have a same bit width” ([0070] multiplicand X and multiplier Y are same bit width), and “the predetermined output format corresponds to the first number format or the second number format” ([0005] the multiplication result may have a negative sign. As is understood, the output will be one of a positive or negative integer); “and perform the operation” “that directly use[s] the first operand in the first number format and the second operand in the second number format to produce the output result” (Fig. 8 and [0075] - [0080] signed or unsigned data multiplied directly and an output produced. Signed data will be one of positive or negative “number format”)
JP ‘065 does not appear to explicitly disclose the system comprising “a memory,” the processing circuit receiving operands “from the memory,” nor “decod[ing] the operation into micro-operations that use the first number format and the second number format; and perform[ing] the operation via the decoded micro-operations.”
However, Henry discloses the system comprising “a memory,” the processing circuit receiving operands “from the memory” ([0042] values are often represented in an integer format or a floating-point format. A value occupies a number of bits in computer memory), “decod[ing] the operation into micro-operations that use the first number format and the second number format; and perform[ing] the operation via the decoded micro-operations” (Fig. 1 and [0056] At reference 102, an instruction is decoded. The instruction specifies at least two operands. [0137] The decode unit 840 (or decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions).
JP ‘065 and Henry are analogous art because they are from the same field of endeavor, which is processing using various types of data.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of JP ‘065 and Henry before him or her, to modify the teachings of JP ‘065 to include the teachings of Henry so that a decoder decodes an operation into micro-operations for processing the first operand in the first number format and the second operand in the second number format to produce an output result.
The motivation for doing so would have been to utilize well-known instruction decoders, which interpret instructions and provide control signals for the processing circuits to execute the desired task. This allows for instruction code to be more user/human friendly while still controlling the processing circuits correctly.
Therefore, it would have been obvious to combine Henry with JP ‘065 to obtain the invention as specified in the instant claim.
Note, claim 12 recites the corresponding limitations of claim 2. Therefore, the rejection of claim 2 applies to claim 12.
Also, JP ‘065 discloses “a plurality of possible combinations of the plurality of number formats for the first operand and the second operand” ([0075] - [0080] signed or unsigned data multiplied directly and an output produced. Signed data will be one of positive or negative “number format.” Each possibility of negative*negative, negative*positive, positive*negative, and positive*positive are covered by JP ‘065 teachings).
JP ‘065 does not appear to explicitly disclose “decode the operation into micro-operations by selecting the micro-operations corresponding to one of a plurality of combinations of the plurality of number formats for the first operand and the second operand.”
However, Henry discloses another system for mixed-precision operations ([0047] and [0058]) and the system including steps to “decode the operation into micro-operations by selecting the micro-operations corresponding to” the function and the operands (Fig. 1 and [0056] At reference 102, an instruction is decoded. The instruction specifies at least two operands. [0137] The decode unit 840 (or decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions).
JP ‘065 and Henry are analogous art because they are from the same field of endeavor, which is processing using various types of data.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of JP ‘065 and Henry before him or her, to modify the teachings of JP ‘065 to include the teachings of Henry so that a decoder decodes an operation into micro-operations for processing the first operand in the first number format and the second operand in the second number format to produce an output result.
The motivation for doing so would have been to utilize well-known instruction decoders, which interpret instructions and provide control signals for the processing circuits to execute the desired task. This allows for instruction code to be more user/human friendly while still controlling the processing circuits correctly.
Therefore, it would have been obvious to combine Henry with JP ‘065 to obtain the invention as specified in the instant claim.
Referring to claim 16, JP ‘065 discloses “A method comprising: identifying, for an operation to produce an output result having a predetermined output format” ([0005] – [0006] perform multiplication of signed integers, multiplication result being a signed integer), “a first number format for a first operand of the operation and a second number format for a second operand of the operation, wherein the first number format and the second number format correspond to different number formats of a plurality of number formats” ([0075] - [0080] signed or unsigned data multiplied directly and an output produced. Signed data will be one of positive or negative “number format.” The case of multiplicand data and multiplier data being of opposite signs are covered by JP ‘065 teachings) “that each have a same bit width” ([0070] multiplicand X and multiplier Y are same bit width) and “the predetermined output format corresponds to the first number format or the second number format” ([0005] the multiplication result may have a negative sign. As is understood, the output will be one of a positive or negative integer); “and performing the operation by directly using the first operand and the second operand” “to produce the output result” (Fig. 8 and [0075] - [0080] signed or unsigned data multiplied directly and an output produced. Signed data will be one of positive or negative “number format”).
JP ‘065 does not appear to explicitly disclose the method including “selecting, based on the first number format and the second number format, a set of instructions that use the first number format and the second number format to perform the operation” and performing the operation “with the selected set of instructions.”
However, Henry discloses “selecting, based on the first number format and the second number format, a set of instructions that use the first number format and the second number format to perform the operation” and performing the operation “with the selected set of instructions” ([0148] "The cores 902A-N may be homogenous or heterogeneous in terms of architecture instruction set; that is, two or more of the cores 902A-N may be capable of execution the same instruction set, while others may be capable of executing only a subset of that instruction set or a different instruction set").
JP ‘065 and Henry are analogous art because they are from the same field of endeavor, which is processing using various types of data.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of JP ‘065 and Henry before him or her, to modify the teachings of JP ‘065 to include the teachings of Henry so that the device includes multiple instruction sets.
The motivation for doing so would have been to provide a more efficient system that includes dedicated instruction sets for each combination. The dedicated instruction sets can be optimized for each combination of formats.
Therefore, it would have been obvious to combine Henry with JP ‘065 to obtain the invention as specified in the instant claim.
Claims 8, 15, 20 are rejected under 35 U.S.C. 103 as being unpatentable over JP ‘065 in view of Fan et al., Machine Translation of Chinese Patent Application CN 116795324 A (hereinafter referred to as Fan).
As per claim 8, JP ‘065 does not appear to explicitly disclose “the processing circuit is further configured to perform the operation with a third operand having a third number format by directly using the third operand in the third number format to produce the output result.”
However, Fan discloses “the processing circuit is further configured to perform the operation with a third operand having a third number format by directly using the third operand in the third number format to produce the output result” (page 6 lines 5 – 12 “at least two floating point operands” and “the number and precision type of the floating point operands with different precisions are not limited”).
JP ‘065 and Fan are analogous art because they are from the same field of endeavor, which is processing using various types of data.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of JP ‘065 and Fan before him or her, to modify the teachings of JP ‘065 to include the teachings of Fan so that the operation is performed with a third operand having a third number format.
The motivation for doing so would have been to further improve the computation efficiency of the mixing precision (as stated by Fan at the top of page 5).
Therefore, it would have been obvious to combine Fan with JP ‘065 to obtain the invention as specified in the instant claim.
Note, claim 15 recites the corresponding limitations of claim 8. Therefore, the rejection of claim 8 applies to claim 15.
Note, claim 20 recites the corresponding limitations of claim 8. Therefore, the rejection of claim 8 applies to claim 20.
Allowable Subject Matter
Claims 6, 7, 9, 13 – 14, 18 – 19, and 21 – 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claims 1, 10, and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Machine Translation of Japanese Patent Application JP 3544821 B2 teaches performing signed division without converting a negative value of a dividend and/or a divisor into a positive value.
U.S. Patent 6393554 teaches a computation core handling many different number formats.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN G SNYDER whose telephone number is (571)270-1971. The examiner can normally be reached on M-F 8:00am-4:30pm (flexible).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVEN G SNYDER/Primary Examiner, Art Unit 2184
