DETAILED ACTION
This is in response to the request for continued examination filed on 2/20/2026.
Status of Claims
Claims 1 – 10, 12 – 16, and 18 – 22 are pending, of which claims 1, 10, and 16 are in independent form.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/20/2026 has been entered.
Claim Objections
Claims 10, 12 – 16, and 18 – 22 are objected to because of the following informalities: Independent claims 10 and 16 as amended state “and plurality of number formats includes the predetermined output format.” The examiner recommends amending both claims 10 and 16 to state “and the plurality of number formats includes the predetermined output format.” Claims 12 – 15 and 18 – 22 inherit this objection based on their dependencies. Appropriate correction is required.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections – 35 USC 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 2 are rejected under 35 U.S.C. 103 as being unpatentable over Fan et al., Machine Translation of Chinese Patent Application CN 116795324 A (hereinafter referred to as Fan) in view of Das Sarma et al., U.S. Patent Application 2020/0349216 (hereinafter referred to as Das Sarma).
Referring to claim 1, Fan discloses “A device comprising: a processing circuit configured to perform an operation” “with a first operand having a first number format and a second operand having a second number format by directly using the first operand in the first number format and the second operand in the second number format to produce an output result, wherein the first number format and the second number format correspond to different number formats of a plurality of number formats” (page 5 paragraph beginning with “In one embodiment” teaches as shown in Fig. 1, a hybrid precision floating point multiplication device is provided. Page 6 lines 1 – 9 teaches at least two floating point operands comprising an index part and a mantissa part and states “The at least two floating-point operands may include the same precision floating-point operands, and may also include different precision floating-point operands.” Page 6 lines 10 – 12 teaches “The floating point operands with different precisions include FP8, FP32, BF16, FP8-M2E5 and other floating point operands with different precisions”).
Fan does not appear to explicitly disclose “wherein the first number format and the second number format correspond to different number formats of a plurality of number formats that each have a same bit width.”
However, Das Sarma discloses “wherein the first number format and the second number format correspond to different number formats of a plurality of number formats that each have a same bit width” (Fig. 4 and [0060] teaching 2 different formats of 8 bit floating point data. [0061] a 4-bit mantissa and 3-bit exponent format may be supported (not shown)).
Fan also does not appear to explicitly disclose “to perform an operation to produce an output result having a predetermined output format” and “the plurality of number formats includes the predetermined output format.”
However, Das Sarma discloses “to perform an operation to produce an output result having a predetermined output format” and “the plurality of number formats includes the predetermined output format” ([0037] Each input array is sized to fit an entire input matrix and each output accumulator is sized to fit an entire matrix result. In some embodiments, the node engine supports multiple floating-point formats including the 8-bit floating-point formats 400 and 410 of FIG. 4 and the 21-bit floating-point format 500 of FIG. 5. [0048] By optimizing the matrix elements using a configurable 8-bit floating-point format, the bandwidth for loading matrix elements into a matrix processor is improved significantly. Power consumption per area is also drastically improved. To prevent overflow and underflow errors, the intermediate and final results stored in the designated accumulator utilize a larger bit format, such as a 21-bit, 27-bit, or another appropriate floating-point format). Note that Applicant’s claim language can be reasonably interpreted broadly so that “wherein the first number format and the second number format correspond to different number formats of a plurality of number formats that each have a same bit width, and the plurality of number formats includes the predetermined output format” refers to two operands with different number formats, but a same bit width, as well as another, separate output format which may not have the same bit width. If Applicant is attempting to claim that the output format also has the same bit width as the operands, the examiner suggests further clarification.
It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to combine Das Sarma with Fan so that the first number format and the second number format correspond to different number formats of a plurality of number formats that have a same bit width.
Fan and Das Sarma are analogous art because they are from the same field of endeavor, which is computations involving different data precisions/formats.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Fan and Das Sarma before him or her, to modify the teachings of Fan to include the teachings of Das Sarma so that the first number format and the second number format correspond to different number formats of a plurality of number formats that have a same bit width.
The motivation for doing so would have been to support multiple floating-point formats in order to improve bandwidth and performance (as stated by Das Sarma at [0036]).
Therefore, it would have been obvious to combine Das Sarma with Fan to obtain the invention as specified in the instant claim.
As per claim 2, Fan discloses “the processing circuit is configured to perform the operation for each of a plurality of possible combinations of the plurality of number formats for the first operand and the second operand” (page 5 paragraph beginning with “In one embodiment” teaches as shown in Fig. 1, a hybrid precision floating point multiplication device is provided. Page 6 lines 1 – 9 teaches “The at least two floating-point operands may include the same precision floating-point operands, and may also include different precision floating-point operands.” Page 6 lines 10 – 12 teaches “The floating point operands with different precisions include FP8, FP32, BF16, FP8-M2E5 and other floating point operands with different precisions”).
Also, Das Sarma discloses Das Sarma discloses “the processing circuit is configured to perform the operation for each of a plurality of possible combinations of the plurality of number formats for the first operand and the second operand” (Fig. 4 and [0060] teaching 2 different formats of 8 bit floating point data. [0061] a 4-bit mantissa and 3-bit exponent format may be supported (not shown)).
Claims 3 – 5, 8, 10, 12, 15, 16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Fan in view of Das Sarma, as applied to claims above, further in view of Henry et al., U.S. Patent Application 2019/0042244 (hereinafter referred to as Henry).
As per claim 3, neither Fan nor Das Sarma appears to explicitly disclose “the processing circuit includes circuitry, for each of the plurality of possible combinations, to perform the operation.”
However, Henry discloses “the processing circuit includes circuitry, for each of the plurality of possible combinations, to perform the operation” ([0138] "The execution units 862 may perform various operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions").
Fan, Das Sarma, and Henry are analogous art because they are from the same field of endeavor, which is floating-point processing and precision.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Fan, Das Sarma, and Henry before him or her, to modify the teachings of Fan and Das Sarma to include the teachings of Henry so that the device includes circuitry for each combination.
The motivation for doing so would have been to provide a more efficient system that includes dedicated circuitry for each combination. The dedicated circuitry provides better efficiency than utilizing a single execution circuit because the different data precisions would be handled without requiring any changes/transformations/conversion.
Therefore, it would have been obvious to combine Henry with Fan and Das Sarma to obtain the invention as specified in the instant claim.
As per claim 4, neither Fan nor Das Sarma appears to explicitly disclose “the processing circuit includes instruction sets, for each of the plurality of possible combinations, to perform the operation.”
However, Henry discloses “the processing circuit includes instruction sets, for each of the plurality of possible combinations, to perform the operation” ([0148] "The cores 902A-N may be homogenous or heterogeneous in terms of architecture instruction set; that is, two or more of the cores 902A-N may be capable of execution the same instruction set, while others may be capable of executing only a subset of that instruction set or a different instruction set").
Fan, Das Sarma, and Henry are analogous art because they are from the same field of endeavor, which is floating-point processing and precision.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Fan, Das Sarma, and Henry before him or her, to modify the teachings of Fan and Das Sarma to include the teachings of Henry so that the device includes multiple instruction sets.
The motivation for doing so would have been to provide a more efficient system that includes dedicated instruction sets for each combination. The dedicated instruction sets can be optimized for each combination of formats.
Therefore, it would have been obvious to combine Henry with Fan and Das Sarma to obtain the invention as specified in the instant claim.
As per claim 5, Fan discloses operands “that use the first number format and the second number format” (Page 6 lines 1 – 9 teaches at least two floating point operands comprising an index part and a mantissa part and states “The at least two floating-point operands may include the same precision floating-point operands, and may also include different precision floating-point operands.” Page 6 lines 10 – 12 teaches “The floating point operands with different precisions include FP8, FP32, BF16, FP8-M2E5 and other floating point operands with different precisions”).
Neither Fan nor Das Sarma appears to explicitly disclose “the processing circuit is further configured to decode the operation into micro-operations that use the first number format and the second number format.”
However, Henry discloses “the processing circuit is further configured to decode the operation into micro-operations” (Fig. 1 and [0056] At reference 102, an instruction is decoded. The instruction specifies at least two operands. [0137] The decode unit 840 (or decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions).
Fan, Das Sarma, and Henry are analogous art because they are from the same field of endeavor, which is floating-point processing and precision.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Fan, Das Sarma, and Henry before him or her, to modify the teachings of Fan and Das Sarma to include the teachings of Henry so that a decoder decodes an operation into micro-operations for processing the first operand in the first number format and the second operand in the second number format to produce an output result.
The motivation for doing so would have been to utilize well-known instruction decoders, which interpret instructions and provide control signals for the processing circuits to execute the desired task. This allows for instruction code to be more user/human friendly while still controlling the processing circuits correctly.
Therefore, it would have been obvious to combine Henry with Fan and Das Sarma to obtain the invention as specified in the instant claim.
As per claim 8, Fan discloses “the processing circuit is further configured to perform the operation with a third operand having a third number format by directly using the third operand in the third number format to produce the output result” (page 6 lines 5 – 12 “at least two floating point operands” and “the number and precision type of the floating point operands with different precisions are not limited”).
Further, as learned from In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960), mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In this case, it would have been obvious to one of ordinary skill at the time of Applicant’s filing to directly use a third operand for processing along with the first two described operands of Fan.
Referring to claim 10, Fan discloses “A system comprising: a memory; and a processing circuit” (“in FIG. 9. The computer device comprises a processor, a memory”) “configured to: receive, for an operation to produce an output result”, “a first operand from the memory having a first number format and a second operand having a second number format, wherein the first number format and the second number format correspond to different number formats of a plurality of number formats”; and “perform the operation” “that directly use the first operand in the first number format and the second operand in the second number format to produce the output result” (page 5 paragraph beginning with “In one embodiment” teaches as shown in Fig. 1, a hybrid precision floating point multiplication device is provided. Page 6 lines 1 – 9 teaches at least two floating point operands comprising an index part and a mantissa part and states “The at least two floating-point operands may include the same precision floating-point operands, and may also include different precision floating-point operands.” Page 6 lines 10 – 12 teaches “The floating point operands with different precisions include FP8, FP32, BF16, FP8-M2E5 and other floating point operands with different precisions”).
Fan does not appear to explicitly disclose “wherein the first number format and the second number format correspond to different number formats of a plurality of number formats that each have a same bit width.”
However, Das Sarma discloses “wherein the first number format and the second number format correspond to different number formats of a plurality of number formats that each have a same bit width” (Fig. 4 and [0060] teaching 2 different formats of 8 bit floating point data. [0061] a 4-bit mantissa and 3-bit exponent format may be supported (not shown)).
Fan also does not appear to explicitly disclose “an operation to produce an output result having a predetermined output format” and “the plurality of number formats includes the predetermined output format.”
However, Das Sarma discloses “an operation to produce an output result having a predetermined output format” and “the plurality of number formats includes the predetermined output format” ([0037] Each input array is sized to fit an entire input matrix and each output accumulator is sized to fit an entire matrix result. In some embodiments, the node engine supports multiple floating-point formats including the 8-bit floating-point formats 400 and 410 of FIG. 4 and the 21-bit floating-point format 500 of FIG. 5. [0048] By optimizing the matrix elements using a configurable 8-bit floating-point format, the bandwidth for loading matrix elements into a matrix processor is improved significantly. Power consumption per area is also drastically improved. To prevent overflow and underflow errors, the intermediate and final results stored in the designated accumulator utilize a larger bit format, such as a 21-bit, 27-bit, or another appropriate floating-point format). Note that Applicant’s claim language can be reasonably interpreted broadly so that “wherein the first number format and the second number format correspond to different number formats of a plurality of number formats that each have a same bit width and [the] plurality of number formats includes the predetermined output format” refers to two operands with different number formats, but a same bit width, as well as another, separate output format which may not have the same bit width. If Applicant is attempting to claim that the output format also has the same bit width as the operands, the examiner suggests further clarification.
It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to combine Das Sarma with Fan so that the first number format and the second number format correspond to different number formats of a plurality of number formats that have a same bit width.
Fan and Das Sarma are analogous art because they are from the same field of endeavor, which is computations involving different data precisions/formats.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Fan and Das Sarma before him or her, to modify the teachings of Fan to include the teachings of Das Sarma so that the first number format and the second number format correspond to different number formats of a plurality of number formats that have a same bit width.
The motivation for doing so would have been to support multiple floating-point formats in order to improve bandwidth and performance (as stated by Das Sarma at [0036]).
Neither Fan nor Das Sarma appears to explicitly disclose “decode the operation into micro-operations that use the first number format and the second number format” and “perform the operation via the decoded micro-operations.”
However, Henry discloses another system for mixed-precision operations ([0047] and [0058]) and the system including steps to “decode the operation into micro-operations” and “perform the operation via the decoded micro-operations” (Fig. 1 and [0056] At reference 102, an instruction is decoded. The instruction specifies at least two operands. [0137] The decode unit 840 (or decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions).
Fan, Das Sarma, and Henry are analogous art because they are from the same field of endeavor, which is floating-point processing and precision.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Fan, Das Sarma, and Henry before him or her, to modify the teachings of Fan and Das Sarma to include the teachings of Henry so that a decoder decodes an operation into micro-operations for processing the first operand in the first number format and the second operand in the second number format to produce an output result.
The motivation for doing so would have been to utilize well-known instruction decoders, which interpret instructions and provide control signals for the processing circuits to execute the desired task. This allows for instruction code to be more user/human friendly while still controlling the processing circuits correctly.
Therefore, it would have been obvious to combine Henry with Fan and Das Sarma to obtain the invention as specified in the instant claim.
Note, claim 12 recites the corresponding limitations of claim 2. Therefore, the rejection of claim 2 applies to claim 12.
Also, Fan discloses “a plurality of combinations of the plurality of number formats for the first operand and the second operand” (Page 6 lines 1 – 9 teaches at least two floating point operands comprising an index part and a mantissa part and states “The at least two floating-point operands may include the same precision floating-point operands, and may also include different precision floating-point operands.” Page 6 lines 10 – 12 teaches “The floating point operands with different precisions include FP8, FP32, BF16, FP8-M2E5 and other floating point operands with different precisions”).
Neither Fan nor Das Sarma appears to explicitly disclose “decode the operation into micro-operations by selecting the micro-operations corresponding to one of a plurality of combinations of the plurality of number formats for the first operand and the second operand.”
However, Henry discloses another system for mixed-precision operations ([0047] and [0058]) and the system including steps to “decode the operation into micro-operations by selecting the micro-operations corresponding to” the function and the operands (Fig. 1 and [0056] At reference 102, an instruction is decoded. The instruction specifies at least two operands. [0137] The decode unit 840 (or decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions).
Fan, Das Sarma, and Henry are analogous art because they are from the same field of endeavor, which is floating-point processing and precision.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Fan, Das Sarma, and Henry before him or her, to modify the teachings of Fan and Das Sarma to include the teachings of Henry so that a decoder decodes an operation into micro-operations for processing the first operand in the first number format and the second operand in the second number format to produce an output result.
The motivation for doing so would have been to utilize well-known instruction decoders, which interpret instructions and provide control signals for the processing circuits to execute the desired task. This allows for instruction code to be more user/human friendly while still controlling the processing circuits correctly.
Therefore, it would have been obvious to combine Henry with Fan and Das Sarma to obtain the invention as specified in the instant claim.
Note, claim 15 recites the corresponding limitations of claim 8. Therefore, the rejection of claim 8 applies to claim 15.
Referring to claim 16, Fan discloses “A method comprising: identifying, for an operation to produce an output result,” “a first number format for a first operand of the operation and a second number format for a second operand of the operation” (page 5 paragraph beginning with “In one embodiment” teaches as shown in Fig. 1, a hybrid precision floating point multiplication device is provided. Page 6 lines 1 – 9 teaches at least two floating point operands comprising an index part and a mantissa part and states “The at least two floating-point operands may include the same precision floating-point operands, and may also include different precision floating-point operands.” Page 6 lines 10 – 12 teaches “The floating point operands with different precisions include FP8, FP32, BF16, FP8-M2E5 and other floating point operands with different precisions.” First paragraph of page 11 “in order to be based on the application of the hybrid precision floating point multiplication device, the floating point operand X and the floating point operand Y are obtained from the register, in response to the multiplication processing instruction of the floating point operand X and the floating point operand Y, unpacking the floating-point operand X and floating-point operand Y to obtain respective corresponding symbol, index and mantissa”), “wherein the first number format and the second number format correspond to different number formats of a plurality of number formats” (Fig. 2, Fan describes FP8 and BF16); “and performing the operation by directly using the first operand and the second operand with the” instruction “to produce the output result” (Second paragraph of page 11 “performing multiplication processing”).
Fan does not appear to explicitly disclose “wherein the first number format and the second number format correspond to different number formats that each have a same bit width.”
However, Das Sarma discloses “wherein the first number format and the second number format correspond to different number formats that each have a same bit width” (Fig. 4 and [0060] teaching 2 different formats of 8 bit floating point data. [0061] a 4-bit mantissa and 3-bit exponent format may be supported (not shown)).
Fan also does not appear to explicitly disclose “an operation to produce an output result having a predetermined output format” and “[the] plurality of number formats includes the predetermined output format.”
However, Das Sarma discloses “an operation to produce an output result having a predetermined output format” and “[the] plurality of number formats includes the predetermined output format” ([0037] Each input array is sized to fit an entire input matrix and each output accumulator is sized to fit an entire matrix result. In some embodiments, the node engine supports multiple floating-point formats including the 8-bit floating-point formats 400 and 410 of FIG. 4 and the 21-bit floating-point format 500 of FIG. 5. [0048] By optimizing the matrix elements using a configurable 8-bit floating-point format, the bandwidth for loading matrix elements into a matrix processor is improved significantly. Power consumption per area is also drastically improved. To prevent overflow and underflow errors, the intermediate and final results stored in the designated accumulator utilize a larger bit format, such as a 21-bit, 27-bit, or another appropriate floating-point format). Note that Applicant’s claim language can be reasonably interpreted broadly so that “wherein the first number format and the second number format correspond to different number formats of a plurality of number formats that each have a same bit width and [the] plurality of number formats includes the predetermined output format” refers to two operands with different number formats, but a same bit width, as well as another, separate output format which may not have the same bit width. If Applicant is attempting to claim that the output format also has the same bit width as the operands, the examiner suggests further clarification.
It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to combine Das Sarma with Fan so that the first number format and the second number format correspond to different number formats of a plurality of number formats that have a same bit width.
Fan and Das Sarma are analogous art because they are from the same field of endeavor, which is computations involving different data precisions/formats.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Fan and Das Sarma before him or her, to modify the teachings of Fan to include the teachings of Das Sarma so that the first number format and the second number format correspond to different number formats of a plurality of number formats that have a same bit width.
The motivation for doing so would have been to support multiple floating-point formats in order to improve bandwidth and performance (as stated by Das Sarma at [0036]).
Neither Fan nor Das Sarma appears to explicitly disclose “selecting, based on the first number format and the second number format, a set of instructions that use the first number format and the second number format to perform the operation” and “the selected set of instructions.”
However, Henry discloses “a set of instructions that use the first number format and the second number format to perform the operation” ([0138] "The execution units 862 may perform various operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions." Also, [0148] "The cores 902A-N may be homogenous or heterogeneous in terms of architecture instruction set; that is, two or more of the cores 902A-N may be capable of execution the same instruction set, while others may be capable of executing only a subset of that instruction set or a different instruction set").
It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to combine the teachings of Henry with Fan and Das Sarma so that a method includes “selecting, based on the first number format and the second number format, a set of instructions that use the first number format and the second number format to perform the operation.”
In other words, in a system that provides multiple cores/execution units dedicated to executing specific sets of functions, it would have been obvious to one of ordinary skill to select the execution unit/set of instructions based on the source operand formats.
Fan, Das Sarma, and Henry are analogous art because they are from the same field of endeavor, which is floating-point processing and precision.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Fan, Das Sarma, and Henry before him or her, to modify the teachings of Fan and Das Sarma to include the teachings of Henry so that the method includes selecting a set of instruction for handling processing based on the first number format and the second number format.
The motivation for doing so would have been to provide a more efficient system that includes dedicated instruction sets for each combination. The dedicated instruction sets can be optimized for each combination of formats.
Therefore, it would have been obvious to combine Henry with Fan and Das Sarma to obtain the invention as specified in the instant claim.
Note, claim 20 recites the corresponding limitations of claim 8. Therefore, the rejection of claim 8 applies to claim 20.
Claims 6 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Fan in view of Das Sarma, further in view of Henry, further in view of Olson et al., U.S. Patent Application 2010/0250639 (hereinafter referred to as Olson).
As per claim 6, Fan discloses “a first sign, a first exponent, and a first mantissa of the first operand” “a second sign, a second exponent, and a second mantissa of the second operand” (page 5 lines 3 - 4 the bias of at least two floating point operands. Also, page 12 lines 5 – 9 “the exponent corresponding to each floating point operand” and “the mantissa of each floating point operand”). Fan also discloses “the first number format” and “the second number format” (Page 6 lines 1 – 9 teaches at least two floating point operands comprising an index part and a mantissa part and states “The at least two floating-point operands may include the same precision floating-point operands, and may also include different precision floating-point operands.” Page 6 lines 10 – 12 teaches “The floating point operands with different precisions include FP8, FP32, BF16, FP8-M2E5 and other floating point operands with different precisions”).
Also, Das Sarma discloses “a first sign, a first exponent, and a first mantissa of the first operand” “a second sign, a second exponent, and a second mantissa of the second operand” (Fig. 4). Fan also discloses “the first number format” and “the second number format” (Fig. 4).
As above, Henry discloses “the micro-operations” (Fig. 1 and [0056] At reference 102, an instruction is decoded. The instruction specifies at least two operands. [0137] The decode unit 840 (or decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions).
Neither Fan nor Das Sarma nor Henry appears to explicitly disclose “the micro-operations include micro-operations for normalizing a first sign, a first exponent, and a first mantissa of the first operand based on the first number format and normalizing a second sign, a second exponent, and a second mantissa of the second operand based on the second number format.”
However, normalizing floating point numbers is known in the art. For example, Olson teaches floating-point operations and a normalization circuit (abstract). Further Olson teaches “normalizing a first sign, a first exponent, and a first mantissa of the first operand” and “normalizing a second sign, a second exponent, and a second mantissa of the second operand” ([0096] The above discussion assumed that the divide operands were already normalized before the exponent arithmetic was performed. To normalize a denormal mantissa, the mantissa is shifted left by the number of leading zeros, which has the effect of multiplying the mantissa by 2 for each bit position shifted. To maintain the same arithmetic value, the exponent of the normalized mantissa may be decremented by 1 for each bit position the mantissa is shifted during normalization).
It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to combine Olson with Fan/Das Sarma/Henry so that the micro-operations include micro-operations for normalizing a first sign, a first exponent, and a first mantissa of the first operand based on the first number format and normalizing a second sign, a second exponent, and a second mantissa of the second operand based on the second number format.
As above, Fan teaches different precision floating-point operands. Therefore, when normalizing the operands, it would have been obvious to normalize ‘based on the first number format’ and ‘based on the second number format.’
Fan, Das Sarma, Henry, and Olson are analogous art because they are from the same field of endeavor, which is floating-point processing and precision.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Fan, Das Sarma, Henry, and Olson before him or her, to modify the teachings of Fan, Das Sarma, and Henry to include the teachings of Olson so that the micro-operations include micro-operations for normalizing a first sign, a first exponent, and a first mantissa of the first operand based on the first number format and normalizing a second sign, a second exponent, and a second mantissa of the second operand based on the second number format.
The motivation for doing so would have been to provide for a common representation of floating point numbers and to optimize the range of numbers that can be represented.
Therefore, it would have been obvious to combine Olson with Fan, Das Sarma, and Henry to obtain the invention as specified in the instant claim.
Note, claim 18 recites the corresponding limitations of claim 6. Therefore, the rejection of claim 6 applies to claim 18.
Claims 7, 14, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Fan in view of Das Sarma, further in view of Henry, and further in view of Olson, and further in view of Rao et al., “IMPLEMENTATION OF THE STANDARD FLOATING POINT MAC USING IEEE 754 FLOATING POINT ADDER” (hereinafter referred to as Rao).
As per claim 7, Henry discloses “the micro-operations” (Fig. 1 and [0056] At reference 102, an instruction is decoded. The instruction specifies at least two operands. [0137] The decode unit 840 (or decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions).
Neither Fan nor Das Sarma nor Henry nor Olson appears to explicitly disclose “the micro-operations include micro-operations for combining the first sign with the second sign, the first mantissa with the second mantissa, and the first exponent with the second exponent in accordance with the operation to produce the output result.”
However, Rao discloses another floating point processing device “for combining the first sign with the second sign, the first mantissa with the second mantissa, and the first exponent with the second exponent in accordance with the operation to produce the output result” (Fig. 4 floating point multiplier with A_sign and B_sign combined, A_Exponent and B_Exponent combined, and A_Mantissa and B_Mantissa combined to produce a result).
Fan, Das Sarma, Henry, Olson, and Rao are analogous art because they are from the same field of endeavor, which is floating-point processing.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Fan, Das Sarma, Henry, Olson, and Rao before him or her, to modify the teachings of Fan, Das Sarma, Henry, and Olson to include the teachings of Rao so that the micro-operations include micro-operations for combining the first sign with the second sign, the first mantissa with the second mantissa, and the first exponent with the second exponent in accordance with the operation to produce the output result.
The motivation for doing so would have been to provide a means for proper and simple multiplication of floating point operands (as stated by Rao at section III. C).
Therefore, it would have been obvious to combine Rao with Fan, Das Sarma, Henry, and Olson to obtain the invention as specified in the instant claim.
Note, claim 14 recites the corresponding limitations of claims 6 and 7. Therefore, the rejections of claims 6 and 7 apply to claim 14.
Note, claim 19 recites the corresponding limitations of claim 7. Therefore, the rejection of claim 7 applies to claim 19.
Allowable Subject Matter
Claims 9, 13, 21, and 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant argues, on pages 8 – 9 section A., that
Fan describes dynamically arriving at a mixed precision floating-point number. Even if, ad arguendo, Fan suggests "first number format and the second number format correspond to different number formats of a plurality of number formats," Fan fails to disclose or suggest "an operation to produce an output result having a predetermined output format" and "the plurality of number formats includes the predetermined output format," as recited by currently amended independent claim 1. Das Sarma is not seen to cure these deficiencies of Fan. Accordingly, currently amended independent claim 1 is patentably distinguishable from the cited references.
Fan thus does not disclose "an operation to produce an output result having a predetermined output format," "a plurality of number formats that each have a same bit width," and "the plurality of number formats includes the predetermined output format," as recited by claim 1. The Office Action does not allege that Das Sarma discloses this language of claim 1. As such, even if one of ordinary skill would have been led to modify Fan based on Das Sarma in the manner proposed by the Office Action (which Applicant does not concede), the Office Action's proposed modification would not have disclosed at least the quoted language of claim 1.
The examiner disagrees. As above, Das Sarma teaches a predetermined output format. This predetermined output format fits with “the plurality of number formats includes the predetermined output format.” As above, Das Sarma’s teachings, when using the broadest reasonable interpretation, meets Applicant’s claim language. Notably, Das Sarma’s predetermined output format is not of the same bit width as the operands.
Again, the examiner notes that Applicant’s claim language can be reasonably interpreted broadly so that “wherein the first number format and the second number format correspond to different number formats of a plurality of number formats that each have a same bit width and [the] plurality of number formats includes the predetermined output format” refers to two operands with different number formats, but a same bit width, as well as another, separate output format which may not have the same bit width. If Applicant is attempting to claim that the output format also has the same bit width as the operands, the examiner suggests further clarification, as well as convincing evidence that this feature is supported by the original disclosure.
Applicant had cited [0035] – [0037] and [0045] – [0046] of the originally filed specification for support for this amendment. The examiner finds a best description at [0037], which states “In some examples, the output result can be in one of the formats of either operand, such as the first floating point number format or the second floating point number format, although in other examples the output result can be in another desired floating point number format.” Notably, this paragraph does not clarify that the output result would have the same bit width as the operands.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent 12,554,466 teaches computation on numbers in formats such as BFloat16, IEEE half-precision 16-bit float FP16, or the like for neural networks.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN G SNYDER whose telephone number is (571)270-1971. The examiner can normally be reached on M-F 8:00am-4:30pm (flexible).
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/STEVEN G SNYDER/Primary Examiner, Art Unit 2184