Prosecution Insights
Last updated: April 19, 2026
Application No. 18/400,022

PRINTED CIRCUIT BOARD AND ELECTRONIC DEVICE

Non-Final OA §103
Filed
Dec 29, 2023
Examiner
GANI, OBAIDUL NMN
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Huawei Technologies Co., Ltd.
OA Round
1 (Non-Final)
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant

Examiner Intelligence

Grants only 0% of cases
0%
Career Allow Rate
0 granted / 0 resolved
-68.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
3 currently pending
Career history
3
Total Applications
across all art units

Statute-Specific Performance

§103
50.0%
+10.0% vs TC avg
§102
50.0%
+10.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 0 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . 6.36 Drawings Do Not Show Claimed Subject Matter The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the Substrate layers as disclosed in Claim-10 & Claim-11 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1, 2, 3, 8, 14, 15 - are rejected under 35 U.S.C. 103 as being unpatentable over Chen [US20180177056] in view of Kariya et.al., US 20070134910 Regrading Claim-1 & Claim-2: Chen discloses - A printed circuit board (Fig. 3) , having a core board and a substrate (Fig. 3, 101), wherein the core board covers (Fig. 3, 103, 104, 1021) and is disposed on one of two opposing outer surfaces of the substrate (Fig. 3); and the core board having a first conductive layer (Fig. 3, 104), located on a side that is of the core board and that is away from the substrate; a second conductive layer, located on a side that is of the core board and that is close to the substrate (Fig. 3, 1021); and a first dielectric layer (Fig. 3, 103), located between the first conductive layer and the second conductive layer (Fig. 3). Chen does not disclose having a flexible dielectric layer, wherein a Young's modulus of the flexible dielectric layer is less than or equal to a preset Young's modulus, wherein the preset Young's modulus is less than or equal to 15 GPa. Kariya et. al. discloses having a flexible dielectric layer, wherein a Young's modulus of the flexible dielectric layer is less than or equal to a preset Young's modulus, wherein the preset Young's modulus is less than or equal to 15 GPa (Paragraph 30). Would have been obvious to one skilled in the art at the time of the invention having a flexible dielectric layer, wherein a Young's modulus of the flexible dielectric layer is less than or equal to a preset Young's modulus, wherein the preset Young's modulus is less than or equal to 15 GPa as shown Kariya et. al. -with the circuit board of Chen, since this is commonly done so as to provide certain flexibility to the circuit board to help prevent damage from bending. Regarding Claim-3, Chen discloses wherein the core board also covers and is disposed on the other outer surface of the two opposing outer surfaces of the substrate (Fig. 3, 103, 104, 1021) shows those layers at the both sides of the substrate. Regarding Claim-8, Chen discloses the surface that is of the flexible dielectric layer (Fig., 103) [this dielectric layer has some degree of flexibility thus flexible] - and that is close to the first conductive layer is closely attached to the first conductive layer (Fig. 3, 104), and the surface that is of the flexible dielectric layer and that is close to the second conductive layer is closely attached to the second conductive layer (Fig. 3, 1021). Regarding Claim-14, Chen discloses that the flexible dielectric layer is made of a polyimide material (Paragraph- 0005), Regarding Claim-15, Chen discloses that the power device is electrically connected to the printed circuit board (Fig. 1, 1 shows a schematic view of a known electronic product with an LCD) is connected with an electric device Claim(s) 4 – is/ are rejected under 35 U.S.C. 103 as being unpatentable over Chen [US20180177056] in view of Kariya et.al., US 20070134910 as detailed in Claim rejection one above and further in view of KIM [US 20220110212] Regarding Claim-4, modified Chen does not disclose the first dielectric layer further comprises a prepreg, and the first dielectric layer is formed through hybrid lamination on the flexible dielectric layer and the prepreg. However KIM discloses the first dielectric layer further comprises a prepreg (Fig. 7, 50), and the first dielectric layer (Fig. 7, 13). >> Further claim language “is formed through hybrid lamination on the flexible dielectric layer and the prepreg”- is not given patentable weight since this a method of making the device which is not germane to the patentability of a device itself. Would have been obvious to one skilled in the art at the time of the invention having the first dielectric layer further comprises a prepreg as shown KIM with the circuit board of Chen, since this is commonly done- to provide the required support to the flexible circuit board. Regarding Claim-5, modified Chen does not disclose wherein the prepreg partially or completely covers a surface that is of the flexible dielectric layer and that is close to the second conductive layer, a surface that is of the flexible dielectric layer and that is close to the first conductive layer is closely attached to the first conductive layer, and the prepreg is closely attached to both the flexible dielectric layer and the second conductive layer. However KIM discloses - wherein the prepreg (Fig. 7, 50) partially or completely covers a surface that is of the flexible dielectric layer (Fig. 7, 13) and that is close to the second conductive layer, a surface that is of the flexible dielectric layer and that is close to the first conductive layer is closely attached to the first conductive layer, and the prepreg is closely attached to both the flexible dielectric layer and the second conductive layer (Fig.7, 60). Would have been obvious to one skilled in the art at the time of the invention- the prepreg partially or completely covers a surface that is of the flexible dielectric layer and that is close to the second conductive layer, a surface that is of the flexible dielectric layer and that is close to the first conductive layer is closely attached to the first conductive layer, and the prepreg is closely attached to both the flexible dielectric layer and the second conductive layer as shown by KIM with the circuit board of Chen, since this is commonly done to provide the required support to the flexible circuit board. Regarding Claim-6, modified Chen does not disclose - The printed circuit board according to claim 4, wherein both the surface that is of the flexible dielectric layer and that is close to the first conductive layer and the surface that is of the flexible dielectric layer and that is close to the second conductive layer partially or completely cover the prepreg, and the flexible dielectric layer is closely connected to both the first conductive layer and the second conductive layer by using the prepreg. However, KIM discloses – The printed circuit board according to claim 4, wherein both the surface that is of the flexible dielectric layer and that is close to the first conductive layer and the surface that is of the flexible dielectric layer and that is close to the second conductive layer partially or completely cover the prepreg, and the flexible dielectric layer is closely connected to both the first conductive layer and the second conductive layer by using the prepreg. The printed circuit board according to claim 4, wherein both the surface that is of the flexible dielectric layer and that is close to the first conductive layer and the surface that is of the flexible dielectric layer and that is close to the second conductive layer partially or completely cover the prepreg, and the flexible dielectric layer is closely connected to both the first conductive layer and the second conductive layer by using the prepreg. It would have been obvious to one skilled in the art at the time of the invention- The printed circuit board according to claim 4, wherein both the surface that is of the flexible dielectric layer and that is close to the first conductive layer and the surface that is of the flexible dielectric layer and that is close to the second conductive layer partially or completely cover the prepreg, and the flexible dielectric layer is closely connected to both the first conductive layer and the second conductive layer by using the prepreg. As shown by KIM with the circuit board of Chen, since this is commonly done to provide the required stability to the flexible circuit board. Claim(s) 7 – is/ are rejected under 35 U.S.C. 103 as being unpatentable over Chen [US20180177056] in view of Kariya et.al., US 20070134910 and KIM [US 20220110212] as detailed in Claim rejection four above and further in view of Bagung [US 8624130 B2, Fig. 4, 102, Column-3, Lines 59-66]. Regarding Claim-7, modified Chen does not disclose that - the prepreg is an FR4 prepreg. However, Bagung does disclose that - the prepreg is an FR4 prepreg [Fig. 4, 102, Column-3, Lines 59-66]. Would have been obvious to one skilled in the art at the time of the invention that the prepreg is an FR4 prepreg as shown by Bagung. With the circuit board of Chen, since it is common to use FR4 prepreg for its durability. Claim(s) 9 – is/ are rejected under 35 U.S.C. 103 as being unpatentable over Chen [US20180177056] in view of Kariya et.al., US 20070134910 ss detailed in Claim rejection one above and further in view of YANG [US 12041717 B2]. Regarding Claim-9, modified Chen does not disclose that- wherein a pad is disposed at the first conductive layer, and the flexible dielectric layer is disposed at a position that corresponds to the pad and is at the first dielectric layer. However, Yang discloses that wherein a pad is disposed at the first conductive layer, and the flexible dielectric layer is disposed at a position that corresponds to the pad and is at the first dielectric layer [Fig. 2B, 230]. It would have been obvious to one skilled in the art at the time of the invention to use a pad that is disposed at the first conductive layer, and the flexible dielectric layer is disposed at a position that corresponds to the pad and is at the first dielectric layer as shown by Yang, with the circuit board of modified Chen. This is commonly done to allow the flexible circuit board to be electrically attached to an external component. Claim(s) 1 – is/ are rejected under 35 U.S.C. 103 as being unpatentable over Chen [US20180177056] in view of Kariya et.al., US 20070134910 detailed in Claim rejection one above and further in view of MIN; Tae-Hong [20160192488] Regarding Claim-11, modified Chen doe not discloses - N third conductive layers and M second dielectric layers, the third conductive layers and the second dielectric layers are alternately stacked, M = N + 1, and both N and M are natural numbers; and a part of the M second dielectric layers comprises the flexible dielectric layer; or each of the M second dielectric layers comprises the flexible dielectric layer. However, MIN et al.- discloses- N third conductive layers and M second dielectric layers, the third conductive layers and the second dielectric layers are alternately stacked, M = N + 1, and both N and M are natural numbers; and a part of the M second dielectric layers comprises the flexible dielectric layer; or each of the M second dielectric layers comprises the flexible dielectric layer [Fig. 2, 111 (insulating), 112 (metal), 113 (metal), 114 (insulating, covers the both the top and bottom of the substrate)] additionally MIN -discloses the substrate has improved Heat dissipating capability [Paragraph 11]. It would have been obvious to one skilled in the art at the time of the invention to use - N third conductive layers and M second dielectric layers, the third conductive layers and the second dielectric layers are alternately stacked, M = N + 1, and both N and M are natural numbers; and a part of the M second dielectric layers comprises the flexible dielectric layer; or each of the M second dielectric layers comprises the flexible dielectric layer as shown by NIM, with the circuit board of Chen, since this is commonly done for improved heat dissipating capability. Claim(s) 12 and 13 – are rejected under 35 U.S.C. 103 as being unpatentable over Chen [US20180177056] in view of Kariya et.al., US 20070134910 detailed in Claim rejection one above and further in view of Anderson et al., [US 5527998 A, Claim#37]. Regarding Claim-12 and 13, modified Chen does not disclose that- wherein a coefficient of thermal expansion (CTE) of the flexible dielectric layer in an X-axis direction and a Y-axis direction is less than or equal to a preset threshold, whereas preset threshold is less than or equal to 30. However, Anderson et al., discloses- a coefficient of thermal expansion (CTE) of the flexible dielectric layer in an X-axis direction and a Y-axis direction is less than or equal to a preset threshold, whereas preset threshold is less than or equal to 30- Anderson et al., [US 5527998 A, Claim#37] Anderson discloses coefficient of thermal expansion (CTE) at all of the metal traces & insulating layers needs to be roughly the same, since we know that modifies Chen uses Cupper metal traces, and we know the CTE for Cu- is 16.5. Thus, we want to select insulating layer’s CTE is 16.5, which is less than 30. It would have been obvious to one skilled in the art at the time of the invention that - a coefficient of thermal expansion (CTE) of the flexible dielectric layer in an X-axis direction and a Y-axis direction is less than or equal to a preset threshold, whereas preset threshold is less than or equal to 30, since this is commonly done for improved heat expansion capability in a flexible printed circuit board (the engineering toolbox, www.engineeringtoolbox.com states that Cu- has a coefficient of thermal expansion (CTE) of 16.5. um\[mk] . Allowable Subject Matter Claim-10 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Any inquiry concerning this communication or earlier communications from the examiner should be directed to OBAIDUL GANI whose telephone number is (571)272-8665. The examiner can normally be reached Mon-Fri: 7:30 - 5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. OBAIDUL GANI Examiner Art Unit 2847 /TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
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Prosecution Timeline

Dec 29, 2023
Application Filed
Mar 05, 2026
Non-Final Rejection — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
Grant Probability
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 0 resolved cases by this examiner. Grant probability derived from career allow rate.

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