DETAILED ACTION
This action is responsive to: the amendment filed October 23, 2025. Claims 1 – 20 are pending. Claims 1, 13, and 18 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Arguments
Applicant's arguments filed December 30, 2025 have been fully considered but they are not persuasive.
Applicant argues their claim 1 has a limitation such as “using different driving strengths during the same period as generally required by amended claim 1…” Applicant’s arguments are not persuasive. Kim, in figure 7 and paragraph 70, shows/mentions the period could be different indicating it could be the same as well. The 103 rejection of claim 1 is maintained.
It is recommended that the applicant explain the patentable difference between the applicant’s recovery driver and Kim’s recovery driver. Also, ensure that any other patentably distinct feature is made noticeable.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 9, 13-14, and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 9165660) in view of Kim et al. (US 20180211709).
Regarding independent claim 1, Lee teaches a non-volatile memory device (Fig. 1: 100) comprising:
a memory block (Fig. 1: e.g., BLK1) including
a plurality of cell strings (Fig. 3: CS) including
a plurality of string selection transistors (Fig. 3: SST) and
a plurality of memory cells (Fig. 3: MC),
a first-string selection line (Fig. 3: SSL1) connected to a string selection transistor (Fig. 3: SST) of a first cell string (Fig. 3: CS11) of the plurality of cell strings (Fig. 3: CS), and
a second-string selection line (Fig. 1: SSL2) connected to a string selection transistor (Fig. 3 SST) of a second cell string (Fig. 3: CS21) of the plurality of cell strings (Fig. 3: CS); and
a control circuit (Fig. 1: 150) configured to control a recovery operation (see col. 2, lines 16 - 33) to apply a recovery voltage (Fig. 1: 130) to the first-string selection line (Fig. 3: SSL1) and the second-string selection line (Fig. 3: SSL2) in a recovery period (Fig. 7 showing different drive strengths, also see paragraph 70).
Lee does not teach:
The control circuit to control the recovery voltage applied to the first- and second-string selection transistors to have “different drive strengths”.
However, Kim teaches a control logic circuit (Fig. 1:120) that permits adjusting the voltages applied to the first- and second-string selection transistors such that the applied voltages have different driving strengths (see para. 82).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lee’s apparatus with Kim’s control logic circuitry for the purpose of preventing or reducing read disturb deterioration, and recovery methods of the non-volatile memory devices.
Regarding claim 2, Lee and Kim teach the limitations of claim 1.
Lee further teaches wherein:
the first-string selection line (Fig. 3: SSL1) and the second-string selection line (Fig. 3: SSL2);
Kim further teaches string selection lines (Fig. 3: SSL) have different RC values (Fig. 7: wlrcv, see para. 72).
Regarding claim 3, Lee and Kim teach the limitations of claim 1.
Kim further teaches wherein:
based on an RC value (Fig. 7: wlrcv, see para. 72) of the first-string selection line (Fig. 3: SSL) being greater than an RC value (Fig. 7: wlrcv, see para. 72) of the second-string selection line (Fig. 3: SSL), the recovery operation (see para. 32) is controlled to apply the recovery voltage (Fig. 1: 122) to the first-string selection line (Fig. 3: SSL) with a stronger drive strength (Fig. 1: 132, see para. 82) than a drive strength (Fig. 1: 132, see para. 82) for applying the recovery voltage (Fig. 1: 122) to the second-string selection line (Fig. 3: SSL).
Regarding claim 9, Lee and Kim teach the limitations of claim 1.
Lee further teaches, wherein:
the plurality of cell strings (Fig. 3: CS) further comprise a plurality of ground selection transistors (Fig. 3: GST),
the memory block (Fig. 1: 110) comprises a first ground selection line (Fig. 3: GSL) connected to a first ground selection transistors (Fig. 3: GST) of the plurality of ground selection transistors (Fig. 3: GSTs) and a second ground selection line (Fig. 3: GSL) connected to second ground selection transistors (Fig. 3: GSTs) of the plurality of ground selection transistors (Fig. 3: GSTs), and
the control circuit (Fig. 1: CTRL) is further configured to determine application timing (Fig. 4: Time) of the recovery voltage (Fig. 1: 130) to the first ground selection line (Fig. 3: GSL) and the second ground selection line (Fig. 3: GSL) based on a voltage of at least one of the first ground selection line (Fig. 3: GSL) and the second ground selection line (Fig. 3: GSL).
Regarding independent claim 13, Lee teaches a recovery method of a non-volatile memory device (Fig. 1: 100) that includes a plurality of cell strings (Fig. 3: CS) including a plurality of string selection transistors (Fig. 3: SST) and a plurality of memory cells (Fig. 3: MC), comprising:
applying a string selection turn-on voltage (Fig. 4: VON1) to a first-string selection line (Fig. 3: SSL1) connected to a string selection transistor (Fig. 3: SST) of a first cell string (Fig. 3: CS11) of the plurality of cell strings (Fig. 3: CS), and
applying a string selection turn-off voltage (Fig. 4: VOFF) to a second-string selection line (Fig. 1: SSL2) connected to a string selection transistor (Fig. 3: SST) of a second cell string (Fig. 3: CS21) of the plurality of cell strings (Fig. 3: CS);
applying the string selection turn-on voltage (Fig. 4: VON1) to the first-string selection line (Fig. 3: SSL1) and the second-string selection line (Fig. 1: SSL2);
counting a period of a voltage of the first-string selection line (Fig. 3: SSL1) being less than or equal to a first reference voltage (Fig. 4: VSS); and
applying a recovery voltage (Fig. 1: 130, see col 2. Lines 25-33) to the first-string selection line (Fig. 3: SSL1) and the second-string selection line (Fig. 1: SSL2) based on a time length (Fig. 4: Time) of the period in a recovery period (Fig. 7 showing different drive strengths, also see paragraph 70).
Lee does not teach:
“Different drive strengths.”
However, Kim teaches:
different drive strengths (see para. 82).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lee’s apparatus with Kim’s control logic circuitry for the purpose of preventing or reducing read disturb deterioration, and recovery methods of the non-volatile memory devices.
Regarding claim 14, Lee and Kim teach the limitations of claim 13.
Lee further teaches wherein:
the applying the recovery voltage (Fig. 1: 130) comprises
based on the time length (Fig. 4: Time) of the period being longer than a time length (Fig. 4: Time),
Kim further teaches determining a first drive strength (Fig. 1: 132, see para. 82) for applying the recovery voltage (Fig. 1: 122) to the first-string selection line (Fig. 3: SSL) to be greater than a second drive strength (Fig. 1: 132, see para. 82) for applying the recovery voltage (Fig. 1: 122) to the second-string selection line (Fig. 3: SSL), and
applying the recovery voltage (Fig. 1: 122) with the first drive strength (Fig. 1: 132, see para. 82) to the first-string selection line (Fig. 3: SSL) and applying the recovery voltage (Fig. 1: 122) with the second drive strength (Fig. 1: 132, see para. 82) to the second-string selection line (Fig. 3: SSL).
Regarding claim 16, Lee and Kim teach the limitations of claim 13.
Lee further teaches wherein:
the plurality of cell strings (Fig. 3: CS) further comprises a plurality of ground selection transistors (Fig. 3: GST), and
the recovery method (Fig. 1: 130, see col. 2, lines 16 - 33) of the non-volatile memory device (Fig. 1: 100) further comprises:
applying a ground selection turn-on voltage (Fig. 4: VON4) to a first ground selection line (Fig. 3: GSL) connected to first ground selection transistors (Fig. 3: GST) of the plurality of ground selection transistors (Fig. 3: GST) and applying a ground selection turn-off voltage (Fig. 4: VSS) to a second ground selection line (Fig. 3: GSL) connected to second ground selection transistors (Fig. 3: GST) of the plurality of ground selection transistors (Fig. 3: GST);
applying the ground selection turn-on voltage (Fig. 4: VON4) to the first ground selection line (Fig. 3: GSL) and the second ground selection line (Fig. 3: GSL); and
applying the recovery voltage (Fig. 1: 130) to the first ground selection line (Fig. 3: GSL) and the second ground selection line (Fig. 3: GSL) based on a voltage of the first ground selection line (Fig. 3: GSL) being a same voltage as a second reference voltage (Fig. 4: VSS).
Regarding claim 17, Lee and Kim teach the limitations of claim 16.
Lee further teaches wherein:
the applying the recovery voltage (Fig. 1: 130) to the first ground selection line (Fig. 3: GSL) and the second ground selection line (Fig. 3: GSL) and the applying the recovery voltage (Fig. 1: 130);
Kim further teaches different drive strengths (Fig. 1: 132, see para. 82),
Lee further teaches to the first-string selection line (Fig. 3: SSL1) and the second-string selection line (Fig. 3: SSL2) are performed when the voltage of the first ground selection line (Fig. 3: GSL) is same as the second reference voltage (Fig. 4: VSS).
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Regarding independent claim 18, Lee teaches a semiconductor device (Fig. 2) comprising:
a substrate (Fig. 2: SUB);
a stacking structure (Fig. 2: BLK1) that includes a plurality of first selection gate electrodes (Fig. 2: Gate Electrode Layer) and a plurality of memory gate electrodes (Examiner’s Mark up, Fig. 2: Memory Gate Electrodes) stacked at a distance from each other on the substrate (Fig. 2: SUB);
a first channel structure (Fig. 7: CH1) that penetrates the stacking structure (Fig. 2: BLK1) and extends in a first direction (Examiner’s Mark up, Fig. 2: 1st Direction);
an insulation pattern (Fig. 2: Insulation Layer) on the stacking structure (Fig. 2: BLK1) and covers the first channel structure (Fig. 7: CH1);
a conductive pattern (Fig. 2: Information Storage Layer) that penetrates the insulation pattern (Fig. 2: Insulation Layer) and is connected with the first channel structure (Fig. 7: CH1);
a plurality of second selection gate electrodes (Fig. 2: Gate Electrode Layer) on the conductive pattern (Fig. 2: Information Storage Layer); and
a plurality of second channel structures (Fig. 7: CH2) that penetrate the plurality of second selection gate electrodes (Fig. 2: Gate Electrode Layer) and extend in the first direction (Examiner’s Mark up, Fig. 2: 1st Direction) and thus widths of the plurality of second selection gate electrodes (Fig. 2: Gate Electrode Layer) in a second direction (Examiner’s Mark up, Fig. 2: 2nd Direction) that crosses the first direction (Examiner’s Mark up, Fig. 2: 1st Direction) are different from each other,
wherein the plurality of second selection gate electrodes (Fig. 2: Gate Electrode Layer) are applied with a same voltage.
Lee does not teach: “different drive strengths in a recovery period (Fig. 7 showing different drive strengths, also see paragraph 70).”
However, Kim teaches:
Different drive strengths (see para. 82).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lee’s apparatus with Kim’s control logic circuitry for the purpose of preventing or reducing read disturb deterioration, and recovery methods of the non-volatile memory devices.
Regarding claim 19, Lee and Kim teach the limitations of claim 18.
Kim further teaches wherein:
a drive strength (Fig. 1: 132, see para. 82) for applying a voltage (see para. 82, referencing VSSL) to;
Lee further teaches: a second selection gate electrode (Fig. 2: Gate Electrode Layer) with a smaller width in the second direction (Examiner’s Mark up, Fig. 2: 2nd Direction) among the plurality of second selection gate electrodes (Fig. 2: Gate Electrode Layer) is stronger than;
Kim further teaches: a drive strength (Fig. 1: 132, see para. 82) for applying the voltage (see para. 82, referencing VSSL) to;
Lee further teaches: a second selection gate electrode (Fig. 2: Gate Electrode Layer) with a larger width in the second direction (Examiner’s Mark up, Fig. 2: 2nd Direction) among the plurality of second selection gate electrodes (Fig. 2: Gate Electrode Layer).
Regarding claim 20, Lee and Kim teach the limitations of claim 18.
Lee further teaches wherein:
an application timing (Fig. 4: Time) of a voltage to the plurality of first selection gate electrodes (Fig. 2: Gate Electrode Layer) is controlled based on a voltage of one of the plurality of first selection gate electrode (Fig. 2: Gate Electrode Layer) of which the voltage is boosted (Fig. 7: Boosting) among the plurality of first selection gate electrodes (Fig. 2: Gate Electrode Layer).
Claims 4-5, and 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 9165660) in view of Kim et al. (US 20180211709) and Seong et al. (US 20150109840).
Regarding claim 4, Lee and Kim teach the limitations of claim 1.
Lee further teaches:
further comprising the first-string selection line (Fig. 3: SSL1) and the second-string selection line (Fig. 3: SSL2), wherein the control circuit (Fig. 1: CTRL);
Kim further teaches the control circuit (Fig. 1 CTRL) configured to determine the drive strengths (Fig. 1: 132, see para. 82).
Lee and Kim do not teach:
“at least one voltage detector configured to detect at least one voltage.”
However, Seong teaches:
a voltage detector (Fig. 1: 700) configured to detect at least one voltage (See para. 47).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lee’s apparatus, Kim’s control circuitry with the different driving strengths, and Seong’s voltage detector for the purpose of preventing or reducing, and detecting read disturb deterioration, and recovery methods of the non-volatile memory devices.
Regarding claim 5, Lee, Kim and Seong teach the limitations of claim 4.
Lee further teaches:
further comprising a voltage generator (Fig. 1: 130) configured to generate a string selection turn-on voltage (Fig. 4: VON1), a string selection turn-off voltage (Fig. 4: VOFF), and the recovery voltage (Fig. 1: 130), wherein a selected string selection line (Fig. 4: Selected SSL) to which the string selection turn-on voltage (Fig. 4: VON1) is provided among the first-string selection line (Fig. 3: SSL1) and the second-string selection line (Fig. 3: SSL2).
Seong further teaches:
the voltage detector (Fig. 1: 700) is further configured to detect a voltage (See para. 47).
Regarding claim 10, Lee and Kim teach the limitations of claim 9.
Lee further teaches:
further comprising one of the first ground selection line (Fig. 3: GSL) and the second ground selection line (Fig. 3: GSL), wherein the control circuit (Fig. 1: CTRL) is further configured to determine the application timing in response to the voltage of one of the first ground selection line (Fig. 3: GSL) and the second ground selection line (Fig. 3: GSL), which has been boosted among the first ground selection line (Fig. 3: GSL) and the second ground selection line (Fig. 3: GSL) being a same voltage as a reference voltage (Fig. 4: VSS),
Lee and Kim do not teach:
“A voltage detector configured to detect a voltage.”
However, Seong teaches:
A voltage detector (Fig. 1: 700) configured to detect a voltage (see para. 45).
Therefore, it would have been obvious to one ordinary skill in the air before the effective filing date of the claimed invention to combine the teachings of Lee’s apparatus and Kim’s different driving strengths circuitry with Seong’s voltage detector for the purpose of preventing or reducing, and detecting read disturb deterioration, and recovery methods of the non-volatile memory devices.
Regarding claim 11, Lee, Kim, and Seong teach the limitations of claim 10.
Lee further teaches wherein:
the control circuit (Fig. 1: CTRL) is further configured to determine the application timing (Fig. 4: Time) of the recovery voltage (Fig. 1: 130) to the first-string selection line (Fig. 3: SSL1) and the second-string selection line (Fig. 3: SSL2) based on the voltage of at least one of the first ground selection line (Fig. 3: GSL) and the second ground selection line (Fig. 3: GSL).
Regarding claim 12, Lee, Kim and Seong teach the limitations of claim 10.
Lee further teaches wherein:
the memory block (Fig. 1: 110) further comprises a plurality of word lines (Fig. 3: WL) connected to the plurality of memory cells (Fig. 3: MC), and the control circuit (Fig. 1: CTRL) is further configured to determine the application timing (Fig. 4: Time) of the recovery voltage (Fig. 1: 130) to the plurality of word lines (Fig. 3: WL) based on the voltage of at least one of the first ground selection line (Fig. 3: GSL) and the second ground selection line (Fig. 3: GSL).
Allowable Subject Matter
Claims 6-8, and 15 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to dependent claim 6 (as well as further dependent claim 7 and 8), the closest prior art Kim (US 20180211709) and Lee (US 9165660) show 3D NAND flash memory that employ recovery operations, and Kim teach the ability of changing the drive strength of the voltages applied to the string selection lines for the string selection transistors. Further, Seong teach a voltage generator. However, these reference are silent to the specific details of the voltage generator, as claimed, namely: the voltage detector outputs a detection signal that counts a time length of a period in which a voltage of the selected string selection line detected by the voltage detector is less than or equal to a reference voltage in a post pulse period during which the string selected turn-on voltage is provided to an unselected string selection line to which the string selected turn-off voltage is provided, and using the detection signal to determine the drive strength.
With respect to dependent claim 15, the applied prior art Kim (US 20180211709) and Lee (US 9165660) both employ some form of voltage generation, so as to generate a “reference voltage,” however, these references are silent to the details of determining the “first reference voltage” based on the temperature information received from a temperature sensor.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TRACY HAMPTON/ Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/ Supervisory Patent Examiner, Art Unit 2825