Prosecution Insights
Last updated: July 17, 2026
Application No. 18/400,164

QUANTUM CHIP, QUANTUM DEVICE, AND QUANTUM COMPUTER

Non-Final OA §112
Filed
Dec 29, 2023
Priority
Jan 18, 2023 — JP 2023-006126
Examiner
ROLAND, CHRISTOPHER M
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
NEC Corporation
OA Round
1 (Non-Final)
65%
Grant Probability
Favorable
1-2
OA Rounds
7m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 65% — above average
65%
Career Allowance Rate
356 granted / 548 resolved
-3.0% vs TC avg
Strong +22% interview lift
Without
With
+21.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
35 currently pending
Career history
584
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
81.9%
+41.9% vs TC avg
§102
8.2%
-31.8% vs TC avg
§112
9.1%
-30.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 548 resolved cases

Office Action

§112
ETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement Information disclosure statement filed 29 December 2023 has been fully considered. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 9 recites the limitation, “a substrate.” It is unclear whether this substrate is the same as, or distinct from, the previously-recited substrate of claim 1. Allowable Subject Matter Claims 1-8 and 10 are allowed. Claim 9 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. The following is an examiner’s statement of reasons for allowance: The prior art of record fails to teach the quantum chip of claim 1, the quantum device of claim 8, and the quantum computer of claim 10 in the combination of limitations as claimed, noting particularly the limitation, “a periodic structure formed on a surface of the superconducting layer along an outer edge of the substrate.” Koizumi (Japanese Kokai Publication H01-133308, hereinafter Koizumi ‘308) teaches a superconducting layer (2); and an electrode (3) formed on a surface of the superconducting layer along an outer edge. However, Koizumi ‘308 is silent to a periodic structure formed on a surface of the superconducting layer along an outer edge of the substrate as claimed. Yamazaki (US Patent 5,596,206) and Coombs (US Patent Application Publication 2008/0252404) are similar references suffering from a similar deficiency. Hato (US Patent Application Publication 2004/0223380) teaches a quantum superconducting chip, but also fails to teach or suggest a periodic structure formed on a surface of the superconducting layer along an outer edge of the substrate as claimed. Dommerque et al. (US Patent Application Publication 2010/0157499, hereinafter Dommerque ‘499) teaches a substrate (1); a superconducting layer (2) formed on a surface of the substrate; an electrode (4) formed along an outer edge of the substrate; and a periodic structure (7) formed along an outer edge of the substrate. However, Dommerque ‘499 is silent to the electrode (4) and the periodic structure (7) being formed on a surface of the superconducting layer as claimed. Nakamura et al. (US Patent Application Publication 2021/0343785) is a similar reference suffering from a similar deficiency. Claims 2-8 and 10 are allowed based merely upon their dependencies from allowed claim 1. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher M. Roland whose telephone number is (571)270-1271. The examiner can normally be reached Monday-Friday, 10:00AM-7:00PM Eastern. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at (571)270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /C.M.R./Examiner, Art Unit 2893 /YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Dec 29, 2023
Application Filed
Jun 25, 2026
Non-Final Rejection mailed — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12677413
ONE-TIME PROGRAMMABLE (OTP) SEMICONDUCTOR DEVICE
3y 11m to grant Granted Jul 07, 2026
Patent 12672362
AVALANCHE PHOTODIODES AND METHODS OF MAKING THE SAME
3y 10m to grant Granted Jun 30, 2026
Patent 12672480
DOUBLE-GATE CARBON NANOTUBE TRANSISTOR
2y 10m to grant Granted Jun 30, 2026
Patent 12660351
IMAGE SENSOR COMPRISING DEEP DEVICE ISOLATION PATTERN
3y 10m to grant Granted Jun 16, 2026
Patent 12660213
CAPACITOR COMPRISING ANTI-FERROELECTRIC LAYERS AND HIGH-K DIELECTRIC LAYERS
2y 0m to grant Granted Jun 16, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
65%
Grant Probability
86%
With Interview (+21.5%)
3y 2m (~7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 548 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month