DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP § 2123.
Claim Status
Claims 1-20 are currently pending. Claims 1 and 11 are amended as per Applicant’s amendment filed 22 December 2025. This office action is in response to a request for continued examination and amendments filed on 22 December 2025.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 22 December 2025 has been entered.
Response to Arguments
Applicant's arguments filed 22 December 2025 have been fully considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
With regards to Applicant’s arguments on page 9, in essence, “Applicant will file a Terminal Disclaimer when all other issues are overcome”. Examiner once again reminds Applicant of the following: A complete response to a nonstatutory double patenting (NSDP) rejection is either a reply by applicant showing that the claims subject to the rejection are patentably distinct from the reference claims or the filing of a terminal disclaimer in accordance with 37 CFR 1.321 in the pending application(s) with a reply to the Office action (see MPEP § 1490 for a discussion of terminal disclaimers). Such a response is required even when the nonstatutory double patenting rejection is provisional. As filing a terminal disclaimer, or filing a showing that the claims subject to the rejection are patentably distinct from the reference application’s claims, is necessary for further consideration of the rejection of the claims, such a filing should not be held in abeyance. Only objections or requirements as to form not necessary for further consideration of the claims may be held in abeyance until allowable subject matter is indicated. see MPEP § 804
The amended claims are addressed in the rejections below further in view of Steinmetz-B (US 20220334740 A1).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12169436. Although the claims at issue are not identical, they are not patentably distinct from each other because they recite substantially similar subject matter and the limitations of the Patent/Copending Application would anticipate those of the current application as shown in the example claims in the table below.
Current Application
U.S. Patent No. 12169436
1. A method of operation of a computing system comprising: in a Non-Volatile Random Access Memory module (NVRAM) having a non-volatile device, a volatile memory device with data, a non-volatile controller unit, and a serial host interface, the method comprising:
receiving a request for data on the serial host interface wherein the serial host interface is configured to provide both block access and byte access to the volatile memory device and wherein the byte access is provided via a Compute Express Link (CXL) protocol multiplexed over a Peripheral Component Interconnect Express (PCIe) physical layer;
providing the requested data, from the volatile memory device with data, on the serial host interface;
detecting a disruptive volatile memory event;
copying the data of the volatile memory device to the non-volatile device through the serial host interface based on the disruptive volatile memory event; and
restoring the data to the volatile memory device from the non-volatile device through the serial host interface.
11. A computing system comprising: a Non-Volatile Random Access Memory module (NVRAM) having a non-volatile device, a volatile memory device with data, a non-volatile controller unit, and a serial host interface;
the non-volatile controller unit configured to:
receive a request for data on the serial host interface wherein the serial host interface is configured to provide both block access and byte access to the volatile memory device and wherein the byte access is provided via a Compute Express Link (CXL) protocol multiplexed over a Peripheral Component Interconnect Express (PCIe) physical layer;;
provide the requested data, from the volatile memory device with data, on the serial host interface;
detect a disruptive volatile memory event;
copy the data of the volatile memory device to the non-volatile device through the serial host interface based on the disruptive volatile memory event; and
restore the data of the volatile memory device from the non-volatile device through the serial host interface.
1. A method of operation of a computing system comprising: in a Non-Volatile Random Access Memory module (NVRAM) having a non-volatile device, a volatile memory device with data, a non-volatile controller unit, and a serial host interface, the method comprising:
receiving a request for data on the serial host interface;
providing the requested data, from the volatile memory device with data, on the serial host interface;
detecting a disruptive volatile memory event; copying the data of the volatile memory device to the non-volatile device based on the disruptive volatile memory event; and
restoring the data to the volatile memory device from the non-volatile device;
where providing the requested data comprises providing the requested data with byte access on the serial host interface.
4. The method as claimed in claim 1 wherein the serial host interface comprises a Peripheral Component Interconnect Express (PCIe) interface.
5. The method as claimed in claim 1 wherein the serial host interface comprises a Compute Express Link (CXL) interface.
11. A computing system comprising: a Non-Volatile Random Access Memory module (NVRAM) having a non-volatile device, a volatile memory device with data, a non-volatile controller unit, and a serial host interface;
the non-volatile controller unit configured to:
receive a request for data on the serial host interface;
provide the requested data, from the volatile memory device with data, on the serial host interface;
detect a disruptive volatile memory event;
copy the data of the volatile memory device to the non-volatile device based on the disruptive volatile memory event; and
restore the data of the volatile memory device from the non-volatile device;
where providing the requested data comprises providing the requested data with byte access on the serial host interface.
14. The computing system as claimed in claim 11 wherein the serial host interface comprises a Peripheral Component Interconnect Express (PCIe) interface.
15. The computing system as claimed in claim 11 wherein the serial host interface comprises a Compute Express Link (CXL) interface.
A complete response to a nonstatutory double patenting (NSDP) rejection is either a reply
by applicant showing that the claims subject to the rejection are patentably distinct from the
reference claims or the filing of a terminal disclaimer in accordance with 37 CFR 1.321 in the
pending application(s) with a reply to the Office action (see MPEP § 1490 for a discussion of
terminal disclaimers). Such a response is required even when the nonstatutory double
patenting rejection is provisional. As filing a terminal disclaimer, or filing a showing that the
claims subject to the rejection are patentably distinct from the reference application’s
claims, is necessary for further consideration of the rejection of the claims, such a filing
should not be held in abeyance. Only objections or requirements as to form not necessary for
further consideration of the claims may be held in abeyance until allowable subject matter is
indicated. see MPEP § 804
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Steinmetz (US 20220197833 A1) in view of Nachimuthu (US 20190243637 A1) and further in view of Steinmetz-B (US 20220334740 A1).
Referring to claims 1 and 11, taking claim 11 as exemplary, Steinmetz teaches
A computing system comprising: a Non-Volatile Random Access Memory module (NVRAM) having a non-volatile device, ([Steinmetz 0022, 0030, Fig. 1] A memory sub-system 110 can be a storage device, a memory module, or a combination of a storage device and memory module. Examples of memory modules include a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), and various types of non-volatile dual in-line memory modules (NVDIMMs). non-volatile memory components such as a 3D cross-point array of non-volatile memory cells and NAND type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide based memories, ferroelectric transistor random-access memory (FeTRAM), ferroelectric random access memory (FeRAM), magneto random access memory (MRAM), Spin Transfer Torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide based RRAM (OxRAM), negative-or (NOR) flash memory, or electrically erasable programmable read-only memory (EEPROM)) a volatile memory device with data, ([Steinmetz 0021, Fig. 1] The memory sub-system 110 can include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such) a non-volatile controller unit, ([Steinmetz 0031] A memory sub-system controller 115 (or controller 115 for simplicity) can communicate with the memory devices 130 to perform operations such as reading data, writing data, or erasing data at the memory devices 130 and other such operations) and a serial host interface; ([Steinmetz 0034, 0039, 0041] The memory sub-system controller 115 can further include host interface circuitry to communicate with the host system 120 via the physical host interface, including PCIe and CXL (both known serial interfaces) ) the non-volatile controller unit configured to: receive a request for data on the serial host interface; ([Steinmetz 0015, 0034] The memory sub-system controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. One example of such a logical-device interface for accessing a memory device is Non-Volatile Memory Express (NVMe). A host system (“host”) can access the memory sub-system via, e.g., a Peripheral Component Interconnect Express (PCIe) bus, and the access to the memory device(s) of the memory sub-system can be referred to herein as PCIe NVMe) provide the requested data, from the volatile memory device with data, on the serial host interface; ([Steinmetz 0015] A host system (“host”) can access the memory sub-system via, e.g., a Peripheral Component Interconnect Express (PCIe) bus, and the access to the memory device(s) of the memory sub-system can be referred to herein as PCIe NVMe. More specifically, the memory sub-system (e.g., SSD) can include a storage element and a persistent memory region (PMR). For example, the storage element can include a block storage element. A PMR corresponds an area of readable persistent memory implemented as a power protected volatile memory device (e.g., power protected dynamic random-access memory (DRAM)). More specifically, the PMR can be a byte-addressable memory region accessible through a base address register (BAR). An NVMe SSD connected memory device can include a PMR, with such a device being referred to as an NVMe SSD device with PMR.) detect a disruptive volatile memory event; ([Steinmetz 0044, 0062] write data in response to a power loss event) copy the data of the volatile memory device to the non-volatile device through the serial host interface based on the disruptive volatile memory event; ([Steinmetz 0015, 0018-0019, 0044] The PMR can be implemented as a power protected region on the volatile memory device, enable the PMR to write data in response to a power loss event. More specifically, the PMR memory region(s) can be written to non-volatile memory (e.g., SSD NAND). Where the memory sub-system (e.g., SSD) can include a storage element and a persistent memory region (PMR) and access the memory sub-system via, e.g., a Peripheral Component Interconnect Express (PCIe) bus or the underlying interface standard is compute express link (CXL) (both known serial interfaces)).
Steinmetz does not explicitly disclose wherein the serial host interface is configured to provide both block access and byte access to the volatile memory device and wherein the byte access is provided via a Compute Express Link (CXL) protocol multiplexed over a Peripheral Component Interconnect Express (PCIe) physical layer and restore the data of the volatile memory device from the non-volatile device through the serial host interface. Steinmetz does disclose accessing the memory sub-system, the persistent memory region (PMR), via, e.g., a Peripheral Component Interconnect Express (PCIe) bus or the underlying interface standard compute express link (CXL) (both known serial interfaces) ([Steinmetz 0015, 0018-0019]).
Nachimuthu teaches and restore the data of the volatile memory device from the non-volatile device through the serial host interface ([Nachimuthu 0044, 0088] the process 500 restores the volatile data, including the volatile passphrase and keys as needed if the persistent memory module's power cycle count has not changed.).
Steinmetz and Nachimuthu are analogous art because they are from the same field of endeavor in storage systems. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Steinmetz and Nachimuthu before him or her to modify the persistent memory region (PMR) of Steinmetz to include the data restoration of Nachimuthu, thereafter the PMR is connected to data restoration and accessed vis the PCIe/CXL interface. The suggestion and/or motivation for doing so would be obtaining the advantage of allowing the PMR have more traditional persistent storage capability and provide both a backup and restore capability for the volatile data as suggested by Nachimuthu. It is known to combine prior art elements according to known methods to yield predictable results. Therefore, it would have been obvious to combine Steinmetz with Nachimuthu to obtain the invention as specified in the instant application claims.
Steinmetz in view of Nachimuthu does not explicitly disclose wherein the serial host interface is configured to provide both block access and byte access to the volatile memory device and wherein the byte access is provided via a Compute Express Link (CXL) protocol multiplexed over a Peripheral Component Interconnect Express (PCIe) physical layer. Steinmetz does disclose accessing the memory sub-system, the persistent memory region (PMR), via, e.g., a Peripheral Component Interconnect Express (PCIe) bus or the underlying interface standard compute express link (CXL) (both known serial interfaces) ([Steinmetz 0015, 0018-0019, 0044]).
Steinmetz-B teaches wherein the serial host interface is configured to provide both block access and byte access to the volatile memory device and wherein the byte access is provided via a Compute Express Link (CXL) protocol multiplexed over a Peripheral Component Interconnect Express (PCIe) physical layer ([Steinmetz-B 0015, 0017-0019, 0029, 0043-0044, Fig.2] It has become more important to have regions of system-exposed byte addressable memory alongside the block storage element for a variety of implementations or use cases that can make use of transaction oriented persistent memory, and modern application reliance on transaction consistency has grown significantly. The host system 120 can be coupled to the memory sub-system 110 via a physical host interface. Examples of a physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface. A memory sub-system, such as a solid-state drive (SSD), can be accessed by a logical-device interface attached via a bus. One example of such a logical-device interface for accessing a memory device is Non-Volatile Memory Express (NVMe). A host system (“host”) can access the memory sub-system via, e.g., a Peripheral Component Interconnect Express (PCIe) bus, and the access to the memory device(s) of the memory sub-system can be referred to herein as PCIe NVMe. More specifically, the memory sub-system (e.g., SSD) can include a storage element and a persistent memory region (PMR). For example, the storage element can include a block storage element. A PMR corresponds an area of readable persistent memory. As one example, the PMR can be implemented as a power protected region on a volatile memory device of the memory sub-system. Here, the volatile memory device can include a Dynamic Random-Access Memory (DRAM) device. More specifically, the DRAM device can be a Double Data Rate Synchronous Dynamic Random-Access Memory (DDR) device. As another example, the PMR can be implemented on a native non-volatile memory device, such as magnetic RAM (MRAM) or other similar non-volatile memory device. More specifically, the PMR can be a byte-addressable memory region accessible through a base address register (BAR). In some embodiments, the memory sub-system is an NVMe SSD including a PMR, with such a device being referred to as an NVMe SSD device with PMR. The memory sub-system can implement any suitable interface standard in accordance with the embodiments described herein. In some embodiments, the interface standard is PCIe. In some embodiments, the interface standard is compute express link (CXL). The PMR can be exposed by any suitable interface standard in accordance with the embodiments described herein (e.g., PCIe and/or CXL).).
Steinmetz, Nachimuthu, and Steinmetz-B are analogous art because they are from the same field of endeavor in storage systems. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Steinmetz, Nachimuthu, and Steinmetz-B before him or her to modify the persistent memory region (PMR) of Steinmetz and Nachimuthu to include the exposing the PMR via PCIe and/or CXL of Steinmetz-B, thereafter the PMR is connected to and accessed via the PCIe/CXL interface. The suggestion and/or motivation for doing so would be obtaining the advantage of allowing the PMR to be exposed by any suitable interface standard in accordance with the embodiments described herein (e.g., PCIe and/or CXL) as suggested by Steinmetz-B. It is known to combine prior art elements according to known methods to yield predictable results. Therefore, it would have been obvious to combine Steinmetz and Nachimuthu with Steinmetz-B to obtain the invention as specified in the instant application claims.
As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above.
Referring to claims 2 and 12, taking claim 12 as exemplary, Steinmetz in view of Nachimuthu and Steinmetz-B teaches
The computing system as claimed in claim 11 wherein the non-volatile device comprises one or more of the group consisting of: a NAND Flash device, a Phase Change Memory (PCM), Resistive Random Access Memory (RERAM), Magnetoresistive Random Access Memory (MRAM), and Nano Random Access Memory (NRAM) ([Steinmetz 0017, 0030] Although non-volatile memory components such as a 3D cross-point array of non-volatile memory cells and NAND type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide based memories, ferroelectric transistor random-access memory (FeTRAM), ferroelectric random access memory (FeRAM), magneto random access memory (MRAM), Spin Transfer Torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide based RRAM (OxRAM), negative-or (NOR) flash memory, or electrically erasable programmable read-only memory (EEPROM)).
As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above.
Referring to claims 3 and 13, taking claim 13 as exemplary, Steinmetz in view of Nachimuthu and Steinmetz-B teaches
The computing system as claimed in claim 11 wherein the volatile memory device with data comprises a Dynamic Random-Access Memory (DRAM) device ([Steinmetz, 0017] the volatile memory device can include DRAM).
As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above.
Referring to claims 4 and 14, taking claim 14 as exemplary, Steinmetz in view of Nachimuthu and Steinmetz-B teaches
The computing system as claimed in claim 11 wherein the serial host interface comprises a Peripheral Component Interconnect Express (PCIe) interface ([Steinmetz 0015, 0018-0019] access the memory sub-system via, e.g., a Peripheral Component Interconnect Express (PCIe) bus, and the access to the memory device(s) of the memory sub-system can be referred to herein as PCIe NVMe.).
As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above.
Referring to claims 5 and 15, taking claim 15 as exemplary, Steinmetz in view of Nachimuthu and Steinmetz-B teaches
The computing system as claimed in claim 11 wherein the serial host interface comprises a Compute Express Link (CXL) interface ([Steinmetz 0018-0019] the underlying interface standard is compute express link (CXL)).
As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above.
Referring to claims 6 and 16, taking claim 16 as exemplary, Steinmetz in view of Nachimuthu and Steinmetz-B teaches
The computing system as claimed in claim 11 wherein the serial host interface comprises one (see rejection above).
Steinmetz does not explicitly disclose or more of the group consisting of: an OpenCAPI Memory Interface (OMI); a Cache Coherent Interconnect for Accelerators (CCIX) interface; and a Gen-Z interface.
Nachimuthu teaches or more of the group consisting of: an OpenCAPI Memory Interface (OMI); a Cache Coherent Interconnect for Accelerators (CCIX) interface; and a Gen-Z interface ([Nachimuthu 0029] The memory interface to the persistent memory modules 214 can be any compatible interface, such as the DDR-T, Compute Express Link (CXL), Cache Coherent Interconnect for Accelerators (CCIX) and Gen-Z memory interfaces.).
Steinmetz and Nachimuthu are analogous art because they are from the same field of endeavor in storage systems. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Steinmetz and Nachimuthu before him or her to modify the interfaces of Steinmetz to include the interfaces of Nachimuthu, thereafter the interfaces are connected. The suggestion and/or motivation for doing so would be obtaining the advantage of allowing the interfaces to support the varied protocols used in modern day storage devices as suggested by Nachimuthu. It is known to combine prior art elements according to known methods to yield predictable results. Therefore, it would have been obvious to combine Steinmetz with Nachimuthu to obtain the invention as specified in the instant application claims.
As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above.
Referring to claims 7 and 17, taking claim 17 as exemplary, Steinmetz in view of Nachimuthu and Steinmetz-B teaches
The computing system as claimed in claim 11 wherein detecting the disruptive volatile memory event comprises detecting a power loss event ([Steinmetz 0044, 0062] The PMR can be implemented as a power protected region on the volatile memory device using any suitable mechanism(s) in accordance with the embodiments described herein. For example, the PMR can be implemented as a power protected region on the volatile memory device by employing backup capacitors. Such backup capacitors can store charge that can be used to enable the PMR to write data in response to a power loss event.).
As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above.
Referring to claims 8 and 18, taking claim 18 as exemplary, Steinmetz in view of Nachimuthu and Steinmetz-B teaches
The computing system as claimed in claim 17 wherein the power loss event is scheduled ([Steinmetz 0020, 0060] One consideration is startup and shutdown. For example, since PMR is persistent, special startup and shutdown (i.e. scheduled power loss) solutions can be provided to synchronize “state” with the host. The host may not be aware of things that are causing the PMR to not be “ready” or available, such as, e.g., power loss or memory degradation.).
As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above.
Referring to claims 9 and 19, taking claim 19 as exemplary, Steinmetz in view of Nachimuthu and Steinmetz-B teaches
The computing system as claimed in claim 17 wherein the power loss event is unscheduled ([Steinmetz 0062] For example, in the event of power loss (i.e. unscheduled event), it can be important to have a mechanism that provides enough time to write any data that is not committed to non-volatile memory. For example, as described above with reference to FIG. 2, backup capacitors can be used to store energy to enable data writes in the event of power loss. In embodiments in which PMR is implemented as a power protected region on a volatile memory device (e.g., DRAM), PMR can rely on mechanisms such as, e.g., capacitors to enable data writes to non-volatile memory (e.g., NAND flash) in the event of power loss. However, a capacitor can degrade over time, and thus negatively affect the ability of the capacitor to provide data write support during a power loss event.).
As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above.
Referring to claims 10 and 20, taking claim 20 as exemplary, Steinmetz in view of Nachimuthu and Steinmetz-B teaches
The computing system as claimed in claim 11 wherein the non-volatile controller unit is further configured to: in response to detecting the disruptive volatile memory event, provide power to the volatile memory device while copying the data of the volatile memory device to the non-volatile device ([Steinmetz 0044, 0062] backup capacitors can be used to store energy to enable data writes in the event of power loss).
As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRANCISCO A GRULLON whose telephone number is (571)272-8318. The examiner can normally be reached Monday - Friday, 9-5.
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/FRANCISCO A GRULLON/Primary Examiner, Art Unit 2132