DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of invention I, claims 1-18, in the reply filed on 01/05/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 8-10, and 15-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mo et al. (U.S. Pub. No. 20130089175).
Regarding claim 1, Mo discloses:
An image sensor device comprising:
a first pixel located at a first row and a first column, corresponding to a first color filter, and configured to output a first pixel signal through a first column line (green Gr pixel (of Bayer pattern) in super pixel 1201 with integration time t0 (on the top left in Fig. 12 super pixels 1201 with integration times t0, t1, t2, and t3 have the shape of a square and each super pixel is considered to have a configuration of two columns and two rows) is readout using column readout line pixout1 and stored in a first arithmetic counter included in a first column parallel ADC, par. 65, 67, 70, 109-113, and Figs. 12 and 14);
a second pixel located at a second row different from the first row and the first column, corresponding to the first color filter, and configured to output a second pixel signal through a second column line (green Gb pixel (of Bayer pattern) in super pixel 1201 with integration time t2, and arranged on a different row than green Gr pixel (on the top left in Fig. 12 super pixels 1201 with integration times t0, t1, t2, and t3 have the shape of a square and each super pixel is considered to have a configuration of two columns and two rows), is readout using column readout line pixout connected to green Gb pixel and stored in an arithmetic counter included in the column parallel ADC connected to the column readout line pixout, par. 65, 67, 70, 109-113, and Figs. 12 and 14); and
a conversion circuit configured to receive the first pixel signal through the first column line, receive the second pixel signal through the second column line, and generate first image data and second image data based on the first pixel signal and the second pixel signal (readout circuitry 102, where image data is readout as an analog voltage level on each readout column to readout circuitry 102, including Analog-to-Digital converters 106, and after amplification, the readout image data is transferred to the function logic 111, which may store the image data or may manipulate the image data by applying post image effects (e.g., crop, rotate remove red eye, adjust brightness, adjust contrast or otherwise), par. 64),
wherein the first pixel signal and the second pixel signal are respectively output through the first column line and the second column line simultaneously (simultaneously image data from a first super pixel 1201 (misstated as 1210 based on par. 109-111) having a t0 integration time is readout and stored in a first arithmetic counter included in a first column parallel ADC and the image data from a third super pixel 1201 (misstated as 1210 based on par. 109-111) having a t2 integration time is readout and stored in a second arithmetic counter included in the second column ADC, par. 112-113 and Figs. 12-14).
Regarding claim 8, Mo further discloses:
a first frame rate corresponding to the first image data is identical to a second frame rate corresponding to the second image data (multiple row concurrent readout, which means identical frame rate, where frame rate is calculated based on different sized pixel array, par. 83-86 and 112-113).
Regarding claim 9, Mo further discloses:
a range expressed by the first image data corresponds to a range expressed by the second image data (super pixel 1201 with integration time t0 is in the same ROW <N-1> as super pixel 1201 with integration time t2 as seen in Fig. 12).
Regarding claim 10, Mo further discloses:
conversion circuit includes:
a switching circuit connected to the first column line and the second column line (MUX circuitry 104, where in order to output multiple rows at a time, control circuitry 220 configures the top and bottom MUX circuitry 104.sub.1 and 104.sub.2, to respectively select alternate column readout lines, par. 89);
a first analog-to-digital converter (ADC) configured to receive one of the first pixel signal and the second pixel signal from the switching circuit and to generate the first image data by sampling the one pixel signal thus received (two analog-to-digital converter ADC 106 are connected through amplification circuitry 105 to MUX circuitry 104, where MUX circuitry 104 is connected to PIXOUT column lines that are in turn connected to super pixels 1201 with t0 and t1 exposure times, and the readout image data is transferred to the function logic 111, par. 64, 89, and Fig. 12); and
a second ADC configured to receive the other of the first pixel signal and the second pixel signal from the switching circuit and to generate the second image data by sampling the other pixel signal thus received (two analog-to-digital converter ADC 106 are connected through amplification circuitry 105 to MUX circuitry 104, where MUX circuitry 104 is connected to PIXOUT column lines that are in turn connected to super pixels 1201 with t2 and t3 exposure times, and the readout image data is transferred to the function logic 111, par. 64, 89, and Fig. 12).
Regarding claim 15, Mo discloses:
An operation method of an image sensor device which includes a plurality of pixel rows, the method comprising:
performing a first readout operation on a first pixel row among the plurality of pixel rows (green Gr pixel (of Bayer pattern) in super pixel 1201 with integration time t0 (on the top left in Fig. 12 super pixels 1201 with integration times t0, t1, t2, and t3 have the shape of a square and each super pixel is considered to have a configuration of two columns and two rows) is readout using column readout line pixout1 and stored in a first arithmetic counter included in a first column parallel ADC, par. 65, 67, 70, 109-113, and Figs. 12 and 14);
performing a second readout operation on a second pixel row different from the first pixel row from among the plurality of pixel rows (green Gb pixel (of Bayer pattern) in super pixel 1201 with integration time t2, and arranged on a different row than green Gr pixel (on the top left in Fig. 12 super pixels 1201 with integration times t0, t1, t2, and t3 have the shape of a square and each super pixel is considered to have a configuration of two columns and two rows), is readout using column readout line pixout connected to green Gb pixel and stored in an arithmetic counter included in the column parallel ADC connected to the column readout line pixout, par. 65, 67, 70, 109-113, and Figs. 12 and 14); and
generating first image data based on first pixel signals output by the first readout operation and generating second image data based on second pixel signals output by the second readout operation (image data is readout as an analog voltage level on each readout column to readout circuitry 102, including Analog-to-Digital converters 106, and after amplification, the readout image data is transferred to the function logic 111, which may store the image data or may manipulate the image data by applying post image effects (e.g., crop, rotate remove red eye, adjust brightness, adjust contrast or otherwise), par. 64),
wherein the first readout operation and the second readout operation are simultaneously performed (simultaneously image data from a first super pixel 1201 (misstated as 1210 based on par. 109-111) having a t0 integration time is readout and stored in a first arithmetic counter included in a first column parallel ADC and the image data from a third super pixel 1201 (misstated as 1210 based on par. 109-111) having a t2 integration time is readout and stored in a second arithmetic counter included in the second column ADC, par. 112-113 and Figs. 12-14).
Regarding claim 16, Mo further discloses:
second readout operation on the second pixel row is performed with respect to some of a plurality of pixels included in the second pixel row (pixels from super pixel 1201 with integration time T2 are read out before pixels from super pixel 1201 with integration time T3, par. 113-115 and Figs. 12 and 14).
Regarding claim 17, Mo further discloses:
first readout operation is performed once for each of the plurality of pixel rows, the second readout operation on the second pixel row is performed at least two times (multiple row concurrent readout and read out at a frame rate calculated based on different sized pixel array, par. 83-86 and 112-113).
Regarding claim 18, Mo further discloses:
performing a third readout operation on a third pixel row different from the first and second pixel rows from among the plurality of pixel rows (in the upper rightmost super pixel 1201 with integration time t0 green Gr pixel (of Bayer pattern) is readout using column readout line pixout and stored in an arithmetic counter included in a column parallel ADC, par. 65, 67, 70, 109-113, and Figs. 12 and 14); and
generating third image data based on third pixel signals output by the third readout operation (image data is readout as an analog voltage level on each readout column to readout circuitry 102, including Analog-to-Digital converters 106, and after amplification, the readout image data is transferred to the function logic 111, which may store the image data or may manipulate the image data by applying post image effects (e.g., crop, rotate remove red eye, adjust brightness, adjust contrast or otherwise), par. 64),
wherein the first readout operation, the second readout operation, and the third readout operation are simultaneously performed (simultaneously image data from a first super pixel 1201 (misstated as 1210 based on par. 109-111) having a t0 integration time is readout and stored in a first arithmetic counter included in a first column parallel ADC and the image data from a third super pixel 1201 (misstated as 1210 based on par. 109-111) having a t2 integration time is readout and stored in a second arithmetic counter included in the second column ADC, par. 112-113 and Figs. 12-14).
Allowable Subject Matter
Claims 2-7 and 11-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 2, no prior art could be located that teaches or fairly suggests a third pixel located at the first row and the first column, corresponding to a second color filter, and configured to output a third pixel signal through a third column line; a fourth pixel located at the first row and the first column, corresponding to a third color filter, and configured to output a fourth pixel signal through a fourth column line; and a fifth pixel located at the first row and the first column, corresponding to a fourth color filter, and configured to output a fifth pixel signal through a fifth column line, wherein the third pixel signal, the fourth pixel signal, and the fifth pixel signal are respectively output through the third column line, the fourth column line, and the fifth column line simultaneously with the first pixel signal and the second pixel signal, in combination with the rest of the limitations of the claim and parent claim.
Claims 3-5 depend on claim 2 and therefore are objected to.
Regarding claim 6, no prior art could be located that teaches or fairly suggests a second frame rate corresponding to the second image data is higher than a first frame rate corresponding to the first image data, in combination with the rest of the limitations of the claim and parent claim
Claims 7 depends on claim 6 and therefore is objected to.
Regarding claim 11, no prior art could be located that teaches or fairly suggests when the first pixel is associated with the first image data, the switching circuit performs a first switching operation such that the first column line is connected to the first ADC and the second column line is connected to the second ADC, and wherein, when the first pixel is associated with the second image data, the switching circuit performs a second switching operation such that the first column line is connected to the second ADC and the second column line is connected to the first ADC, in combination with the rest of the limitations of the claim and parent claims.
Regarding claim 12, no prior art could be located that teaches or fairly suggests each of the first pixel and the second pixel has a split photodiode structure including a large photodiode and a small photodiode, in combination with the rest of the limitations of the claim and parent claim.
Claims 13 and 14 depend on claim 12 and therefore are objected to.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS G GILES whose telephone number is (571)272-2824. The examiner can normally be reached M-F 6:45AM-3:15PM EST (HOTELING).
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/NICHOLAS G GILES/ Primary Examiner, Art Unit 2639