Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This office action is in response claims elected communication filed on 09/22/2025. Claims 1-3 have been elected for examination. Claims 4-21 have been withdrawn with traverses.
Response to Arguments
3. Applicant's election with traverse of restriction in the reply filed on 09/22/2025 is acknowledged. The traversal is on the groups 1-8 are interrelated. This is not found persuasive because the following:
Each independent of each group is required a searched for differences subject matter as explained from previous Requirement of Restriction mailed on 06/26/2025. Therefore, would be a serious search and/or examination burden for each independent claim in each group if restriction were not required.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
5. Claim 1 is are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nezuka Pub. No. 2019/0363731.
Regarding claim 1. Fig. 1 of Nezuka discloses a charge (Charge of Cs, Cf) coupled combiner (combiner at - input node of OP) comprising: a source of an input charge (Vin); a first memory node (node of capacitor Cs to store charge); a second memory node (Node of capacitor Cf to store charge); a first transfer gate (switch SS1) coupled between the source of the input charge (Vin) and the first memory node (memory node Cs), and a second transfer gate (switch SS3) coupled between the first memory node (memory node Cs) and the second memory node (memory node Cf) wherein an actuation of the first transfer gate (actuation of SS1) adds charge to the first memory node (charging Cs with Vin) and actuation of the second transfer gate (actuation of SS3) removes charge from the first memory node (discharge from Cs); signals (Signals control SS1/SS3) coupled to the first transfer gate (SS1) and the second transfer gate (SS3) to actuate the first transfer gate (SS1) and the second transfer gate (SS3).
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Nezuka applied to claim 1 above in view of McNutt U.S. patent No. 4,321,584.
Regarding claim 2. Nezuka applied to claim 1 above does not discloses the first transfer gate and the second transfer gate are notch transfer gates.
Fig. 2 of McNutt discloses a transfer gate is a notch transfer gate (Col. 3 lines 65-67).
Nezuka and McNutt are common subject matter of transfer gate; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate notch transfer gate of McNutt into transfer gates of Nezuka for the purpose of providing transfer gate that is charges in the various potential wells can be combined or summed to form a potential on an output gate (Col. 2 lines 2-5 of McNutt).
Regarding claim 3. Nezuka and McNutt applied to claim 1 above, Fig. 2 and Fig. 3 of Mc Nutt further discloses wherein the second notch transfer gate (Col. 3 lines 65-67) comprises a combination of at least one of implants (64) or spacers (spacers of 64) formed under the gate portion of the transfer gate (47) to form a barrier (64; Col. 9 lines 10-13) ) capable of being raised or lowered (Col. 5 lines 40-46 discloses “it raises the potential on the n+ contact and injects electrons over the backflow potential 71 of the corresponding storage well, as shown by the arrow labeled 1 in FIG. 3. If on the other hand the input data line represents a binary 0, then the potential on the n+ contact remains low and no charge is injected into the well. Reference may be made at this point to FIG. 4 which shows a timing diagram of the voltage level of signals present on the various gates shown in FIG. 1. Assuming that circuit is implemented with n-channel technology, when the sample gate is switched on by a relatively low electron potential or a relatively positive voltage, the n+ data line contacts to a constant low potential at the commonly connected n+ sample drains. The result is that the potential in the region 69 the n+ data line contact is dropped, shown by the arrow labeled 2 in FIG. 3”) and a charge notch (Col. 3 lines 65-67) capable of being raised or lowered (Fig. 3 discloses raised or lower potential of 1, 2, 3), and a fixed barrier portion (barrier 46) of the transfer gate (47) not residing under the gate portion of the transfer gate (47).
Contact Information
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 8:30 – 5:00 Monday-Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications.
11/10/2025
/LINH V NGUYEN/Primary Examiner, Art Unit 2845