DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
2. Claims 1-20 are presented for examination.
Response to Arguments
3. Applicant’s argument filed on 12/23/2025 with respect claims 1-20 have been fully considered but they are not persuasive.
The applicant keeps repeating the same agreement that has been addressed before in the office action dated on 09/25/2025, and also has been discussed in the interview that held on 11/25/2025. The applicant contends that the office action fails to teach or suggest the limitation of "ECC encoder receives memory built-in self-test (MBIST)-generated input data from MBIST circuitry as a source of the input data." As recited in claims 1 and 6.
Examiner respectfully disagrees and asserts the reference of Kumar et al. (US 2011/0225475 A1) in paragraphs [0055], [0056] and Fig. 1 teaches the such limitation. For example, Reasons that error correction in memory is important include permanent failures in memory due to aging and other phenomena, and transient failures or soft errors in on-chip memory during application execution due to effects such as alpha particle incidence, heat, process marginalities, etc. These failures and effects motivate error correction improvements for use during manufacturing test and built-in self-test (BIST) in the field. Error correcting codes (ECC) can address both these problems. Not only transient failures but also some permanent failures are correctable using ECC. ECC technology reduces dependency on other techniques such as redundant row/column based repair solutions. See paragraph [0055.
FIG. 1 shows a basic ECC architecture. A bus master 110, such as processor CPU, direct memory access (DMA), BIST, etc., sends read/write addresses and controls and write data via a bus 120 to access a memory 130. Memory 130 is a functional memory that can enter write data or can return read data in response to an access. Problematic high overheads and limitations are associated with conventional ECC based implementations. ECC based on Hamming codes can have higher timing overheads that slow down the maximum useful system frequency. Pipelining might reduce timing overheads but at the cost of throughput. An ECC encoder 140 is coupled for input from bus 120 and generates parity to a parity storage memory 150. See Fig.1 is printed below for your convenience.
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As been described above and has been shown in Fig. 1 above, the ECC encoder 140 is coupled for input from bus 120. Therefore, it would have been obvious to one of ordinary skill in the art that the bus master 110 can be employed as memory built-in self-test (MBIST) circuitry (BIST), and it’s clear that the ECC encoder 140 receives write data [input test data] form built-in self-test BIST 110 [memory built-in self-test (MBIST) circuitry]. “Emphasis added.”
Also, the applicant contends that the cited references fail to teaches or suggest “provides the corrected data and a multi-bit error flag associated with the corrected data as output.” As recited in claim 1.
The Examiner respectfully disagrees and asserts the reference of Kumar et al. (US 2011/0225475 A1) in paragraphs [0056], [0060], [0116], and [0128] teaches the such limitation. For example, the decoder checks for any errors which occur on the bus during data transmission due to issues like crosstalk, power supply droop, etc., that can also be corrected. See paragraph [0048].
Read data from memory 130 and parity from parity storage memory 150 are coupled to an ECC decoder 160 which in turn provides corrected data to the bus master 110. If one or more errors are uncorrectable, an interrupt is supplied to the CPU. In an existing SoC, if ECC is used at all, the CPU is unaware of whether an ECC encode and/or decode pipeline is present and, if present, will have to defer a memory transaction until the existing or current transaction is completely cleared, see discussion of FIG. 21. See paragraph [0056].
One or more Error counters are included in FIG. 16 Error Detector and Correction block 1062. Such Error Counter gets updated in the process embodiments of FIGS. 17 and 18 when multiple errors happen in any data. Single error gets corrected (SECDED) so the counter does not change. The counter decrements when an interrupt is serviced. Error buffers log the values of incorrect data. An Interrupt generator module generates interrupt to CPU whenever a multiple error happens in data. See paragraph [0116].
ECC parity decoder 262 provides error data to an XOR block 264 that corrects the data from main memory 230 and supplies the corrected data to the accessing circuits such as DMA, processor, or other system module. See paragraph [0060].
In FIG. 17, a process embodiment for this BUS BIST mode runs an application in step 1120 (Run with Functional mode) until a bus error (Yes) is detected by a decision step 1130, whereupon Test mode operation at a step 1140 maintains an error count and a log that can be read any time. A decision step 1160 determines whether a latest Error is correctable. If correctable, corrected data is generated by step 1170 in FIG. 16 and the application 1120 continues. If the data is not correctable at step 1160, a step 1180 sends an interrupt to the CPU to flag the uncorrectable data error, and CPU can read and clear the log and possibly take remedial action regarding the particular application and the system. The interrupt can be cleared by CPU. The step 1140 error log is updated until a step 1150 detects that the log is full whereupon a Full flag can be set, the application 1120 continues, and the log can also be analyzed subsequently. For example, when the Full flag is set, an interrupt 1180 is activated, and then CPU operations 1190 Read the Error log and Error count, and the BIST clears the Error log and clears the Error count, whereupon a step 1195 clears the interrupt. See paragraph [0128]. See Fig.1 is printed below for your convenience.
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As been shown in Fig. 1 above, both one or more errors are uncorrectable (interrupt signal) and the corrected data have been provided to the CPU BIST 110. Emphasis added.
Further, the applicant contends that the cited references fail to teaches or suggest “a replica MBIST.” As recited in claim 14.
The Examiner respectfully disagrees and asserts the reference of Kumar et al. (US 2011/0225475 A1) in paragraphs [0060] and Fig. 2 teaches the such limitation. For example, on read, data from a read address in the main memory 230 is read out in response to memory read control and read address signals from the controller 246. Concurrently, the dual-ported parity memory 250 responds to controller 246 and reads out parity from that read address. That parity is the parity pertaining to data that was earlier-written to main memory 230 at that read address. The read data that is read out from main memory 230 should be the same as the write data from which the parity was encoded, but a data error may have occurred. An ECC parity decoder 262 processes the data read from main memory 230 as well as the parity bits retrieved from the parity memory 250. ECC parity decoder 262 provides error data to an XOR block 264 that corrects the data from main memory 230 and supplies the corrected data to the accessing circuits such as DMA, processor, or other system module. See paragraph [0060]. For the Applicant’s convenience, see Fig. 2 is reproduced below.
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As been describes above, as would be understood by one of ordinary skill in the art that the XOR block 264 receives the error data and multi-bit error flag; and selectively modifies and sent the corrected data to BIST 110, which is performed similar function to replica MBIST. “Emphasis added.”
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(a):
(a) IN GENERAL. The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), first paragraph:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
4. Claims 1-20 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
In regards to claim 1, the claim recites “ECC encoder receives memory built-in self-test (MBIST) generated input data from MBIST circuitry as a source of the input data.” The disclosure does not provide the feature this feature. Nowhere in the specification or in the drawings does the applicant teach the features of “generated input data as a source of the input data” Correction is required. In regards to claims 6 and 14, the claim recites similar feature of claim 1, therefore, is rejected for similar reason of claim 1 above. Dependent claims 2-5, 7-13, and 16-20 depend from the base claims 1, 6, and 14 respectively and inherently include limitations therein and therefore are rejected under 35 USC 112, 1st paragraph as well.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
5. Claims 1-5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
In regards to claim 1, the claim recites "provides the corrected data and a multi-bit error flag associated with the corrected data as output." This feature is ambiguous because it’s unclear in the claim how to provide the corrected data and a multi-bit error flag and again associated with the corrected data? (Emphasis added). Please clarify.
Dependent claims 2-5 depend from the base claim 1 and inherently include limitations therein and therefore are rejected under 35 USC 112, 2nd paragraph as well.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
6. Claims 1, 2, 6-10, 12, 14, and 16-20 are rejected under 35 U.S.C. 103 (a) as being unpatentable over Kumar et al. (US 2011/0225475 A1) "herein after as Kumar" in view of Jung Hyunho et al. (JP 2002171172 A "herein after as Jung."
As per claim 1:
Kumar substantially teaches or discloses a device, comprising (see Fig. 1): an error correction coding (ECC) encoder (see Fig. 1, ECC encoder 140) coupled to memory (see Fig. 1, memory 150), wherein the ECC encoder receives memory built-in self-test (MBIST)-generated input data from MBIST circuitry as a source of the input data (see Fig. 1, the ECC encoder 140 receives write data [input data] form built-in self-test BIST 110 [memory built-in self-test (MBIST) circuitry]), generates encoded data by encoding the input data and by adding check bits to the input data, and writes the encoded data to the memory (see paragraph [0056], herein An ECC encoder 140 is coupled for input from bus 120 and generates parity to a parity storage memory 150); and an ECC decoder (see Fig. 1, ECC decoder 160) coupled to the memory (see Fig. 1, memory 150), wherein the ECC decoder reads the encoded data from the memory (see paragraph [0056], herein Read data from memory 130 and parity from parity storage memory 150 are coupled to an ECC decoder 160 which in turn provides corrected data to the bus master 110), generates corrected data by decoding the encoded data, and provides the corrected data and a multi-bit error flag associated with the corrected data as output (see paragraph [0048], herein the decoder checks for any errors which occur on the bus during data transmission due to issues like crosstalk, power supply droop, etc., that can also be corrected, and paragraph [0056], herein Read data from memory 130 and parity from parity storage memory 150 are coupled to an ECC decoder 160 which in turn provides corrected data to the bus master 110), wherein the ECC decoder has error correction logic that performs error correction on the decoded data based on the check bits (see paragraph [0193], herein the ECC circuit to read from the memory and decode the read data using parity from the parity memory to form a first decoded result), wherein if the error correction logic detects a multi-bit error in the decoded data, the error correction logic corrects the multi- bit error in the decoded data to output the corrected data (see paragraph [0048], herein the decoder checks for any errors which occur on the bus during data transmission due to issues like crosstalk, power supply droop, etc., that can also be corrected, and paragraph [0060], herein ECC parity decoder 262 provides error data to an XOR block 264 that corrects the data from main memory 230 and supplies the corrected data to the accessing circuits such as DMA, processor, or other system module); and generates the multi-bit error flag to indicate an outcome of the error correction performed on the decoded data by the error correction logic (see paragraph [0056], herein Read data from memory 130 and parity from parity storage memory 150 are coupled to an ECC decoder 160 which in turn provides corrected data to the bus master 110. If one or more errors are uncorrectable, an interrupt is supplied to the CPU; and paragraph [0128]).
Kumar does not explicitly teach generates corrected data by extracting the check bits from the encoded data.
However, Jung in the same the field of endeavor teaches generates corrected data by extracting the check bits from the encoded data (see paragraph [0026], herein Turbo decoder for generating decoded information bits by removing said detected parity bits from the encoded information bit stream).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Kumar with the teachings of Jung by generating corrected data by extracting the check bits from the encoded data.
This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the generating corrected data by extracting the check bits from the encoded data would have improved reduced power consumption required for decoding information bits and also decoding speed can be improved (see paragraph [0047] of Jung).
As per claim 2:
Kumar teaches that wherein the multi-bit error refers to a double-bit error (see paragraph [0125], herein the combined case wherein ECC module 1062 takes care of both single error correction and double error detection).
As per claim 6:
Kumar substantially teaches or discloses a device, comprising: error correction coding (ECC) circuitry comprising (see Fig. 1, basic ECC architecture):an ECC encoder (see Fig. 1, ECC encoder 140) being operably coupled to a memory (see Fig. 1, memory 150), wherein the ECC encoder: receives memory built-in self-test (MBIST)- generated input data from MBIST circuitry as a source of the input data (see Fig. 1, the ECC encoder 140 receives write data [input data] form built-in self-test BIST 110 [memory built-in self-test (MBIST) circuitry]); generates encoded data by adding check bits to the input data from the MBIST circuitry and encoding the input data from the MBIST circuitry; and writes the encoded data to the memory (see paragraph [0056], herein An ECC encoder 140 is coupled for input from bus 120 and generates parity to a parity storage memory 150); and an ECC decoder (see Fig. 1, ECC decoder 160) being operably coupled to the memory (see Fig. 1, memory 150), wherein the ECC decoder: reads the encoded data from the memory (see paragraph [0056], herein Read data from memory 130 and parity from parity storage memory 150 are coupled to an ECC decoder 160 which in turn provides corrected data to the bus master 110); generates corrected data by decoding the encoded data (see paragraph [0193], herein the ECC circuit to read from the memory and decode the read data using parity from the parity memory to form a first decoded result); and provides the corrected data and a multi-bit error flag as an output (see paragraph [0048], herein the decoder checks for any errors which occur on the bus during data transmission due to issues like crosstalk, power supply droop, etc., that can also be corrected, and paragraph [0060], herein ECC parity decoder 262 provides error data to an XOR block 264 that corrects the data from main memory 230 and supplies the corrected data to the accessing circuits such as DMA, processor, or other system module).
Kumar does not explicitly teach generates corrected data by extracting the check bits from the encoded data.
However, Jung in the same the field of endeavor teaches generates corrected data by extracting the check bits from the encoded data (see paragraph [0026], herein Turbo decoder for generating decoded information bits by removing said detected parity bits from the encoded information bit stream).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Kumar with the teachings of Jung by generating corrected data by extracting the check bits from the encoded data.
This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the generating corrected data by extracting the check bits from the encoded data would have improved reduced power consumption required for decoding information bits and also decoding speed can be improved (see paragraph [0047] of Jung).
As per claim 7:
Kumar teaches that wherein: the ECC circuitry is configured to operate during an MBIST run where the ECC circuitry is active and at least one finite state machine (FSM) is configured to repair memory data based on the corrected data (see paragraph [0061], herein the states of the state machine 300 provide output controls to the main memory 230 and to the parity memory 250 to make operations happen as discussed for FIGS. 2, 4, 10 and other Figures herein. Some embodiments include one or more logic structures and/or further state machines to effectuate operations initiated by the respective Read, Write and Partial Write states of state machine 300, and Fig. 3).
As per claim 8:
Kumar teaches that wherein: in response to the encoded data being greater than the input data, check bits are added to the input data (see paragraph [0013], herein a parity generator module coupled to a first-place on the bus and operable to generate ECC parity, a mode-responsive selector circuit fed at a first input by the parity generator and at a second input from a second place on the bus, and an ECC decoder including an error detector selectively fed from the selector circuit).
As per claim 9:
Kumar teaches that wherein: the multi-bit error flag refers to a double-bit error (see paragraph [0125], herein the combined case wherein ECC module 1062 takes care of both single error correction and double error detection).
As per claim 10:
Kumar teaches that wherein: the ECC decoder comprises error correction logic that performs error correction on the decoded data based on the check bits; and in response to the error correction logic detecting the multi-bit error in the decoded data, the error correction logic corrects the multi-bit error in the decoded data to provide the corrected data (see paragraph [0048], herein the decoder checks for any errors which occur on the bus during data transmission due to issues like crosstalk, power supply droop, etc., that can also be corrected, and paragraph [0060], herein ECC parity decoder 262 provides error data to an XOR block 264 that corrects the data from main memory 230 and supplies the corrected data to the accessing circuits such as DMA, processor, or other system module).
As per claim 12:
Kumar teaches that wherein: a replica MBIST is configured to receive the corrected data and the multi-bit error flag from the ECC decoder and provides output data to the MBIST circuitry (see paragraph [0056], herein Read data from memory 130 and parity from parity storage memory 150 are coupled to an ECC decoder 160 which in turn provides corrected data to the bus master 110).
As per claim 14:
Kumar substantially teaches or discloses an integrated circuit (IC), comprising: error correction coding (ECC) circuitry comprising (see Fig. 1, basic ECC architecture): an ECC encoder (see Fig. 1, ECC encoder 140), wherein the ECC encoder: receives memory built-in self-test (MBIST)- generated input data from MBIST circuitry as a source of the input data ((see Fig. 1, the ECC encoder 140 receives write data [input data] form built-in self-test BIST 110 [memory built-in self-test (MBIST) circuitry]); generates encoded data by encoding the input data and by adding check bits to the input data; and writes the encoded data to a memory (see paragraph [0056], herein An ECC encoder 140 is coupled for input from bus 120 and generates parity to a parity storage memory 150); and an ECC decoder (see Fig. 1, ECC decoder 160); an ECC decoder (see Fig. 1, ECC decoder 160), wherein the ECC decoder: reads the encoded data from the memory (see paragraph [0056], herein Read data from memory 130 and parity from parity storage memory 150 are coupled to an ECC decoder 160 which in turn provides corrected data to the bus master 110); generates corrected data by decoding the encoded by extracting the check bits from the encoded data and (see paragraph [0048], herein the decoder checks for any errors which occur on the bus during data transmission due to issues like crosstalk, power supply droop, etc., that can also be corrected); and outputs the corrected data and multi-bit error flag ( paragraph [0056], herein Read data from memory 130 and parity from parity storage memory 150 are coupled to an ECC decoder 160 which in turn provides corrected data to the bus master 110); and a replica MBIST, wherein the replica MBIST: receives the correct data and multi-bit error flag; and selectively modifies the corrected data based on the multi-bit error flag (see paragraph [0060], herein an ECC parity decoder 262 processes the data read from main memory 230 as well as the parity bits retrieved from the parity memory 250. ECC parity decoder 262 provides error data to an XOR block 264 that corrects the data from main memory 230 and supplies the corrected data to the accessing circuits such as DMA, processor, or other system module); and provides a result of the selective modification of the corrected data to the MBIST circuitry (see paragraph [0056, herein Read data from memory 130 and parity from parity storage memory 150 are coupled to an ECC decoder 160 which in turn provides corrected data to the bus master 110; paragraph [0172], herein said decoder is operable to supply corrected data to said accessing circuit; and Figs. 1 &2). Kumar does not explicitly teach generates corrected data by extracting the check bits from the encoded data.
However, Jung in the same the field of endeavor teaches generates corrected data by extracting the check bits from the encoded data (see paragraph [0026], herein Turbo decoder for generating decoded information bits by removing said detected parity bits from the encoded information bit stream).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Kumar with the teachings of Jung by generating corrected data by extracting the check bits from the encoded data.
This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the generating corrected data by extracting the check bits from the encoded data would have improved reduced power consumption required for decoding information bits and also decoding speed can be improved (see paragraph [0047] of Jung).
As per claim 16:
Kumar teaches that wherein: the ECC encoder is configured to input bus swap with the memory; and the memory is configured to output bus swap with the ECC decoder (see paragraph [0056], herein An ECC encoder 140 is coupled for input from bus 120 and generates parity to a parity storage memory 150. Read data from memory 130 and parity from parity storage memory 150 are coupled to an ECC decoder 160 which in turn provides corrected data to the bus master 110, and Fig. 1).
As per claim 17:
Kumar teaches that wherein: the ECC circuitry is configured to conduct data error checks in multiple passes; and a single pass comprises the input data from MBIST circuitry through the ECC circuitry, wherein the corrected data is outputted (see paragraph [0048], herein the decoder checks for any errors which occur on the bus during data transmission due to issues like crosstalk, power supply droop, etc., that can also be corrected, and paragraph [0060], herein ECC parity decoder 262 provides error data to an XOR block 264 that corrects the data from main memory 230 and supplies the corrected data to the accessing circuits such as DMA, processor, or other system module).
As per claim 18:
Kumar teaches that wherein: the ECC circuitry performs a first pass without bus swapping and a second pass with bus swapping to increase error detection; and the multiple passes are configured to enhance error detection coverage and ensure comprehensive stress testing of bitcells in the memory during MBIST (see Fig. 1, ECC encoder 140 receives input from bus 120 and generates parity to a parity storage memory 150, and ECC decoder 160 reads data from memory 130).
As per claim 19:
Kumar teaches that wherein: in the first pass the ECC encoder generates and adds the check bits to a beginning of the input data creating a first data sequence (see paragraph [0056], herein An ECC encoder 140 is coupled for input from bus 120 and generates parity to a parity storage memory 150; the MBIST circuitry is configured to test the first data sequence (see paragraph [0055], herein These failures and effects motivate error correction improvements for use during manufacturing test and built-in self-test (BIST) in the field. Error correcting codes (ECC) can address both these problems); and error detection is performed by comparing the input data to the corrected data (see paragraph [0017], herein enabling the ECC circuit, reading data and parity from the memory, operating the ECC circuit to detect error in the data read from the memory using the parity, operating the ECC circuit to independently generate parity for the data during the reading of the data from the memory and comparing the generated parity with the parity that is read from the memory, and updating an error report with the results of the comparing).
As per claim 20:
Kumar teaches that wherein: in the second pass the ECC encoder generates a second data sequence by adding the check bits to an end of the input data (see paragraph [0056], herein An ECC encoder 140 is coupled for input from bus 120 and generates parity to a parity storage memory 150); the MBIST circuitry is configured to test the second data sequence see paragraph [0055], herein These failures and effects motivate error correction improvements for use during manufacturing test and built-in self-test (BIST) in the field. Error correcting codes (ECC) can address both these problems); and error detection is performed by comparing the input data to the corrected data (see paragraph [0017], herein enabling the ECC circuit, reading data and parity from the memory, operating the ECC circuit to detect error in the data read from the memory using the parity, operating the ECC circuit to independently generate parity for the data during the reading of the data from the memory and comparing the generated parity with the parity that is read from the memory, and updating an error report with the results of the comparing).
Allowable Subject Matter
7. Claims 3, 11, 13, and 15 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and to overcome the claim rejections under 35 USC § 112, 1st & 2nd set forth in this Office action. Dependent claims 4-5 depend from on claim 34 and inherently include limitations therein and therefore are allowed as well.
Examiner Notes
8. When amending the claims, applicants are respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Prior Art
9. The prior art of record, considered pertinent to the applicant’s disclosure, is listed in the attached PTO-892 form.
Conclusion
10. THIS ACTION IS MADE FINAL; Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to OSMAN ALSHACK whose telephone number is (571)272-2069.
The examiner can normally be reached on MON-FRI 8:30 AM-5:00 PM EST, also please fax interview request to (571) 273- 2069.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ALBERT DECADY can be reached on 5712723819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/OSMAN ALSHACK/
Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112