DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
2. Claims 1-20 are presented for examination.
Request for Continued Examination
3. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant’s submission filed on 05/18/2026 has been entered.
Claim Rejections - 35 USC § 112
4. The rejection of claims 1-20 under 35 U.S.C. § 112, first paragraph, is withdrawn in view of applicant's amendments/remarks.
Claim Rejections - 35 USC § 112
5. The rejection of claims 1-5 under 35 U.S.C. § 112, second paragraph, is withdrawn in view of applicant's amendments/remarks.
Information Disclosure Statement
6. The references listed in the information disclosure statement (IDS) submitted on 03/04/2026 have been considered. The submission complies with the provisions of 37 CFR 1.97. Form PTO- 1449 is signed and attached hereto.
Response to Arguments
7. Applicant’s argument filed on 04/15/2026 with respect claims 1, 6, and 14 have been fully considered but they are not persuasive.
The applicant contends that the office action fails to teach or suggest the limitation of " generates the multi-bit error flag as an output together with the corrected data, and wherein the multi-bit error flag is generated to indicate an outcome of the error correction performed or attempted on the decoded data by the error correction logic." As recited in claims 1 and 6.
The Examiner respectfully disagrees and asserts the reference of Kumar et al. (US 2011/0225475 A1) in paragraphs [0056], [0060], [0089], [0092], [0128] and Figs. 1 & 2 teaches the such limitation. For example, FIG. 1 shows a basic ECC architecture. A bus master 110, such as processor CPU, direct memory access (DMA), BIST, etc., sends read/write addresses and controls and write data via a bus 120 to access a memory 130. Memory 130 is a functional memory that can enter write data or can return read data in response to an access. Problematic high overheads and limitations are associated with conventional ECC based implementations. ECC based on Hamming codes can have higher timing overheads that slow down the maximum useful system frequency. Pipelining might reduce timing overheads but at the cost of throughput. An ECC encoder 140 is coupled for input from bus 120 and generates parity to a parity storage memory 150. Read data from memory 130 and parity from parity storage memory 150 are coupled to an ECC decoder 160 which in turn provides corrected data to the bus master 110. If one or more errors are uncorrectable, an interrupt is supplied to the CPU. In an existing SoC, if ECC is used at all, the CPU is unaware of whether an ECC encode and/or decode pipeline is present and, if present, will have to defer a memory transaction until the existing or current transaction is completely cleared, see discussion of FIG. 21. Partial writes to memory present problems in FIG. 1, see discussion of FIG. 22. Partial writes to memory and some other accesses can be handled much more efficiently as taught with other Figures herein and can deliver a beneficial impact on throughput. Advantage can be taken of the locality that is characteristic of data traffic in applications as taught herein. See paragraph [0056].
On read, data from a read address in the main memory 230 is read out in response to memory read control and read address signals from the controller 246. Concurrently, the dual-ported parity memory 250 responds to controller 246 and reads out parity from that read address. That parity is the parity pertaining to data that was earlier-written to main memory 230 at that read address. The read data that is read out from main memory 230 should be the same as the write data from which the parity was encoded, but a data error may have occurred. An ECC parity decoder 262 processes the data read from main memory 230 as well as the parity bits retrieved from the parity memory 250. ECC parity decoder 262 provides error data to an XOR block 264 that corrects the data from main memory 230 and supplies the corrected data to the accessing circuits such as DMA, processor, or other system module. See paragraph [0060].
FIG. 10 details interconnected portions of the ECC Parity Decoder 262 of FIG. 2 with the ECC Encoder 242 of FIG. 2. In FIG. 10, the Decoder 262 architecture provides remarkable structures 740, 760, 770 shown enclosed in dotted lines 750 for throughput improvement in a read path. Moreover, a parity-decoding XOR tree 720 is remarkably based on transpose H matrix of Hsiao code of FIG. 20 to more rapidly produce a Syndrome from data bits from main memory 230 (Data Memory) and parity bits from Parity memory 250 of FIG. 2 for a given Read address. A Look-up table 730 stores each error generation output associated with each respective possible Syndrome value. The Look-up table 730 thus generates an Error pattern output from a particular current Syndrome value input from the XOR tree 720. In the decoder 262 the XOR tree 720 detects if an error exists in the data being read from the memory 230. XOR tree 720 corresponds to the transpose of H matrix for Hsiao code, see FIG. 20, and outputs the syndrome. The Look-up table 730 indicates uniquely the bit position where the data is in error. The Look-up table 730 is indexed by the syndrome, and outputs the error pattern one-hot encoded. See paragraph [0089].
FIG. 10A shows re-arranged selectors and alternative MUX couplings for write data buffer W.D.B. 440 and memory Mem 230 relative to FIG. 10. In FIG. 10A, the write data buffer 440 is instead selected by MUX 770 in response to the comparator 760 if the write address buffer 410 holds the pertinent (matching) address to which the read pertains. If that address is absent, the output of MUX 740 is selected by the MUX 770. MUX 740 has its selector control responsive to an absence of error (syndrome=0 at syndrome generator output) to select uncorrected memory 230 read data (Mem). That way, if no error, mux 740 for timing purposes bypasses the error correction circuitry including the XOR error corrector 264 and the Lookup table 730. If a memory 230 data error is detected (syndrome not 0), then MUX 740 in FIG. 10A selects the XOR 720 error correction circuitry output. See paragraph [0092].
In FIG. 17, a process embodiment for this BUS BIST mode runs an application in step 1120 (Run with Functional mode) until a bus error (Yes) is detected by a decision step 1130, whereupon Test mode operation at a step 1140 maintains an error count and a log that can be read any time. A decision step 1160 determines whether a latest Error is correctable. If correctable, corrected data is generated by step 1170 in FIG. 16 and the application 1120 continues. If the data is not correctable at step 1160, a step 1180 sends an interrupt to the CPU to flag the uncorrectable data error, and CPU can read and clear the log and possibly take remedial action regarding the particular application and the system. The interrupt can be cleared by CPU. The step 1140 error log is updated until a step 1150 detects that the log is full whereupon a Full flag can be set, the application 1120 continues, and the log can also be analyzed subsequently. For example, when the Full flag is set, an interrupt 1180 is activated, and then CPU operations 1190 Read the Error log and Error count, and the BIST clears the Error log and clears the Error count, whereupon a step 1195 clears the interrupt. See paragraph [0128]. See paragraph [0128]. Also, see Figs. 1, 2, and 10 are printed below for your convenience.
PNG
media_image1.png
657
680
media_image1.png
Greyscale
PNG
media_image2.png
406
659
media_image2.png
Greyscale
As been described above, it’s clear that decoder 160 outputs together the corrected data and interrupt signals [multiple bit error flag], and the output generated from decoder 262 include two values, and the MUX 740 has its selector control responsive to an absence of error (syndrome=0 at syndrome generator output) to select uncorrected memory 230 read data (Mem). That way, if no error, mux 740 for timing purposes bypasses the error correction circuitry including the XOR error corrector 264 and the Lookup table 730. If a memory 230 data error is detected (syndrome not 0). Emphasis added.
Further, the applicant contends that the cited references fail to teaches or suggest “a replica MBIST, wherein the replica MBIST: receives the corrected data and the multi-bit error flag; selectively modifies the corrected data based on the multi-bit error flag; and provides a result of the selective modification of the corrected data to the MBIST circuitry.” As recited in claim 14.
The Examiner notes that the applicant’s arguments regarding to the above limitations have been considered but are moot in view of the new ground(s) of rejection. In addition to, the Examiner maintained the reference of Kumar et al. (US 2011/0225475 A1) since there is no further argument/s regarding to this reference.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
8. Claims 1, 2, 6-10, and 12 are rejected under 35 U.S.C. 103 (a) as being unpatentable over Kumar et al. (US 2011/0225475 A1) "herein after as Kumar" in view of Jung Hyunho et al. (JP 2002171172 A) "herein after as Jung."
As per claim 1:
Kumar substantially teaches or discloses a device, comprising (see Fig. 1): an error correction coding (ECC) encoder (see Fig. 1, ECC encoder 140) coupled to memory (see Fig. 1, memory 150), wherein the ECC encoder receives memory built-in self-test (MBIST)-generated input data from MBIST circuitry (see Fig. 1, the ECC encoder 140 receives write data [input data] form built-in self-test BIST 110 [memory built-in self-test (MBIST) circuitry]), generates encoded data by encoding the input data and by adding check bits to the input data, and writes the encoded data to the memory (see paragraph [0056], herein An ECC encoder 140 is coupled for input from bus 120 and generates parity to a parity storage memory 150); and an ECC decoder (see Fig. 1, ECC decoder 160) coupled to the memory (see Fig. 1, memory 150), wherein the ECC decoder reads the encoded data from the memory (see paragraph [0056], herein Read data from memory 130 and parity from parity storage memory 150 are coupled to an ECC decoder 160 which in turn provides corrected data to the bus master 110), generates corrected data by decoding the encoded data, and provides the corrected data and a multi-bit error flag (see paragraph [0048], herein the decoder checks for any errors which occur on the bus during data transmission due to issues like crosstalk, power supply droop, etc., that can also be corrected; paragraph [0056], herein Read data from memory 130 and parity from parity storage memory 150 are coupled to an ECC decoder 160 which in turn provides corrected data to the bus master 110. If one or more errors are uncorrectable, an interrupt is supplied to the CPU, and Fig. 1 [the decoder 160 outputs corrected data and interrupt signal]), wherein the ECC decoder has error correction logic that performs error correction on the decoded data based on the check bits (see paragraph [0193], herein the ECC circuit to read from the memory and decode the read data using parity from the parity memory to form a first decoded result), wherein if the error correction logic detects a multi-bit error in the decoded data, the error correction logic corrects the multi- bit error in the decoded data to output the corrected data (see paragraph [0048], herein the decoder checks for any errors which occur on the bus during data transmission due to issues like crosstalk, power supply droop, etc., that can also be corrected, and paragraph [0060], herein ECC parity decoder 262 provides error data to an XOR block 264 that corrects the data from main memory 230 and supplies the corrected data to the accessing circuits such as DMA, processor, or other system module); and generates the multi-bit error flag as an output together with the corrected data, and wherein the multi-bit error flag is generated to indicate an outcome of the error correction performed or attempted on the decoded data by the error correction logic (see paragraph [0092], herein MUX 740 has its selector control responsive to an absence of error (syndrome=0 at syndrome generator output) to select uncorrected memory 230 read data (Mem). That way, if no error, mux 740 for timing purposes bypasses the error correction circuitry including the XOR error corrector 264 and the Lookup table 730. If a memory 230 data error is detected (syndrome not 0), then MUX 740 in FIG. 10A selects the XOR 720 error correction circuitry output; and paragraphs [0089] [0128], and Fig. 10).
Kumar does not explicitly teach generates corrected data by extracting the check bits from the encoded data.
However, Jung in the same the field of endeavor teaches generates corrected data by extracting the check bits from the encoded data (see paragraph [0026], herein turbo decoder for generating decoded information bits by removing said detected parity bits from the encoded information bit stream).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Kumar with the teachings of Jung by generating corrected data by extracting the check bits from the encoded data.
This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the generating corrected data by extracting the check bits from the encoded data would have improved reduced power consumption required for decoding information bits and also decoding speed can be improved (see paragraph [0047] of Jung).
As per claim 2:
Kumar teaches that wherein the multi-bit error flag has a first value when the error correction logic corrects the multi-bit error in the decoded data and a second value when the error correction logic attempts to correct the multi-bit error in the decoded data (see paragraph [0092], herein If that address is absent, the output of MUX 740 is selected by the MUX 770. MUX 740 has its selector control responsive to an absence of error (syndrome=0 at syndrome generator output) to select uncorrected memory 230 read data (Mem). That way, if no error, mux 740 for timing purposes bypasses the error correction circuitry including the XOR error corrector 264 and the Lookup table 730. If a memory 230 data error is detected (syndrome not 0), then MUX 740 in FIG. 10A selects the XOR 720 error correction circuitry output).
As per claim 6:
Kumar substantially teaches or discloses a device, comprising: error correction coding (ECC) circuitry comprising (see Fig. 1, basic ECC architecture):an ECC encoder (see Fig. 1, ECC encoder 140) being operably coupled to a memory (see Fig. 1, memory 150), wherein the ECC encoder: receives memory built-in self-test (MBIST)- generated input data from MBIST circuitry (see Fig. 1, the ECC encoder 140 receives write data [input data] form built-in self-test BIST 110 [memory built-in self-test (MBIST) circuitry]); generates encoded data by adding check bits to the input data from the MBIST circuitry and encoding the input data from the MBIST circuitry; and writes the encoded data to the memory (see paragraph [0056], herein An ECC encoder 140 is coupled for input from bus 120 and generates parity to a parity storage memory 150); and an ECC decoder (see Fig. 1, ECC decoder 160) being operably coupled to the memory (see Fig. 1, memory 150), wherein the ECC decoder: reads the encoded data from the memory (see paragraph [0056], herein Read data from memory 130 and parity from parity storage memory 150 are coupled to an ECC decoder 160 which in turn provides corrected data to the bus master 110); generates corrected data by decoding the encoded data (see paragraph [0193], herein the ECC circuit to read from the memory and decode the read data using parity from the parity memory to form a first decoded result); decoding the encoded data generates a multi-bit error flag as an output together with the corrected data (see paragraph [0048], herein the decoder checks for any errors which occur on the bus during data transmission due to issues like crosstalk, power supply droop, etc., that can also be corrected, and paragraph [0060], herein ECC parity decoder 262 provides error data to an XOR block 264 that corrects the data from main memory 230 and supplies the corrected data to the accessing circuits such as DMA, processor, or other system module; paragraph [0056], herein Read data from memory 130 and parity from parity storage memory 150 are coupled to an ECC decoder 160 which in turn provides corrected data to the bus master 110. If one or more errors are uncorrectable, an interrupt is supplied to the CPU, and Fig. 1 [the decoder 160 outputs corrected data and interrupt signal]), and wherein the multi-bit error flag is generated to indicate an outcome of the error correction performed or attempted on the decoded data; and provides the corrected data and the multi-bit error flag as an output (see paragraph [0092], herein MUX 740 has its selector control responsive to an absence of error (syndrome=0 at syndrome generator output) to select uncorrected memory 230 read data (Mem). That way, if no error, mux 740 for timing purposes bypasses the error correction circuitry including the XOR error corrector 264 and the Lookup table 730. If a memory 230 data error is detected (syndrome not 0), then MUX 740 in FIG. 10A selects the XOR 720 error correction circuitry output; and paragraphs [0089] [0128], and Fig. 10).
Kumar does not explicitly teach generates corrected data by extracting the check bits from the encoded data.
However, Jung in the same the field of endeavor teaches generates corrected data by extracting the check bits from the encoded data (see paragraph [0026], herein Turbo decoder for generating decoded information bits by removing said detected parity bits from the encoded information bit stream).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Kumar with the teachings of Jung by generating corrected data by extracting the check bits from the encoded data.
This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the generating corrected data by extracting the check bits from the encoded data would have improved reduced power consumption required for decoding information bits and also decoding speed can be improved (see paragraph [0047] of Jung).
As per claim 7:
Kumar teaches that wherein: the ECC circuitry is configured to operate during an MBIST run where the ECC circuitry is active and at least one finite state machine (FSM) is configured to repair memory data based on the corrected data (see paragraph [0061], herein the states of the state machine 300 provide output controls to the main memory 230 and to the parity memory 250 to make operations happen as discussed for FIGS. 2, 4, 10 and other Figures herein. Some embodiments include one or more logic structures and/or further state machines to effectuate operations initiated by the respective Read, Write and Partial Write states of state machine 300, and Fig. 3).
As per claim 8:
Kumar teaches that wherein: in response to the encoded data being greater than the input data, check bits are added to the input data (see paragraph [0013], herein a parity generator module coupled to a first-place on the bus and operable to generate ECC parity, a mode-responsive selector circuit fed at a first input by the parity generator and at a second input from a second place on the bus, and an ECC decoder including an error detector selectively fed from the selector circuit).
As per claim 9:
Kumar teaches that wherein: the multi-bit error flag refers to a double-bit error (see paragraph [0125], herein the combined case wherein ECC module 1062 takes care of both single error correction and double error detection).
As per claim 10:
Kumar teaches that wherein: the ECC decoder comprises error correction logic that performs error correction on the decoded data based on the check bits; and in response to the error correction logic detecting the multi-bit error in the decoded data, the error correction logic corrects the multi-bit error in the decoded data to provide the corrected data (see paragraph [0048], herein the decoder checks for any errors which occur on the bus during data transmission due to issues like crosstalk, power supply droop, etc., that can also be corrected, and paragraph [0060], herein ECC parity decoder 262 provides error data to an XOR block 264 that corrects the data from main memory 230 and supplies the corrected data to the accessing circuits such as DMA, processor, or other system module).
As per claim 12:
Kumar teaches that wherein: a replica MBIST is configured to receive the corrected data and the multi-bit error flag from the ECC decoder and provides output data to the MBIST circuitry (see paragraph [0056], herein Read data from memory 130 and parity from parity storage memory 150 are coupled to an ECC decoder 160 which in turn provides corrected data to the bus master 110).
9. Claims 14, and 16-20 are rejected under 35 U.S.C. 103 (a) as being unpatentable over Kumar et al. (US 2011/0225475 A1) "herein after as Kumar" in view of Jung Hyunho et al. (JP 2002171172 A "herein after as Jung" in further view of Engin et al, (US 2017/0039103 A1) “herein after as Engin.”
As per claim 14:
Kumar substantially teaches or discloses an integrated circuit (IC), comprising: error correction coding (ECC) circuitry comprising (see Fig. 1, basic ECC architecture): an ECC encoder (see Fig. 1, ECC encoder 140), wherein the ECC encoder: receives memory built-in self-test (MBIST)- generated input data from MBIST circuitry (see Fig. 1, the ECC encoder 140 receives write data [input data] form built-in self-test BIST 110 [memory built-in self-test (MBIST) circuitry]); generates encoded data by encoding the input data and by adding check bits to the input data; and writes the encoded data to a memory (see paragraph [0056], herein An ECC encoder 140 is coupled for input from bus 120 and generates parity to a parity storage memory 150); and an ECC decoder (see Fig. 1, ECC decoder 160); an ECC decoder (see Fig. 1, ECC decoder 160), wherein the ECC decoder: reads the encoded data from the memory (see paragraph [0056], herein Read data from memory 130 and parity from parity storage memory 150 are coupled to an ECC decoder 160 which in turn provides corrected data to the bus master 110); generates corrected data by decoding the encoded by extracting the check bits from the encoded data and (see paragraph [0048], herein the decoder checks for any errors which occur on the bus during data transmission due to issues like crosstalk, power supply droop, etc., that can also be corrected); and outputs the corrected data and multi-bit error flag (see paragraph [0056], herein Read data from memory 130 and parity from parity storage memory 150 are coupled to an ECC decoder 160 which in turn provides corrected data to the bus master 110. If one or more errors are uncorrectable, an interrupt is supplied to the CPU, and Fig. 1 [the decoder 160 outputs corrected data and interrupt signal]). Kumar does not explicitly teach generates corrected data by extracting the check bits from the encoded data.
However, Jung in the same the field of endeavor teaches generates corrected data by extracting the check bits from the encoded data (see paragraph [0026], herein Turbo decoder for generating decoded information bits by removing said detected parity bits from the encoded information bit stream).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Kumar with the teachings of Jung by generating corrected data by extracting the check bits from the encoded data.
This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the generating corrected data by extracting the check bits from the encoded data would have improved reduced power consumption required for decoding information bits and also decoding speed can be improved (see paragraph [0047] of Jung).
Kumar-Jung as combined teaches all the subject matter of claim 14 except a replica MBIST, wherein the replica MBIST: receives the corrected data and the multi-bit error flag; selectively modifies the corrected data based on the multi-bit error flag; and provides a result of the selective modification of the corrected data to the MBIST circuitry.
However, Engin in the same the field of endeavor teaches a replica MBIST, wherein the replica MBIST: receives the corrected data and the multi-bit error flag (see paragraph [0004], herein the ECC decoder is further coupled to an error map in the SRAM module and the ECC decoder is configured to write back decoding information to the error map); selectively modifies the corrected data based on the multi-bit error flag; and provides a result of the selective modification of the corrected data to the MBIST circuitry (see paragraph [0010], herein information regarding the error correction is written back to an error map and used to identify weak cells; paragraph [0041], herein the ECC decoder is also configured to determine the state of cells in the SRAM (e.g., if cells in the SRAM module are weak or otherwise unable to store data) and to write information regarding the state of the cells back to an error map 524 stored in the SRAM module. The ECC decoder can determine the state of a cell by, for example, tracking the number of times a bit that the cell is storing needs to be corrected (e.g., should be a 1, but reads as a 0) during decoding and error-correction. For example, if after four refresh attempts, a bit stored in a particular cell has needed correcting each attempt, the ECC decoder can determine that the particular cell is weak and pass information regarding the state of the particular cell back to the SRAM module to be stored in the error map).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Kumar-Jung as combined with the teachings of Engin by including a replica MBIST, wherein the replica MBIST: receives the corrected data and the multi-bit error flag; selectively modifies the corrected data based on the multi-bit error flag; and provides a result of the selective modification of the corrected data to the MBIST circuitry.
This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the a replica MBIST, wherein the replica MBIST: receives the corrected data and the multi-bit error flag; selectively modifies the corrected data based on the multi-bit error flag; and provides a result of the selective modification of the corrected data to the MBIST circuitry would have improved the system performance.
As per claim 16:
Kumar teaches that wherein: the ECC encoder is configured to input bus swap with the memory; and the memory is configured to output bus swap with the ECC decoder (see paragraph [0056], herein An ECC encoder 140 is coupled for input from bus 120 and generates parity to a parity storage memory 150. Read data from memory 130 and parity from parity storage memory 150 are coupled to an ECC decoder 160 which in turn provides corrected data to the bus master 110, and Fig. 1).
As per claim 17:
Kumar teaches that wherein: the ECC circuitry is configured to conduct data error checks in multiple passes; and a single pass comprises the input data from MBIST circuitry through the ECC circuitry, wherein the corrected data is outputted (see paragraph [0048], herein the decoder checks for any errors which occur on the bus during data transmission due to issues like crosstalk, power supply droop, etc., that can also be corrected, and paragraph [0060], herein ECC parity decoder 262 provides error data to an XOR block 264 that corrects the data from main memory 230 and supplies the corrected data to the accessing circuits such as DMA, processor, or other system module).
As per claim 18:
Kumar teaches that wherein: the ECC circuitry performs a first pass without bus swapping and a second pass with bus swapping to increase error detection; and the multiple passes are configured to enhance error detection coverage and ensure comprehensive stress testing of bitcells in the memory during MBIST (see Fig. 1, ECC encoder 140 receives input from bus 120 and generates parity to a parity storage memory 150, and ECC decoder 160 reads data from memory 130).
As per claim 19:
Kumar teaches that wherein: in the first pass the ECC encoder generates and adds the check bits to a beginning of the input data creating a first data sequence (see paragraph [0056], herein An ECC encoder 140 is coupled for input from bus 120 and generates parity to a parity storage memory 150; the MBIST circuitry is configured to test the first data sequence (see paragraph [0055], herein These failures and effects motivate error correction improvements for use during manufacturing test and built-in self-test (BIST) in the field. Error correcting codes (ECC) can address both these problems); and error detection is performed by comparing the input data to the corrected data (see paragraph [0017], herein enabling the ECC circuit, reading data and parity from the memory, operating the ECC circuit to detect error in the data read from the memory using the parity, operating the ECC circuit to independently generate parity for the data during the reading of the data from the memory and comparing the generated parity with the parity that is read from the memory, and updating an error report with the results of the comparing).
As per claim 20:
Kumar teaches that wherein: in the second pass the ECC encoder generates a second data sequence by adding the check bits to an end of the input data (see paragraph [0056], herein An ECC encoder 140 is coupled for input from bus 120 and generates parity to a parity storage memory 150); the MBIST circuitry is configured to test the second data sequence see paragraph [0055], herein These failures and effects motivate error correction improvements for use during manufacturing test and built-in self-test (BIST) in the field. Error correcting codes (ECC) can address both these problems); and error detection is performed by comparing the input data to the corrected data (see paragraph [0017], herein enabling the ECC circuit, reading data and parity from the memory, operating the ECC circuit to detect error in the data read from the memory using the parity, operating the ECC circuit to independently generate parity for the data during the reading of the data from the memory and comparing the generated parity with the parity that is read from the memory, and updating an error report with the results of the comparing).
Allowable Subject Matter
10. Claims 3, 11, and 15 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Dependent claims 4-5, and 13 depend from on claim 4, and 11 respectively and inherently include limitations therein and therefore are allowed as well.
Examiner Notes
11. When amending the claims, applicants are respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Prior Art
12. The prior art of record, considered pertinent to the applicant’s disclosure, is listed in the attached PTO-892 form.
Conclusion
13. Any inquiry concerning this communication or earlier communications from the examiner should be directed to OSMAN ALSHACK whose telephone number is (571)272-2069. The examiner can normally be reached on MON-FRI 8:30 AM-5:00 PM EST, also please fax interview request to (571) 273- 2069. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ALBERT DECADY can be reached on 5712723819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/OSMAN M ALSHACK/Examiner, Art Unit 2112
Prosecution Insights