Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are present for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, and 4-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Derner et al. (US 20190279984 A1).
Regarding claim 1: Derner discloses an apparatus comprising memory cells (FIG. 2) comprising: a semiconductor wafer (par. 33) comprising: a plurality of memory arrays (8, par. 17); a plurality of control regions (areas comprising the sense amplifiers SA, FIG. 2), each control region of the plurality of control regions extending along a first direction (along bitlines BL direction, FIG. 2) and comprising control circuitry (sense amplifiers SA, FIG. 2), associated with accessing memory arrays of the plurality of memory arrays (memory cells of memory arrays e.g. 48, FIG. 2) that are located along a second direction (along wordlines WL direction, FIG. 2) from the control region; a plurality of contact regions (par. 24, FIG. 2), each contact region of the plurality of contact regions extending along the second direction (along wordlines WL direction, FIG. 2) and comprising contacts (e.g. 40, 42, 44, FIG. 2) configured for communicating signaling associated with accessing memory arrays of the plurality of memory arrays (contact regions connected to the memory cells of memory array, FIG. 2) that are located along the first direction (along bitlines BL direction, FIG. 2) from the contact region; a plurality of first separation regions (region between defined control regions, FIG. 2) extending along the first direction (along bitlines BL direction separating SA2 from SA1 and SA3, FIG. 2), each first separation region of the plurality of first separation regions located between a respective first pair of control regions (pair e.g. SA1 and SA2, FIG. 2) of the plurality of control regions; and a plurality of second separation regions (area between contact regions, FIG. 2) extending along the second direction (direction along wordlines WL, FIG. 2), each second separation region of the plurality of second separation regions located between a respective pair of contact regions (area between contact region pairs e.g. contact regions within 20 and 21, 22 and 23, FIG. 2) of the plurality of contact regions.
Regarding claim 2: Derner discloses an apparatus wherein the semiconductor wafer is configured in accordance with a plurality of units (memory array architecture can be split into modular subsections sharing control and contact regions, where the subsections can be identical to each other, FIG. 2), each unit of the plurality of units comprising: a respective subset of one or more memory arrays (memory array 8 can be divided into subsets of cells, FIG. 2) of the plurality of memory arrays; a respective portion of a contact region (portion of contact region e.g. 40, 42, 44, FIG. 2) of the plurality of contact regions, the memory arrays of the respective subset located along the first direction from the respective portion of the contact region (subset of memory cells of memory array located along the first direction of bitlines BL from contact region, FIG. 2), and the contacts of the respective portion of the contact region (contact points of contact regions, FIG. 2) associated with signaling of a respective plurality of channels (wordline or bitline pairs acting as channels, par. 27 and 50); and a respective portion of a control region (portion of defined control regions as with sense amplifiers, FIG. 2) of the plurality of control regions, the memory arrays of the respective subset located along the second direction (subset memory cells of the memory array located along second direction wordlines WL, FIG. 2) from the respective portion of the contact region, and the control circuitry (sense amplifiers SA, FIG. 2) of the respective portion of the contact region associated with the signaling of the respective plurality of channels (wordline or bitline pairs acting as channels, par. 27 and 50).
Regarding claim 4: Derner discloses an apparatus wherein: the plurality of control regions are arranged along the second direction according to a first pitch (the specific spacing between the defined control regions along the wordline WL direction, FIG. 2) and the plurality of first separation regions are arranged along the second direction according to the first pitch (region between defined control regions having a specific spacing between the repeating elements arranged along the wordline WL direction, FIG. 2); and the plurality of contact regions are arranged along the first direction according to a second pitch (the second specific spacing between the contact regions along the bitline BL direction, FIG. 2) and the plurality of second separation regions are arranged along the first direction according to the second pitch (the second specific spacing of the regions between contact regions arranged along the bitline BL direction, FIG. 2).
Regarding claim 5: Derner discloses an apparatus wherein each first separation region of the plurality of first separation regions comprises a respective scribe line (trenched isolation material may be provided as lines to segment into regions, par. 22) of the semiconductor wafer.
Regarding claim 6: Derner discloses an apparatus comprising memory cells (FIG. 2) comprising: a plurality of memory arrays (8, FIG. 2) of a memory die (assembly 10, FIG. 2); a plurality of channels (wordline or bitline pairs acting as channels, par. 27 and 50) of the memory die associated with accessing the plurality of memory arrays (associated with accessing the memory cells of the memory array, FIG. 2); one or more control regions (areas comprising the sense amplifiers SA, FIG. 2) of the memory die, each control region of the one or more control regions extending along a first direction (along bitlines BL direction, FIG. 2) and comprising control circuitry (sense amplifiers SA, FIG. 2) associated with accessing memory arrays of the plurality of memory arrays (sense amplifiers access memory cells of memory arrays e.g. 48, FIG. 2) that are located along a second direction (along wordlines WL direction, FIG. 2) from the control region; one or more contact regions (par. 24, FIG. 2) of the memory die, each contact region of the one or more contact regions extending along the second direction (along wordlines WL direction, FIG. 2) and comprising contacts (e.g. 40, 42, 44, FIG. 2) configured for communicating signaling associated with accessing memory arrays of the plurality of memory arrays (contact regions connected to the memory cells of memory array, FIG. 2) that are located along the first direction (along bitlines BL direction, FIG. 2) from the contact region; and one or more separation regions of the memory die (regions between defined control regions, FIG. 2) extending along the first direction (along bitlines BL direction separating SA2 from SA1 and SA3, FIG. 2), each separation region of the one or more separation regions disposed between a control region of the one or more control regions and a respective border of the apparatus (separation region between defined control region and border of neighboring subsections of the memory array or memory die assembly, FIG. 2).
Regarding claim 7: Derner discloses an apparatus further comprising: one or more second separation regions of the memory die (area between contact regions, FIG. 2) extending along the second direction (direction along wordlines WL, FIG. 2), each second separation region of the one or more second separation regions disposed between a respective pair of contact regions of the one or more contact regions (area between pairs of contact regions, FIG. 2).
Regarding claim 8: Derner discloses an apparatus wherein the apparatus is configured in accordance with one or more units (modular subsections made out of the divided memory array where each subsection with its own control and contact region, FIG. 2), each unit of the one or more units comprising: a respective subset of one or more memory arrays (subset of memory array, FIG. 2) of the plurality of memory arrays and a respective subset of one or more channels (subset of wordline or bitline pairs acting as channels, FIG. 2) of the plurality of channels; a respective portion of a contact region (portion of contact regions, par. 24, FIG. 2) of the one or more contact regions, the memory arrays of the respective subset located along the first direction (along bitlines BL direction, FIG. 2) from the respective portion of the contact region (contact points of contact regions, FIG. 2), and the contacts of the respective portion of the contact region associated with signaling of the respective subset of one or more channels (contact regions along the bitline BL channels, FIG. 2); and a respective portion of a control region (portion of defined control region, FIG. 2) of the one or more control regions, the memory arrays of the respective subset of one or more memory arrays located along the second direction (along wordlines WL direction, FIG. 2) from the respective portion of the contact region, and the control circuitry (sense amplifiers SA, FIG. 2) of the respective portion of the contact region associated with the signaling of the respective subset of one or more channels (defined control regions along the bitline BL channels, FIG. 2).
Regarding claim 9: Derner discloses an apparatus, wherein each separation region of the one or more separation regions comprises a respective scribe line of the apparatus (trenched isolation material may be provided as lines to segment into regions, par. 22).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Derner et al. (US 20190279984 A1) in view of Riley et al. (US 20190198127 A1).
Regarding claim s 3 and 12: Derner does not disclose an apparatus, wherein for at least one unit of the plurality of units, the respective portion of the control region comprises one or more fuse arrays, one or more pumps, one or more regulators, one or more voltage sources, or a combination thereof for operating the respective subset of one or more memory arrays.
Riley does disclose a memory device utilizing fuse array systems, wherein for at least one unit of the plurality of units (memory device may use memory modules, par. 17), the respective portion of the control region comprises one or more fuse arrays (memory device utilizing fuse arrays, par. 2), one or more pumps, one or more regulators, one or more voltage sources, or a combination thereof for operating the respective subset of one or more memory arrays.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Derner with eh configuration of Riley to allow the memory device to have the module units utilize fuse arrays in their control regions as in the claimed invention.
Claim(s) 10-11, and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Derner et al. (US 20190279984 A1) in view of Grivna et al. (US 20090267204 A1).
Regarding claim 10: Derner discloses a method for an apparatus which comprises memory cells (FIG. 2), comprising: providing a semiconductor wafer (par. 33) comprising: a plurality of memory arrays (8, par. 17); a plurality of control regions (areas comprising the sense amplifiers SA, FIG. 2), each control region of the plurality of control regions extending along a first direction (along bitlines BL direction, FIG. 2) and comprising control circuitry (sense amplifiers SA, FIG. 2) associated with accessing memory arrays of the plurality of memory arrays (sense amplifiers access memory cells of memory arrays e.g. 48, FIG. 2) that are located along a second direction (along wordlines WL direction, FIG. 2) from the control region; a plurality of contact regions (par. 24, FIG. 2), each contact region of the plurality of contact regions extending along the second direction (along wordlines WL direction, FIG. 2) and comprising contacts (e.g. 40, 42, 44, FIG. 2) configured for communicating signaling associated with accessing memory arrays of the plurality of memory arrays (contact regions connected to the memory cells of memory array, FIG. 2) that are located along the first direction (along bitlines BL direction, FIG. 2) from the contact region; a plurality of first separation regions (region between defined control regions, FIG. 2) extending along the first direction (along bitlines BL direction separating SA2 from SA1 and SA3, FIG. 2), each first separation region of the plurality of first separation regions located between a respective first pair of control regions (pair e.g. SA1 and SA2, FIG. 2) of the plurality of control regions; and a plurality of second separation regions (area between contact regions, FIG. 2) extending along the second direction (direction along wordlines WL, FIG. 2), each second separation region of the plurality of second separation regions located between a respective pair of contact regions (area between contact region pairs e.g. contact regions within 20 and 21, 22 and 23, FIG. 2) of the plurality of contact regions; and each die of the plurality of dies comprising a respective subset of the plurality of memory arrays (subset of memory array, FIG. 2), a respective portion of a control region of the plurality of control regions (portion of defined control region, FIG. 2) associated with the respective subset of the plurality of memory arrays, and a respective portion of a contact region of the plurality of contact regions (portion of contact regions, par. 24, FIG. 2).
Derner does not disclose forming a plurality of dies from the semiconductor wafer based at least in part on separating the semiconductor wafer along at least one second separation region of the plurality of second separation regions.
Grivna does disclose a method of singulating semiconductor dies comprising: forming a plurality of dies from the semiconductor wafer (wafer 25) based at least in part on separating the semiconductor wafer (wafer 25 singulated to separate the dice on wafer 25, par. 19) along at least one second separation region of the plurality of second separation regions (scribing the wafer through a scribe grid akin to a defined separation region, par. 19, FIG. 6).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Derner with the configuration of Grivna to add the step of singulating the memory array into units along the separation regions as in the claimed invention.
Regarding claim 11: Derner discloses a method, wherein the semiconductor wafer is configured in accordance with a plurality of units (memory array architecture can be split into modular subsections sharing control and contact regions, where the subsections can be identical to each other, FIG. 2), each unit of the plurality of units comprising: a respective subset of one or more memory arrays (memory array 8 can be divided into subsets of cells, FIG. 2) of the plurality of memory arrays; a respective portion of a contact region (portion of contact region e.g. 40, 42, 44, FIG. 2) of the plurality of contact regions, the memory arrays of the respective subset located along the first direction (along bitlines BL direction, FIG. 2) from the respective portion of the contact region (subset of memory cells of memory array located along the first direction of bitlines BL from contact region, FIG. 2), and the contacts of the respective portion of the contact region (contact points of contact regions, FIG. 2) associated with signaling of a respective plurality of channels (wordline or bitline pairs acting as channels, par. 27 and 50); and a respective portion of a control region (portion of defined control regions as with sense amplifiers, FIG. 2) of the plurality of control regions, the memory arrays of the respective subset located along the second direction (subset memory cells of the memory array located along second direction wordlines WL, FIG. 2) from the respective portion of the contact region, and the control circuitry (sense amplifiers SA, FIG. 2) of the respective portion of the contact region associated with the signaling of the respective plurality of channels (wordline or bitline pairs acting as channels, par. 27 and 50).
Regarding claim 15: Derner does not disclose a method, wherein the plurality of dies comprises a first die having a first portion of a unit of the plurality of units, and a second die having a second portion of the unit.
Grivna does disclose a method of singulating semiconductor dies comprising: forming a plurality of dies from the semiconductor wafer (wafer 25) based at least in part on separating the semiconductor wafer (wafer 25 singulated to separate the dice on wafer 25, par. 19) along at least one second separation region of the plurality of second separation regions (scribing the wafer through a scribe grid akin to a defined separation region, par. 19, FIG. 6).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Derner with the configuration of Grivna such that the dies after the singulation results in one die having a first portion of units of the original wafer and the other die having a different portion of the original wafer.
Regarding claim 16: Derner discloses a method, wherein: the plurality of control regions are arranged according to a first pitch (the specific spacing between the defined control regions along the wordline WL direction, FIG. 2) and the plurality of first separation regions are arranged according to the first pitch (region between defined control regions having a specific spacing between the repeating elements arranged along the wordline WL direction, FIG. 2); and the plurality of contact regions are arranged according to a second pitch (the second specific spacing between the contact regions along the bitline BL direction, FIG. 2) and the plurality of second separation regions are arranged according to the second pitch (the second specific spacing of the regions between contact regions arranged along the bitline BL direction, FIG. 2).
Regarding claim 17: Derner disclose a method, wherein a die of the plurality of dies comprises a plurality of portions of respective control regions of the plurality of control regions (portion of defined control regions as with sense amplifiers, FIG. 2). It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention that the resulting plurality of dies after singulation would comprise portions of the control regions.
Regarding claim 18: Derner does disclose a method, further comprising:forming the plurality of dies based at least in part on cutting the semiconductor wafer along a control region (trenched isolation material may be provided as lines which are along separation regions and thus along adjacent control regions, par. 22) of the plurality of control regions.
Regarding claim 19: Derner discloses a method, wherein the plurality of first separation regions comprises respective scribe lines of the semiconductor wafer (trenched isolation material may be provided as lines to segment into regions, par. 22).
Regarding claim 20: Derner does not disclose a method, wherein a first die having a first dimension along the first direction and a second dimension along the second direction; and a second die having a third dimension along the first direction and a fourth dimension along the second direction, wherein the third dimension is different than the first dimension, or the fourth dimension is different than the second dimension, or both.
Grivna does disclose a method of singulating semiconductor dies comprising: forming a plurality of dies from the semiconductor wafer (wafer 25) based at least in part on separating the semiconductor wafer (wafer 25 singulated to separate the dice on wafer 25, par. 19) along at least one second separation region of the plurality of second separation regions (scribing the wafer through a scribe grid akin to a defined separation region, par. 19, FIG. 6). It would have been obvious to one of ordinary skill in the art that the dimensions of the resulting dies in relation to one another after being separated is a matter of design choice.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Derner with the configuration of Grivna to add the step of singulating the memory array into units along the separation regions as in the claimed invention.
Claim(s) 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Derner et al. (US 20190279984 A1) in view of Grivna et al. (US 20090267204 A1), in further view of Jeddeloh (US 20180374557 A1).
Regarding claim 13: Derner and Grivna do not disclose a method, further comprising: forming the plurality of dies based at least in part on identifying one or more defects associated with a unit of the plurality of units.
Jeddeloh does disclose a memory device for managing error regions of memory arrays, comprising: forming the plurality of dies based at least in part on identifying one or more defects (error data associated with errors identified on the memory array are used to remove defective memory portions, par. 31-37) associated with a unit of the plurality of units.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Derner and Grivna with the configuration of Jeddeloh to allow the system to monitor and detect problematic defects within the memory arrays to ensure efficient operation.
Regarding claim 14: : Derner and Grivna do not disclose a method, wherein identifying the one or more defects comprises: reading a stored indication of the one or more defects from a storage location of the semiconductor wafer.
Jeddeloh does disclose a memory device for managing error regions of memory arrays, comprising reading a stored indication of the one or more defects from a storage location (error data within a memory map is stored locally on the memory device, par. 33 and 47) of the semiconductor wafer.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Derner and Grivna with the configuration of Jeddeloh to allow the memory device to store recorded defect error data to be used as in the claimed invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY THINH TANG whose telephone number is (571)272-6845. The examiner can normally be reached Monday-Friday 7:30-5:00 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTHONY THINH TANG/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
Prosecution Insights