NON-FINAL REJECTION, FIRST DETAILED ACTION
Status of Prosecution
The present application, 18/401,256 filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The application was filed on December 29, 2023. PCT/US24/57992 was filed subsequently on Nov. 29, 2024.
Claims 1-20 are pending and all are rejected. Claims 1 and 13 are independent.
Status of the Claims
Claims 1-20 are rejected under 35 U.S.C. § 101 because the claimed invention is directed to an abstract idea without significantly more.
Claims 1-2, 4-9. 12-13, 15-16 and 18 are rejected under 35 USC. § 103 as being unpatentable over non-patent literature, Timofejevs et al. (“Timofejevs”), WO 2021/262023A1, published in Dec. 30, 2021 in view of view of non-patent literature, Okada, et al. (“Okada”), “A Dynamic Reconfigurable RF Circuit Architecture” published in 2015.
Claims 3, 10-11, 14 and 17 are rejected under 35 USC. § 103 as being unpatentable over Timofejevs in view of view of Okada in further view of Chang et al. (“Chang”), United States Patent Application Publication 2020/0372330A1 published on Nov. 26, 2020.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A.
Claims 1-2, 4-9. 12-13, 15-16 and 18 are rejected under 35 USC. § 103 as being unpatentable over non-patent literature, Timofejevs et al. (“Timofejevs”), WO 2021/262023A1, published in Dec. 30, 2021 in view of view of non-patent literature, Okada, et al. (“Okada”), “A Dynamic Reconfigurable RF Circuit Architecture” published in 2015.
As to Claim 1, Timofejevs teaches: A method, comprising:
sequentially implementing each of a plurality of layers of a neural network using a collection of resistors and a collection of amplifiers (Timofejevs: Fig. 27A, par. 0223, for a multilayer perceptron, each layer is considered for each layer sequentially; par. 00245, a collection of resistor values as defined by {Rmin, Rmax} is used; par. 0242, the amplifiers are operational that represent analog neurons connected to the resistor (weights and/or biases) of the neurons), including for each of the plurality of layers:
extracting, from memory, a plurality of layer parameters corresponding to a plurality of weights of the respective layer (Timofejevs: pars. 0288-90, a weight matrix is used (i.e. layer parameters corresponding to a plurality of weights);
in accordance with the plurality of layer parameters:
selecting a plurality of resistor [values] from the collection of resistors;
selecting a plurality of amplifiers from the collection of amplifiers, the plurality of amplifiers electrically coupled to the plurality of resistors(Timofejevs: par. 0288, at step [2714], a schematic model for implementing the equivalent analog network is generated, based on selecting component values for the analog components); and
forming a set of input resistors from the plurality of resistors, wherein the set of input resistors are electrically coupled to the plurality of amplifiers to form a neural layer circuit (Timofejevs: par. 0289, a lithographic mask is generated based on the above information for a circuit implementing the analog network)
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Timofejevs may not explicitly teach: selecting a plurality of resistors (not values) from the collection of resistors;
selecting a plurality of amplifiers from the collection of amplifiers, the plurality of amplifiers electrically coupled to the plurality of resistors;
Okada teaches in general concepts related to a dynamic recognifgurable architecture for analog RF circuits (Okada: Abstract). Specifically, Okada teaches a reconfirugable circuit that allows for the use of variable passive components and to switch the components dynamically (Okada: Abstract).
It would have been obvious to a person having ordinary skill in the art at a time before the effective filing date of the invention to have modified the Timofejevs device by implementing the circuit configuration of components (resistors, amplifiers) by allowing for a reconfigurable architecture as taught and disclosed by Okada. Such a person would have been motivated to do so with a reasonable expectation of success to do so to allow for a generalized and flexible by reducing costs for the circuits (Okada: Introduction).
As to Claim 2, Timofejevs and Okada teach the limitations of claim 1.
Timofejevs further teaches: obtaining a plurality of input signals for the neural layer circuit via the plurality of resistors; and
generating, by the neural layer circuit, a plurality of output signals from the plurality of input signals (Timfejevs: par. 0048, “Each operational amplifier represents an analog neuron of the equivalent analog network, and each resistor represents a connection between two analog neurons.”; pars. 0064-65, analog signals, output are measured).
As to Claim 4, Timofejevs and Okada teach the limitations of claim 1.
Timofejevs and Okada as combined further teaches: wherein the plurality of layers includes a first layer and a second layer (Timofejevs: par. 0192-94 the algorithm MPL2TNN1 applies an algorithm to construct a T-neural network from neurons on a layer-by-layer fashion), and forming the set of input resistors for each of the plurality of layers further comprises:
selecting a first subset of resistors from the collection of resistors to form the set of input resistors of the first layer; and
selecting a second subset of resistors from the collection of resistors to form the set of input resistors of the second layer (Okada as combined with Timofejevs allows for the selection of the physical resistors for the creation of the layers).
As to Claim 5, Timofejevs and Okada teach the limitations of claim 4.
Timofejevs and Okada as combined further teaches: wherein the set of input resistors of the first layer has a different number of resistors from the set of input resistors of the second layer (Examiner asserts that this would have been design choice or in the alternative, the applied references contemplate such a difference in number of resistors for each layer, per the algorithm considering the different parameters for different number of resistors, neurons, etc.).
As to Claim 6, Timofejevs and Okada teach the limitations of claim 4.
Timofejevs and Okada as combined further teaches: wherein at least one of the set of input resistors of the first layer has a different resistance value from a corresponding input resistor of the second layer (Examiner asserts that this would have been design choice or in the alternative, the applied references contemplate such a difference in resistance values for each layer, per the algorithm considering the different parameters for different resistance values,, neurons, etc.).
As to Claim 7, Timofejevs and Okada teach the limitations of claim 4.
Timofejevs and Okada as combined further teaches: wherein the first subset of resistors of the first layer has a different number of resistors from the second subset of resistors of the second layer (Examiner asserts that this would have been design choice or in the alternative, the applied references contemplate such a difference in number of resistors for each layer, per the algorithm considering the different parameters for different number of resistors, neurons, etc.).
As to Claim 8, Timofejevs and Okada teach the limitations of claim 4.
Timofejevs and Okada as combined further teaches: wherein at least one of the first subset of resistors of the first layer has a different resistance value from a corresponding resistor of the second subset of resistors of the second layer (Examiner asserts that this would have been design choice or in the alternative, the applied references contemplate such a difference in resistance values for each layer, per the algorithm considering the different parameters for different resistance values,, neurons, etc.).
As to Claim 9, Timofejevs and Okada teach the limitations of claim 4.
Timofejevs and Okada as combined further teaches: wherein the first subset of resistors of the first layer is identical to the second subset of resistors of the second layer, and is coupled differently from the second subset of resistors of the second layer (Examiner asserts that this would have been design choice or in the alternative, the applied references contemplate such a difference in resistors for each layer, per the algorithm considering the different parameters for different resistance values,, neurons, etc.).
As to Claim 12, Timofejevs and Okada teach the limitations of claim 4.
Timofejevs and Okada as combined further teaches: wherein the second layer is separated from the first layer by one or more intermediate layers (Examiner asserts that the number of layers may include intermediate layers, per the discussion of the multi-level perceptron algorithm).
As to Claim 13, it is rejected for similar reasons as claim 1.
As to Claim 15, Timofejevs and Okada teach the limitations of claim 13.
Timofejevs and Okada as combined further teaches: wherein the neural network further includes an alternative layer distinct from the plurality of layers (Timofejevs: par. 0016, there are sublayers).
Timofejevs and Okada may not explicitly teach: the alternative layer is not implemented by the collection of resistors and the collection of amplifiers.
Timofejevs does however teach that certain layers may have different resistor value ranges instead (Timojefevs: par. 00438, the R- and R+ values are chosen differently).
It would have been obvious to a person having ordinary skill in the art at a time before the effective filing date of the invention to have modified Timofejevs by implementing a specific layer as an alternative layer with a different collection of resistor values as taught and suggested by the cited portion of Timofejevs. Such a person would have done so with an expectation for success, because of the desire for different functional layers with different resistance levels.
As to Claim 16, Timofejevs and Okada teach the limitations of claim 15.
Timofejevs and Okada as combined further teaches: wherein the alternative layer is implemented by a distinct collection of resistors and a distinct collection of amplifiers electrically coupled to the distinct collection of resistors (As combined, Okada teaches a reconfirugable circuit that allows for the use of variable passive components and to switch the components dynamically).
As to Claim 18, Timofejevs and Okada teach the limitations of claim 13.
Timofejevs and Okada as combined further teaches: wherein each of the set of input resistors has a respective resistance value that is defined by the plurality of layer parameters to achieve a predefined precision level (Timofejevs: pars. 0030-31, the equation is satisfied within a predetermined precision level).
B.
Claims 3, 10-11, 14 and 17 are rejected under 35 USC. § 103 as being unpatentable over non-patent literature, Timofejevs et al. (“Timofejevs”), WO 2021/262023A1, published in Dec. 30, 2021 in view of view of non-patent literature, Okada, et al. (“Okada”), “A Dynamic Reconfigurable RF Circuit Architecture” published in 2015 in further view of Chang et al. (“Chang”), United States Patent Application Publication 2020/0372330A1 published on Nov. 26, 2020.
As to Claim 3, Timofejevs and Okada teach the limitations of claim 2.
Timofejevs and Okada may not explicitly teach: wherein each of the plurality of resistors has an input terminal and an alternative terminal, and forming the set of input resistors for each of the plurality of layers further comprises, for each of the plurality of input signals:
electrically coupling input terminals of a respective subset of the plurality of resistors to form a respective input interface for receiving the respective input signal, wherein a weight of the respective input signal depends on resistance values of the respective subset of the plurality of resistors.
Chang teaches in general concepts related to a control circuit for a neural network system, using memristive cells (Chang: Abstract). Specifically, each of the memristic e cells have multiple terminals, which can include supply voltage, connections to vit lines or control terminals connected with word lines (Chang: Abstract). Stored weight values are accordingly applied for accumulation operations (Chang: par. 0017, cl. 5, “The control circuit as claimed in claim 4, wherein a neuron connection weight is adjusted according to the tuned resistance value.”).
It would have been obvious to a person having ordinary skill in the art at a time before the effective filing date of the invention to have modified Timofejevs-Okada by implementing the resistors with multiple terminals and forming the resistors in layers and with weights respective of the input signals as taught and suggested by Chang. Such a person would have done so with an expectation for success, because of the need to allow for implementing a control circuit effectively (Chang: par. 0031).
As to Claim 10, Timofejevs and Okada teach the limitations of claim 4.
Timofejevs and Okada may not explicitly teach: temporarily storing a plurality of output signals of the first layer in memory;
extracting the plurality of output signals of the first layer from the memory; and
applying the plurality of output signals of the first layer extracted from the memory as a plurality of input signals of the second layer.
Chang teaches in general concepts related to a control circuit for a neural network system, using memristive cells (Chang: Abstract). Specifically, each of the memristic e cells have multiple terminals, which can include supply voltage, connections to vit lines or control terminals connected with word lines (Chang: Abstract). Stored weight values are accordingly applied for accumulation operations (Chang: par. 0017, cl. 5, “The control circuit as claimed in claim 4, wherein a neuron connection weight is adjusted according to the tuned resistance value.”). A register may be used to store the values temporarily (Chang: par. 0059). The neuron values are stored and then used accordingly (Chang: pars. 0062-63, The j registers 451-45} store the neuron values Do_l-Doj of the next layer.).
It would have been obvious to a person having ordinary skill in the art at a time before the effective filing date of the invention to have modified Timofejevs-Okada by implementing the resistors with multiple terminals and forming the resistors in layers and with weights respective of the input signals using registers as taught and suggested by Chang. Such a person would have done so with an expectation for success, because of the need to allow for implementing a control circuit effectively (Chang: par. 0031).
As to Claim 11, Timofejevs, Solomon and Khalil teach the limitations of claim 4.
Timofejevs, Solomon and Khalil as combined further teaches: temporarily holding a plurality of output signals generated by the first layer by flip-flop registers without being stored in the memory; and
applying the plurality of output signals of the first layer held by the flip-flop registers as a plurality of input signals of the second layer.
Chang teaches in general concepts related to a control circuit for a neural network system, using memristive cells (Chang: Abstract). Specifically, each of the memristic e cells have multiple terminals, which can include supply voltage, connections to vit lines or control terminals connected with word lines (Chang: Abstract). Stored weight values are accordingly applied for accumulation operations (Chang: par. 0017, cl. 5, “The control circuit as claimed in claim 4, wherein a neuron connection weight is adjusted according to the tuned resistance value.”). A register may be used to store the values temporarily (Chang: par. 0059). The neuron values are stored and then used accordingly (Chang: pars. 0062-63, The j registers 451-45} store the neuron values Do_l-Doj of the next layer.).
It would have been obvious to a person having ordinary skill in the art at a time before the effective filing date of the invention to have modified Timofejevs-Okada by implementing the resistors with multiple terminals and forming the resistors in layers and with weights respective of the input signals using registers as taught and suggested by Chang. Such a person would have done so with an expectation for success, because of the need to allow for implementing a control circuit effectively (Chang: par. 0031).
As to Claim 14, Timofejevs and Okada teach the limitations of claim 13.
Timofejevs and Okada may not explicitly teach: wherein each of the plurality of resistors has an input terminal and an alternative terminal, and forming the set of input resistors for each of the plurality of layers further comprises:
electrically coupling each of a plurality of input signals to the input terminal of a respective one of a subset of the plurality of resistors for receiving the respective input signal, wherein a respective weight of each input signal depends partially on a resistance value of the respective one of the subset of the plurality of resistors; and
coupling the alternative terminal of each of the subset of the plurality of resistors to a respective input interface of a respective amplifier.
Chang teaches in general concepts related to a control circuit for a neural network system, using memristive cells (Chang: Abstract). Specifically, each of the memristic e cells have multiple terminals, which can include supply voltage, connections to vit lines or control terminals connected with word lines (Chang: Abstract). Stored weight values are accordingly applied for accumulation operations (Chang: par. 0017, cl. 5, “The control circuit as claimed in claim 4, wherein a neuron connection weight is adjusted according to the tuned resistance value.”). A register may be used to store the values temporarily (Chang: par. 0059). The neuron values are stored and then used accordingly (Chang: pars. 0062-63, The j registers 451-45} store the neuron values Do_l-Doj of the next layer.).
It would have been obvious to a person having ordinary skill in the art at a time before the effective filing date of the invention to have modified Timofejevs-Okada by implementing the resistors with multiple terminals and forming the resistors in layers and with weights respective of the input signals using registers as taught and suggested by Chang. Such a person would have done so with an expectation for success, because of the need to allow for implementing a control circuit effectively (Chang: par. 0031).
As to Claim 17, Timofejevs and Okada teach the limitations of claim 13.
Timofejevs and Okada may not explicitly teach: wherein each of the input resistors has two terminals including a first terminal for receiving a respective input signal and a second terminal coupled to an input of a respective amplifier.
Chang teaches in general concepts related to a control circuit for a neural network system, using memristive cells (Chang: Abstract). Specifically, each of the memristic e cells have multiple terminals, which can include supply voltage, connections to vit lines or control terminals connected with word lines (Chang: Abstract). Stored weight values are accordingly applied for accumulation operations (Chang: par. 0017, cl. 5, “The control circuit as claimed in claim 4, wherein a neuron connection weight is adjusted according to the tuned resistance value.”).
It would have been obvious to a person having ordinary skill in the art at a time before the effective filing date of the invention to have modified Timofejevs-Okada by implementing the resistors with multiple terminals and forming the resistors in layers and with weights respective of the input signals as taught and suggested by Chang. Such a person would have done so with an expectation for success, because of the need to allow for implementing a control circuit effectively (Chang: par. 0031).
As to Claim 19, Timofejevs and Okada teach the limitations of claim 13.
Timofejevs and Okada may not explicitly teach: wherein the plurality of resistors includes a first resistor having a variable resistance.
Chang teaches in general concepts related to a control circuit for a neural network system, using memristive cells (Chang: Abstract). Specifically, each of the memristic e cells have multiple terminals, which can include supply voltage, connections to vit lines or control terminals connected with word lines (Chang: Abstract). Stored weight values are accordingly applied for accumulation operations (Chang: par. 0017, cl. 5, “The control circuit as claimed in claim 4, wherein a neuron connection weight is adjusted according to the tuned resistance value.”). The resistors are variable (Chang: par. 0024, each electrical conductance element comprises a variable resistor).
It would have been obvious to a person having ordinary skill in the art at a time before the effective filing date of the invention to have modified Timofejevs-Okada by implementing the resistors with variable conductance as taught and suggested by Chang. Such a person would have done so with an expectation for success, because of the need to allow for implementing a control circuit effectively (Chang: par. 0031).
As to Claim 20, Timofejevs and Okada teach the limitations of claim 13.
Timofejevs and Okada may not explicitly teach: wherein a subset of the plurality of resistors is selected from a crossbar array of resistive elements having a plurality of word lines, a plurality of bit lines, and a plurality of resistive elements, and wherein each resistive element is located at a cross point of, and electrically coupled between, a respective word line and a respective bit line.
Chang teaches in general concepts related to a control circuit for a neural network system, using memristive cells (Chang: Abstract). Specifically, each of the memristic e cells have multiple terminals, which can include supply voltage, connections to vit lines or control terminals connected with word lines (Chang: Abstract). Stored weight values are accordingly applied for accumulation operations (Chang: par. 0017, cl. 5, “The control circuit as claimed in claim 4, wherein a neuron connection weight is adjusted according to the tuned resistance value.”). A register may be used to store the values temporarily (Chang: par. 0059). The neuron values are stored and then used accordingly (Chang: pars. 0062-63, The j registers 451-45} store the neuron values Do_l-Doj of the next layer.). A cell array with plural memristive cells is a crossbar (Chang: par. 0054).
It would have been obvious to a person having ordinary skill in the art at a time before the effective filing date of the invention to have modified Timofejevs-Okada by implementing the resistors with multiple terminals and forming the resistors in layers and with weights respective of the input signals using registers as taught and suggested by Chang. Such a person would have done so with an expectation for success, because of the need to allow for implementing a control circuit effectively (Chang: par. 0031).
Conclusion
Additional prior art: Khalil, K., Eldash, O., Dey, B., Kumar, A., & Bayoumi, M. (2019, August). A novel reconfigurable hardware architecture of neural network. In 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) (pp. 618-621). IEEE. (Year: 2019).
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/JAMES T TSAI/ Primary Examiner, Art Unit 2147
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