DETAILED ACTION
This office action is in response to arguments filed on 8/14/2026.
Claims 1 – 30 are pending.
Claims 1 – 17 and 28 – 30 are no longer interpreted under 35 USC 112(f) in view of the arguments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 – 10, 13 – 25 and 27 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Haugh (US 20060010353, prior art part of IDS Dated 5/7/2025).
As per claim 1, Haugh discloses: An interrupt controller in a processor-based system (Haugh [0065]: interrupt controller), the interrupt controller configured to:
receive temperature data related to a temperature for a plurality of central processing units (CPU) cores in a processor in the processor-based system; (Haugh figure 5, step 504 and [0059]: “receiving component temperatures. In one embodiment, component temperatures are received from one or more temperature sensors 140. Temperatures sensors 140 may be located on different components within the same or multiple computer systems.”; [0065]: “Many types of components are suitable for use with flow chart 500. Multiple processors systems, as described above, are a natural fit. In a multiprocessor system, an interrupt controller, for example, might include logic by which it routes system interrupts to the processor having the lowest temperature.”)
receive an interrupt in the processor-based system; (Haugh [0058]: “receiving a request for an activity to be performed. Activities may include any action that may be performed by any components, such as processing, storage of data, etc. The request may be received from any source and may be received by the temperature controller 102, the computer system, etc.”; [0065]: “Many types of components are suitable for use with flow chart 500. Multiple processors systems, as described above, are a natural fit. In a multiprocessor system, an interrupt controller, for example, might include logic by which it routes system interrupts to the processor having the lowest temperature”.)
determine one or more eligible CPU cores of the plurality of CPU cores eligible to handle the interrupt based on an interrupt routing policy; determine, based on the temperature data, a first set of eligible CPU cores of the one or more eligible CPU cores that would remain below a temperature threshold based on handling the interrupt; (Haugh [0060] – [0062]: “selecting component to perform an activity based at least partially on the component temperatures determined in element 506… element 508 will select the lowest temperature component to perform an activity. This, in many cases, will provide an effective thermal management system as the lowest temperature component is often the component most likely able to handle the new activity (and the associated heat generated). For example, if a four-processor computer system had processor temperatures of 100 degrees, 125 degrees, 130 degrees, and 150 degrees, a new processing request would be directed to the first processor (e.g., routing system interrupts to the first processor) in this embodiment… In another embodiment, components other than the highest temperature component are selected. As activities are directed away from the high temperature components and towards lower temperature components, the higher temperature component will have a tendency to cool down (and the lower temperature component may heat up). This brings all components closer to an average temperature and reduces the maximum temperature of any component. Using the processor example above, element 508 could prevent new processing requests from going to the fourth processor (at 150 degrees) until its temperature dropped enough so that it would not be the highest temperature processor.”. Examiner notes that the processors that are not the highest temp processor are mapped to the claimed “the first set of eligible CPU cores”.)
and communicate the interrupt to be received by the first set of eligible CPU cores. (Haugh [0064]: “element 510, where the function directs the component selected in element 508 to perform the requested activity”.)
As per claim 2, Haugh further discloses:
The interrupt controller of claim 1, further configured to not communicate the interrupt to the plurality of CPU cores not included in the first set of eligible CPU cores. (Haugh [0062]: “In another embodiment, components other than the highest temperature component are selected. As activities are directed away from the high temperature components and towards lower temperature components, the higher temperature component will have a tendency to cool down (and the lower temperature component may heat up). This brings all components closer to an average temperature and reduces the maximum temperature of any component. Using the processor example above, element 508 could prevent new processing requests from going to the fourth processor (at 150 degrees) until its temperature dropped enough so that it would not be the highest temperature processor.”)
As per claim 3, Haugh further discloses:
The interrupt controller of claim 1, configured to receive the temperature data related to the temperature for the plurality of CPU cores in response to receiving the interrupt. (Haugh figure 5, steps 502 – 504.)
As per claim 4, Haugh further discloses:
The interrupt controller of claim 1, configured to continuously receive the temperature data related to the temperature for the plurality of CPU cores in response to receiving the interrupt. (Haugh figure 5, step 504 and the recursive nature of the flow chart in figure 5.)
As per claim 5, Haugh further discloses:
The interrupt controller of claim 1, configured to: receive the temperature data by being configured to: receive temperature data related to a temperature for each of the plurality of CPU cores in a processor in the processor-based system; and determine the first set of eligible CPU cores by being configured to: determine, based on the temperature data for each CPU core of the one or more eligible CPU cores, the first set of eligible CPU cores of the one or more eligible CPU cores that would remain below the temperature threshold based on handling the interrupt. (Haugh [0060] – [0062].)
As per claim 6, Haugh further discloses:
The interrupt controller of claim 1, configured to determine the first set of eligible CPU cores by being configured to: determine, based on the temperature data, the first set eligible CPU cores of the one or more eligible CPU cores that would remain below a global temperature threshold established for the one or more eligible CPU cores based on handling the interrupt. (Haugh [0062]: “In another embodiment, components other than the highest temperature component are selected. As activities are directed away from the high temperature components and towards lower temperature components, the higher temperature component will have a tendency to cool down (and the lower temperature component may heat up). This brings all components closer to an average temperature and reduces the maximum temperature of any component. Using the processor example above, element 508 could prevent new processing requests from going to the fourth processor (at 150 degrees) until its temperature dropped enough so that it would not be the highest temperature processor.”)
As per claim 7, Haugh further discloses:
The interrupt controller of claim 1, configured to determine the first set of eligible CPU cores by being configured to: determine, based on the temperature data, a temperature time for each of the one or more eligible CPU cores to reach the temperature threshold based on handling the interrupt; and determine, based on the respective temperature time of each of the one or more eligible CPU cores, the first set of eligible CPU cores from the one or more eligible CPU cores that would remain below the temperature threshold based on its respective temperature time. (Haugh [0062]: “In another embodiment, components other than the highest temperature component are selected. As activities are directed away from the high temperature components and towards lower temperature components, the higher temperature component will have a tendency to cool down (and the lower temperature component may heat up). This brings all components closer to an average temperature and reduces the maximum temperature of any component. Using the processor example above, element 508 could prevent new processing requests from going to the fourth processor (at 150 degrees) until its temperature dropped enough so that it would not be the highest temperature processor.”)
As per claim 8, Haugh further discloses:
The interrupt controller of claim 1, configured to determine the first set of eligible CPU cores by being configured to: determine, based on the temperature data, the first set of eligible CPU cores of the one or more eligible CPU cores that would remain below the temperature threshold such that the processor would remain below a global temperature threshold, based on handling the interrupt. (Haugh [0060] – [0062])
As per claim 9, Haugh further discloses:
The interrupt controller of claim 1, configured to determine the first set of eligible CPU cores, by being configured to: determine, based on the temperature data, the first set of eligible CPU cores of the one or more eligible CPU cores that would remain below the same temperature threshold based on handling the interrupt. (Haugh [0060] – [0062])
As per claim 10, Haugh further discloses:
The interrupt controller of claim 1, configured to determine the first set of eligible CPU cores by being configured to: determine, based on the temperature data, the first set of eligible CPU cores of the one or more eligible CPU cores that would remain below a respective temperature threshold for each of the one or more eligible CPU cores based on handling the interrupt. (Haugh [0060] – [0062])
As per claim 13, Haugh further discloses:
The interrupt controller of claim 1, configured to determine the one or more eligible CPU cores by being configured to: determine, based on the temperature data of a CPU core cluster containing the first set of eligible CPU cores, the first set of eligible CPU cores that would remain below the temperature threshold of the CPU core cluster based on handling the interrupt. (Haugh [0060] – [0062])
As per claim 14, Haugh further discloses:
The interrupt controller of claim 1, further comprising: a temperature capture circuit configured to receive the temperature data related to the temperature for the plurality of CPU cores in the processor in the processor-based system; and a temperature-aware routing circuit configured to: determine, based on the temperature data, the first set of eligible CPU cores of the one or more eligible CPU cores that would remain below the temperature threshold based on handling the interrupt; and communicate the interrupt to be received by the first set of eligible CPU cores. (Haugh [0060] – [0062])
As per claim 15, Haugh further discloses:
The interrupt controller of claim 1, further comprising one or more thermal registers; and the interrupt controller further configured to: receive the temperature threshold; and store the received temperature threshold in the one or more thermal registers; the interrupt controller configured to determine, based on the temperature data, the first set of eligible CPU cores of the one or more eligible CPU cores that would remain below the temperature threshold based on handling the interrupt by being configured to: determine the first set of eligible CPU cores that would remain below the temperature threshold stored in the temperature threshold register. (Haugh [0060] – [0062]; [0031]: locally stored threshold temperature.)
As per claim 16, Haugh further discloses:
The interrupt controller of claim 1, further comprising a control unit circuit configured to store the temperature threshold for each CPU core of the plurality of CPU cores; and the interrupt controller configured to determine, based on the temperature data, the first set of eligible CPU cores of the one or more eligible CPU cores that would remain below the respective temperature threshold stored in the control unit circuit for each of the first set of eligible CPU cores, based on handling the interrupt. (Haugh [0060] – [0062]; [0031]: locally stored threshold temperature.)
As per claim 17, Haugh further discloses:
The interrupt controller of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer (Haugh figure 2); a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.
As per claim 18, it is the method variant of claim 1 and is therefore rejected under the same rationale.
As per claim 19, it is the method variant of claim 2 and is therefore rejected under the same rationale.
As per claim 20, it is the method variant of claim 3 and is therefore rejected under the same rationale.
As per claim 21, it is the method variant of claim 4 and is therefore rejected under the same rationale.
As per claim 22, it is the method variant of claim 5 and is therefore rejected under the same rationale.
As per claim 23, it is the method variant of claim 6 and is therefore rejected under the same rationale.
As per claim 24, it is the method variant of claim 7 and is therefore rejected under the same rationale.
As per claim 25, it is the method variant of claim 10 and is therefore rejected under the same rationale.
As per claim 27, it is the method variant of claim 13 and is therefore rejected under the same rationale.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11, 12 and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Haugh, in view of Aguilar et al (US 20070260415, prior art part of IDS dated 5/7/2025, hereinafter Aguilar).
As per claim 11, Haugh did not explicitly disclose:
The interrupt controller of claim 1, configured to determine the one or more eligible CPU cores by being configured to: determine the one or more eligible CPU cores, based on the temperature data of one or more proximity designated CPU cores to the first set of eligible CPU cores, that would remain below the temperature threshold based on handling the interrupt.
However, Aguilar teaches:
The interrupt controller of claim 1, configured to determine the one or more eligible CPU cores by being configured to: determine the one or more eligible CPU cores, based on the temperature data of one or more proximity designated CPU cores to the first set of eligible CPU cores, that would remain below the temperature threshold based on handling the interrupt. (Aguilar [0006] and [0090] – [0091])
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Aguilar into that of Haugh in order to determine the one or more eligible CPU cores, based on the temperature data of one or more proximity designated CPU cores to the first set of eligible CPU cores, that would remain below the temperature threshold based on handling the interrupt. Haugh [0006] teaches proximity based thermal consideration is a commonly known problem in the field to scheduling while minimizing power and thermal profiles, Aguilar [0006] and [0090] – [0091] teaches that the claimed limitations are merely commonly known steps to address the proximity based thermal issue, and thus applicants have merely claimed the combination of known parts in the field to achieve predictable results of minimize proximity based thermal impact and is therefore rejected under 35 USC 103.
As per claim 12, Haugh did not explicitly disclose:
The interrupt controller of claim 1, configured to determine the one or more eligible CPU cores by being configured to: determine, based on the temperature data of one or more proximity designated CPU cores to the first set of eligible CPU cores, the first set of eligible CPU cores, that would cause the one or more proximity designated CPU cores to remain below the temperature threshold based on the first set of eligible CPU cores handling the interrupt.
However, Aguilar teaches:
The interrupt controller of claim 1, configured to determine the one or more eligible CPU cores by being configured to: determine, based on the temperature data of one or more proximity designated CPU cores to the first set of eligible CPU cores, the first set of eligible CPU cores, that would cause the one or more proximity designated CPU cores to remain below the temperature threshold based on the first set of eligible CPU cores handling the interrupt. (Aguilar [0006] and [0090] – [0091])
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Aguilar into that of Haugh in order to determine, based on the temperature data of one or more proximity designated CPU cores to the first set of eligible CPU cores, the first set of eligible CPU cores, that would cause the one or more proximity designated CPU cores to remain below the temperature threshold based on the first set of eligible CPU cores handling the interrupt. Haugh [0006] teaches proximity based thermal consideration is a commonly known problem in the field to scheduling while minimizing power and thermal profiles, Aguilar [0006] and [0090] – [0091] teaches that the claimed limitations are merely commonly known steps to address the proximity based thermal issue, and thus applicants have merely claimed the combination of known parts in the field to achieve predictable results of minimize proximity based thermal impact and is therefore rejected under 35 USC 103.
As per claim 26, it is the method variant of claim 11 and is therefore rejected under the same rationale.
Claim(s) 28 – 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Haugh, in view of Kimelman (US 20100174886).
As per claim 28, Haugh discloses: A processor-based system, comprising:
a first processor comprising a plurality of first central processing unit (CPU) cores; (Haugh [0065]: “Many types of components are suitable for use with flow chart 500. Multiple processors systems, as described above, are a natural fit. In a multiprocessor system, an interrupt controller, for example, might include logic by which it routes system interrupts to the processor having the lowest temperature.”)
and a first interrupt controller configured to: receive first temperature data related to a temperature for the plurality of first CPU cores from one or more temperature sensors; (Haugh figure 5, step 504 and [0059]: “receiving component temperatures. In one embodiment, component temperatures are received from one or more temperature sensors 140. Temperatures sensors 140 may be located on different components within the same or multiple computer systems.”; [0065]: “Many types of components are suitable for use with flow chart 500. Multiple processors systems, as described above, are a natural fit. In a multiprocessor system, an interrupt controller, for example, might include logic by which it routes system interrupts to the processor having the lowest temperature.”)
receive a first interrupt from an interrupt generating device of the plurality of interrupt generating devices; (Haugh [0058]: “receiving a request for an activity to be performed. Activities may include any action that may be performed by any components, such as processing, storage of data, etc. The request may be received from any source and may be received by the temperature controller 102, the computer system, etc.”; [0065]: “Many types of components are suitable for use with flow chart 500. Multiple processors systems, as described above, are a natural fit. In a multiprocessor system, an interrupt controller, for example, might include logic by which it routes system interrupts to the processor having the lowest temperature”.)
determine one or more first eligible CPU cores of the plurality of first CPU cores eligible to handle the first interrupt based on a first interrupt routing policy; determine, based on the first temperature data, a first set of eligible CPU cores of the one or more first eligible CPU cores that would remain below a first temperature threshold based on handling the first interrupt; (Haugh [0060] – [0062]: “selecting component to perform an activity based at least partially on the component temperatures determined in element 506… element 508 will select the lowest temperature component to perform an activity. This, in many cases, will provide an effective thermal management system as the lowest temperature component is often the component most likely able to handle the new activity (and the associated heat generated). For example, if a four-processor computer system had processor temperatures of 100 degrees, 125 degrees, 130 degrees, and 150 degrees, a new processing request would be directed to the first processor (e.g., routing system interrupts to the first processor) in this embodiment… In another embodiment, components other than the highest temperature component are selected. As activities are directed away from the high temperature components and towards lower temperature components, the higher temperature component will have a tendency to cool down (and the lower temperature component may heat up). This brings all components closer to an average temperature and reduces the maximum temperature of any component. Using the processor example above, element 508 could prevent new processing requests from going to the fourth processor (at 150 degrees) until its temperature dropped enough so that it would not be the highest temperature processor.”. Examiner notes that the processors that are not the highest temp processor are mapped to the claimed “the first set of eligible CPU cores”.)
and communicate the first interrupt to be received by the first set of eligible CPU cores; (Haugh [0064]: “element 510, where the function directs the component selected in element 508 to perform the requested activity”.)
Haugh did not explicitly disclose
a plurality of interrupt generating devices each configured to generate an interrupt;
and each first eligible CPU core of the first set of eligible CPU cores configured to: receive the first interrupt; determine whether to service the first interrupt; and in response to determining to service the first interrupt, service the first interrupt.
However, Kimelman teaches:
a plurality of interrupt generating devices each configured to generate an interrupt; (Kimelman figure 3C)
and each first eligible CPU core of the first set of eligible CPU cores configured to: receive the first interrupt; determine whether to service the first interrupt; and in response to determining to service the first interrupt, service the first interrupt. (Kimelman [0023]: “Hyper-interrupt controller 310 feeds interrupts to the… data processor core… If the interrupt priority is below the priority of all four data processor cores 220, 230, 240 and 250, HIC 310 stalls the interrupt and holds it pending. If the interrupt priority is higher than the priority of one or more of data processor cores 220, 230, 240 and 250, HIC 310 routes the interrupt to the data processor core with the lowest priority. This ensures optimal use of data processor cores 220, 230, 240 and 250.”; Figure 3C and [0025]: “FIG. 3C illustrates interrupt controllers 323, 333, 343 and 353 of respective data processor cores 321, 331, 341 and 351 communicating via lines 327, 337 and 347. Using this communication interrupt controllers 323, 333, 343 and 353 handle the multiplexing of interrupts. This distributes interrupts among data processor cores 321, 331, 341 and 351 in the same manner as described above for HIC 310.”. Examiner notes that in the scenario of figure 3C, each IC for the processor would check for eligibility of the CPU its responsible for, and either forward or reject the interrupt based on the result of the check.)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kimelman into that of Haugh in order to have a plurality of interrupt generating devices each configured to generate an interrupt; and each first eligible CPU core of the first set of eligible CPU cores configured to: receive the first interrupt; determine whether to service the first interrupt; and in response to determining to service the first interrupt, service the first interrupt. Haugh [0065] teaches a interrupt controller routes interrupts to processors. Kimelman figure 3C teaches an alternative scenario where the interrupt controller are decentralized and paired to each processor and federate the servicing of interrupts between each other, using verification method such as compare interrupt priority to the core’s priority. Thus applicants have merely claimed the combination of known parts in the field to achieve predictable results of having decentralized interrupt controllers, and is therefore rejected under 35 USC 103.
As per claim 29, the combination of Haugh and Kimelman further teach:
The processor-based system of claim 28, further comprising: a second processor comprising a plurality of second CPU cores; and a second interrupt controller configured to: receive second temperature data related to a temperature for the plurality of second CPU cores; receive a second interrupt from an interrupt generating device of the plurality of interrupt generating devices; determine one or more second eligible CPU cores of the plurality of second CPU cores eligible to handle the second interrupt based on a second interrupt routing policy; determine, based on the second temperature data, a second set of eligible CPU cores of the one or more second eligible CPU cores that would remain below a second temperature threshold based on handling the second interrupt; and communicate the second interrupt to be received by the second set of eligible CPU cores; and each second eligible CPU core of the second set of eligible CPU cores configured to: receive the second interrupt; and in response to determining to service the second interrupt, service the second interrupt. (Kimelman figure 3C: distributed interrupt controller; Haugh figure 5 and [0059] – [0065].)
As per claim 30, the combination of Haugh and Kimelman further teach:
The processor-based system of claim 28, further comprising a second processor, comprising a plurality of second CPU cores; the first interrupt controller configured to: receive second temperature data related to a temperature for the plurality of second CPU cores; receive a second interrupt from an interrupt generating device of the plurality of interrupt generating devices; determine one or more second eligible CPU cores of the plurality of second CPU cores eligible to handle the second interrupt based on a second interrupt routing policy; determine, based on the second temperature data, a second set of eligible CPU cores of the one or more second eligible CPU cores that would remain below a second temperature threshold based on handling the second interrupt; and communicate the second interrupt to be received by the second set of eligible CPU cores; and each second eligible CPU core of the second set of eligible CPU cores configured to: receive the second interrupt; and in response to determining to service the second interrupt, service the second interrupt. (Kimelman figure 3C: distributed interrupt controller; Haugh figure 5 and [0059] – [0065].)
Response to Arguments
Applicant's arguments filed 8/14/2026 have been fully considered but they are not persuasive.
Claim 1:
Applicant argued on pages 13 – 15 that Haugh does not anticipate the claimed limitation of “determine one or more eligible CPU cores of the plurality of CPU cores eligible to handle the interrupt based on an interrupt routing policy; determine, based on the temperature data, a first set of eligible CPU cores of the one or more eligible CPU cores that would remain below a temperature threshold based on handling the interrupt;”. More specifically, applicant argued on page 14, first paragraph, that Haugh teaches “selecting a “lowest temperature” processor, or excluding the “highest temperature” processor, based on the current relative temperatures is not the same as determining that one or more eligible CPU cores “would remain below a temperature threshold based on handing the interrupt,” as claim 1 requires.”.
The examiner disagrees. Referring to Haugh [0061] first, wherein it teaches an example of “if a four-processor computer system had processor temperatures of 100 degrees, 125 degrees, 130 degrees, and 150 degrees, a new processing request would be directed to the first processor (e.g., routing system interrupts to the first processor) in this embodiment. After a number of processing requests are performed, the temperature of the first processor may increase until another processor may have the lowest temperature, after which it will be the recipient of the next request”. Next referring to Haugh [0062], wherein it teaches an alternative example of “element 508 could prevent new processing requests from going to the fourth processor (at 150 degrees) until its temperature dropped enough so that it would not be the highest temperature processor. The processing requests could be directed to the lowest temperature processor, multiple processors, etc.”. The examiner notes that under the example given in [0062], the claimed “first set of eligible CPU cores of the one or more eligible CPU cores that would remain below a temperature threshold based on handing the interrupt” would be mapped to the 3 processor cores at 100, 125 and 130 degrees respectively, and the claimed “temperature threshold” is mapped to the fourth processor at 150 degrees, and the processor’s temperature, after handing the interrupt would still be below the temperature of fourth processor at 150 degrees. Thus Haugh teaches the claimed limitations of claim 1 in full.
Rest of the claims:
No distinct arguments are raised.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES M SWIFT whose telephone number is (571)270-7756. The examiner can normally be reached Monday - Friday: 9:30 AM - 7PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, April Blair can be reached at 5712701014. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHARLES M SWIFT/Primary Examiner, Art Unit 2196
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