Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is in response to the communication filed on 12/26/2025.
Claims 1-9 and 21-31 are examined and rejected.
Response to Arguments
Applicant arguments, dated 12/26/2025 have been fully considered.
Applicant argues the following : Combination of Kreft-Leon does not teach,
‘ .. tamper detection response circuitry operable to, in response to a detected tamper event, cause programmable circuitry to enter standby mode, number generator circuitry operable to generate a number, tamper recovery aggregation circuitry operable to trigger the programmable circuitry to exit the standby mode after a threshold amount of time based on the generated number. . ‘.
Kreft is silent about when and how to reactivate the hardware after the hardware is temporarily unavailable.
Kreft does not teach on how to reenable the hardware module after the hardware module disables itself.
Examiner acknowledges the argument and submits the response below.
Examiner’s response as following: –
Examiner does not find argument persuasive, as combination of references teaches the following limitation(s) as described below –
Kreft teaches in para 199 – ‘ .. trusted time source is to be reinitialized after erasure, the tamper-protected hardware module may receive on-line the current date and time from a trustable authority, e.g. a Root Certification Authority or a CA, or from an eMint signed by a Root Certification Authority, and initialize the trusted time source with the current date and time only if the signature of the Root Certification Authority can be verified successfully .. ‘ and further in para 266 ‘ .. WatchDOG timer (WDOG) in combination with a reset logic may be provided. The CASTOR may further include power management circuitry (e.g. a sleep mode & wake-up logic, voltage & power regulator sensors, filters, etc.). .. ‘.
As examine interprets the teachings of Kreft para 199 and 266 such that upon detection of tamper event at chip / memory level the TPM module verifies with Root certiticate authority with trusted time and date signature, meanwhile the time for confirmation is set for watchdog timer such that system can reset, go into sleep mode with wake-up logic. Where examiner interprets that Kreft’s teaching of system re-set or sleep mode with wakeup logic covers the teaching of claim limitation of standby mode and as the reply from RCA root cause authority determines the status of standby mode.
Examiner replies that in broad view of claim language and as relevant to one of ordinary skills in art the time of invention, it is well know that standby mode and wakup logic covers the claimed limitation.
Examiner concludes that Kreft (and combination of references) teaches argued limitation as described above.
Examiner is open for phone call interview to discuss further with applicant’s representative for the purpose of compact prosecution.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 and 21-31 are rejected under 35 U.S.C. 103 as being unpatentable by U.S. Publication 2020/0228351 to Kreft et al. (hereinafter known as “Kreft”) and in view of U.S. Publication 2012/0185636 to Leon et al. (hereinafter known as “Leon”).
As per claim 1 Kreft teaches, an apparatus comprising:
tamper detection response circuitry operable to, in response to a detected tamper event, cause programmable circuitry to enter standby mode (Kreft para 96-97 teaches tamper detection events by tamper protected circuit such as ‘tamper protected’ ‘tamper detection’ in semiconductor module in PUF (physical unclonable function));
number generator circuitry operable to generate a number (Kreft para 28 and 31 teaches generation of random secret key which is interpreted as generate number); and
tamper recovery aggregation circuitry operable to trigger the programmable circuitry to exit the standby mode after a threshold amount of time based on the generated number (Kreft para 199 and 266 teaches tamper-resistibility in hardware module with time validation with on-chip of the tamper-protected hardware module's trusted time-source and predetermined time span upon disconnection from its power supply which covers claimed limitation).
Although Kreft teaches watchdog mode and sleep mode or stand by mode in tamper detection if further taught by (Leon para 58 teaches Anti-Tamper module with watchdog module where encrypted format detects unauthorized user).
Kreft – Leon are analogous as they are from same domain of tamper resistance hardware in system.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Kreft-Leon before him or her, to combine, Kreft’s teaching of trusted secure software and Physical Unclonable function (Kreft Fig 1) with Leon’s standby mode activated on tamper detection (Leon para 58). The suggestion/motivation for doing so would have been to enhance security and to prevent physical tampering in system (Leon Fig 1).
As per claim 2 combination of Kreft - Leon teaches, the apparatus of claim 1, further including first tamper event aggregation circuitry operable to detect the tamper event based on a second signal from second tamper event aggregation circuitry, wherein the tamper detection response circuitry is implemented in the apparatus and the second tamper event aggregation circuitry is implemented by a leader controller (Kreft Fig 1 element PUF unit is interpreted as tamper event aggregation circuitry and other units as PK/ID generator, clock PLL - timer unit, Crypto primitives are interpreted as second tamper event aggregation circuitry).
As per claim 3 combination of Kreft - Leon teaches, the apparatus of claim 2, wherein the apparatus is a system on chip separate from the leader controller (Kreft Fig 11 para 114 and 142 teaches tamper protected onchip modules with cryptographic element).
As per claim 4 combination of Kreft - Leon teaches, the apparatus of claim 1, further including a counter operable to increment a count to determine whether the number satisfies a threshold corresponding to the threshold amount of time (Kreft Fig 1 para 290).
As per claim 5 combination of Kreft - Leon teaches, the apparatus of claim 4, wherein the counter is operable to initiate the count after the programmable circuitry enters the standby mode (Kreft Fig 1 para 266 teaches - timer-unit and/or Clock Phase Lock Loop (Clock PLL), used to implement timers for detecting timeouts (e.g. fail-stop timeouts, lock timeouts, etc.), and to provide a WatchDOG timer (WDOG) in combination with a reset logic may be provided).
As per claim 6 combination of Kreft - Leon teaches, the apparatus of claim 4, wherein the counter is operable to initiate the count after the tamper event has ceased (Kreft Fig 1 para 26 and 65 teaches detection of any tampering of the tamper-protected semiconductor module by implementing TRUSTLETs to protect integrity protected entity blocks software/firmware functionality to be executed by the tamper-protected hardware with counter mechanism).
As per claim 7 combination of Kreft - Leon teaches, the apparatus of claim 1, wherein the tamper detection response circuitry is operable to, in response to the detected tamper event, cause adjustment of firewall settings to prevent access to a sub-system (Kreft para 182 teaches tamper detection associated with security policy monitoring for breach).
As per claim 8 combination of Kreft - Leon teaches, the apparatus of claim 7, wherein the sub-system includes at least one of an accelerator (Kreft para 66 teaches accelerometer as an input means allowing the user to interact with the eWallet), debug circuitry, or memory (Kreft para 77 teaches tamper-protected semiconductor modules with additional hardware elements, such as memory (volatile memory and/or non-volatile memory)), and wherein the sub-system is part of the apparatus.
As per claim 9 combination of Kreft - Leon teaches, the apparatus of claim 1, wherein the tamper event corresponds to at least one of a temperature adjustment (Kreft para 300 teaches tamper-protected semiconductor modules with teamperature monitoring such as upto (-40 degrees C)), a clock loss (Kreft para 287 teaches analysis of clock jittering attack), an electromagnetic event, or laser-based event (Kreft para 118 teaches tamper-protected semiconductor module, non-invasive (or “passive”, e.g. scanning the tamper-protected semiconductor module through a beam of (LASER) light, other radiation fields or screening technology)).
As per claim 21 combination of Kreft - Leon teaches, the apparatus of claim 1, wherein the number generator circuitry operable to generate the number using a random process or a pseudo-random process (Kreft para 219-221 teaches random secret key generation).
Claim 22,
Claim 22 is rejected in accordance with claim 1.
As per claim 23 combination of Kreft - Leon teaches, the method of claim 22, further comprising detecting the tamper event based on a signal from tamper event aggregation circuitry, wherein the programmable circuitry and the tamper event aggregation circuitry are implemented in separate chips (Kreft para 492-494, Fig 21 teaches architecture of cocoon PUF structure which includes multiple chips).
Claim 24,
Claim 24 is rejected in accordance with claim 4.
Claim 25,
Claim 25 is rejected in accordance with claim 5.
Claims 26,
Claim 26 is rejected in accordance with claim 6.
Claim 27,
Claim 27 is rejected in accordance with claim 8.
Claims 28,
Claim 28 is rejected in accordance with claim 21.
As per claim 29 Kreft teaches, an apparatus comprising:
a first circuit; and a second circuit coupled to the first circuit (Kreft para 492-494, Fig 21 teaches architecture of cocoon PUF structure which includes multiple chips) and configurable to:
cause the first circuit to enter standby mode in response to a detected tamper event (Kreft para 96-97 teaches tamper detection events by tamper protected circuit such as ‘tamper protected’ ‘tamper detection’ in semiconductor module in PUF (physical unclonable function));
set a threshold level using a random process, a pseudo-random process, or a quasi-random process (Kreft para 219-221 teaches random secret key generation);
increment a count after the tamper event is detected; and
trigger the first circuit to exit the standby mode in response to determining that the count satisfies the threshold level (Kreft Fig 1 para 290).
Although Kreft teaches watchdog mode and sleep mode or stand by mode in tamper detection if further taught by (Leon para 58 teaches Anti-Tamper module with watchdog module where encrypted format detects unauthorized user).
Kreft – Leon are analogous as they are from same domain of tamper resistance hardware in system.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Kreft – Leon before him or her, to combine, Kreft’s teaching of trusted secure software and Physical Unclonable function (Kreft Fig 1) with Leon’s standby mode activated on tamper detection (Leon para 58). The suggestion/motivation for doing so would have been to enhance security and to prevent physical tampering in system (Leon Fig 1).
Claim 30,
Claim 30 is rejected in accordance with claim 5.
Claim 31,
Claim 31 is rejected in accordance with claim 6.
Prior Art of Record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Erickson et al US Publication 20220405387
Venerosso et al US Publication 20210073425
McCandlish et al US Patent 11469888
Karakoyunlu et al US Patent 11151290
Whitmore et al US Patent 11397811
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VIRAL S LAKHIA whose telephone number is (571)270-3363. The examiner can normally be reached on 8 am - 6 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynn Feild can be reached on 571-272-2092. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/VIRAL S LAKHIA/Primary Examiner, Art Unit 2431