DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Following prior arts are considered pertinent to applicant's disclosure.
US 20220415815 A1 (Waidhas)
US 20220301975 A1 (HAM)
JP2017126668A (JP68)
US 20210305227 A1 (Chen227)
US 20170170155 A1 (Fig.4 para 73 teaches a device of claim 1)
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 16-18, 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Waidhas.
Claim 1. A chip package [(para 1, Fig.1)] comprising: an integrated circuit (IC) die having functional circuitry [(Fig.1, 101)] : a substrate having the IC die mounted thereon, the substrate comprising: a core having at least a first cavity:[(#133, Fig.1)] , inductor routing vias, a plurality of signal transmission vias, a plurality of ground routing vias, and a plurality of power routing vias:[(power and signal in para 28-30; inductor routing in para 33, ground in para 36, 38, 41)] an upper build-up layer disposed on the core between the core and IC die :[(#148)] , the upper build-up layer including routing coupling the inductor routing vias, the signal transmission vias, and the ground and power routing vias to the functional circuitry of the IC die:[(para 36; 101 be a inductor {para 32} which is connected through via’s and routings located in #148 {see Fig.1}; also see para 33-34)] and a lower build-up layer disposed a side of the core opposite the upper build-up layer, the lower build-up layer including routing coupled to the functional circuitry of the IC die through the vias of the core and the routing of upper build-up layer: [(#150; see the coupling connections in Fig.1 and descriptions in para 28-31 & 34)] and a chiplet disposed in a first cavity formed the core, the chiplet coupled to the functional circuitry of the IC die through upper build-up layer. [(#102, #103, #105)]
Claim 2. The chip package of claim 1, wherein the chiplet includes voltage regulator circuitry.[[(VR in para 32)]
Claim 3. The chip package of claim 2 further comprising: an inductor having an input and an output, the input coupled to an outlet of the voltage regulator circuitry and the output coupled to the functional circuitry of the IC die.[[(Fig.1)]
Claim 4. The chip package of claim 3, wherein the inductor is coupled to the voltage regulator circuitry through the routing of the lower build-up layer [(VR circuits in para 32, VR includes inductor {para 22}, 102 includes inductors {para 33}; “102, 103, 105 may be a single-sided or a double-sided component …… that has connections on both surfaces (e.g., a first surface 170-1 and a second surface 170-2). …. ”; “inductors, may be disposed on the top surface or the bottom surface of the package substrate 150, or may be embedded in the package substrate 150.”; para 34; also see para )]
Claim 5. The chip package of claim 4, wherein the inductor is disposed in the first cavity. [(para 253, 267, 131 and earlier discussion, 103 or 102 which is inside the cavity can be an inductor )]
Claim 16. A chip package comprising: ( see analysis of claims 1-3 & 5) an integrated circuit (IC) die having functional circuitry: a substrate having the IC die mounted thereon, the substrate comprising: a core having one or more cavities, a plurality of signal transmission vias, inductor routing vias, a plurality of ground routing vias, and a plurality of power routing vias: an upper build-up layer disposed on the core between the core and IC die, the upper build-up layer including routing coupling the inductor routing vias, the signal transmission vias, and the ground and power routing vias to the functional circuitry of the IC die: and a lower build-up layer disposed a side of the core opposite the upper build-up layer, the lower build-up layer including routing coupled to the functional circuitry of the IC die through the vias of the core and the routing of upper build-up layer: a chiplet disposed in the one or more cavities formed the core, the chiplet having voltage regulating circuitry coupled to the functional circuitry of the IC die through upper build-up layer: and an inductor disposed in the one or more cavities formed the core, the inductor having an input and an output, the input coupled to an outlet of the voltage regulator circuitry and the output coupled to the functional circuitry of the IC die.
Claim 17. The chip package of claim 16, wherein the inductor and the chiplet are disposed in a common cavity of the one or more cavities formed the core. [(#102-105 can be chip or inductor)]
Claim 18. The chip package of claim 17, wherein the common cavity is disposed directly below the IC die.[[(see Fig.1)]
Claim 20. A method for fabricating a chip package, comprising: securing a chiplet and an inductor in a cavity formed in a substrate: forming build-up layers on the substrate over the chiplet and the inductor, the build-up layers including routing electrically coupled to the chiplet and the inductor: and mounting an integrated circuit (IC) die on the build-up layers, the IC die including functional circuitry coupled by the routing of the build-up layers to the chiplet and the inductor. [(see analysis of claim 1 and para 40 and 109 of Waidhas)]
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 6, 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Waidhas in view of HAM.
Regarding Claim 6. Waidhas teaches plurality of devices with some being inductor but have not shown separate cavities.
Waidhas does not explicitly show the inductor is disposed in a second cavity formed in the core
However, in the same/related field of endeavor, HAM teaches the inductor is disposed in a second cavity formed in the core [(Fig. 22, 23)]
Therefore, in light of above discussion it would have been obvious to one of the ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teaching of the prior arts because such combination would provide predictable result with no change of their respective functionalities [(HAM teaches the same {Fig. 19-21}components can be placed in same or separate cavities {Fig. 2, 23})] .
Claim 12. The chip package of claim 3, wherein the inductor is an air core inductor formed in the substrate. [(Waidhas and HAM teaches inductors, examiner takes official notice that air core inductor is well known design choice for these kind of chip)]
Claim 13. The chip package of claim 5, wherein the inductor is formed from a magnetic material. [(HAM para 55)]
Claim 14. The chip package of claim 5, wherein the inductor is a pre-fabricated component and secured in the substrate by a dielectric filler. [(Waidhas and HAM teach inductors, examiner takes official notice that these kind of inductor is well known design choice for these kind of chip)]
Claim 15. The chip package of claim 3 further comprising: a capacitor having one terminal coupled to the both the functional circuitry of the IC die and the output of the inductor [(Waidhas and HAM teaches inductor and capacitors used in numerous scenarios Waidhas para 22, 33, 34, 109, 131, HAM para 55, 73, while they may not describe the specific claimed connection, examiner takes official notice that such connections are well known )]
Claims 7-8, 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Waidhas in view of HAM in view of JP68.
Regarding Claim 7. HAM teaches backside thermal layer 200 and thermal vias 400 while also describing the thermal via as metal and 200 having high thermal conductivity [(para 98)]
Waidhas does not explicitly show that the layer 200 is metal.
However, in the same/related field of endeavor, JP68 teaches that a metal layer is used for such case [(para 21)]
Therefore, in light of above discussion it would have been obvious to one of the ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teaching of the prior arts because based on HAM metal is an obvious choice.
Waidhas in view of HAM in view of JP68 teaches w.r.t. claim 8. The chip package of claim 7, wherein the upper build-up layer further comprises: thermal vias formed on the backside metal layer. [(HAM #400 and JP68 #31 & 5, Fig.1)]
Claim 10. The chip package of claim 5, wherein the chiplet further comprises: a backside metal layer. [(see analysis of claim 7)]
Claim 11. The chip package of claim 10, wherein the upper build-up layer further comprises: thermal vias formed on the backside metal layer and extending to a top surface of the substrate. [(see JP68, Fig.1)]
Claims 9, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Waidhas in view of HAM in view of JP68 in view Chen227.
Regarding Claim 9. Waidhas in view of HAM in view of JP68 teaches the chip package of claim 8 further comprising: a stiffener disposed on the substrate directly above the thermal vias:[(JP68 #5)] the stiffener and the thermal vias provide a conductive path operable to conduct heat from the backside metal layer [(see discussion of HAM para 98 and JP68 para 21)]
Waidhas in view of HAM in view of JP68 does not explicitly show and a lid disposed over the IC die and stiffener, for conducting heat
However, in the same/related field of endeavor, Chen227 teaches a lid disposed over the IC die and stiffener, for conducting heat [(para 4, Fig.1)]
Therefore, in light of above discussion it would have been obvious to one of the ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teaching of the prior arts because such combination would improve thermal benefit and mechanical integrity [(Chen227 para 4, Fig.1)]
Claim 19. The chip package of claim 16 further comprising: (see clm 7-9) a stiffener disposed on the substrate directly above a cavity of the one or more cavities in which the chiplet resides: a backside metal layer formed on the chiplet: thermal vias formed on the backside metal layer, the thermal via disposed directly below the stiffener: and a lid disposed over the IC die and stiffener, wherein the stiffener and the thermal vias provide a conductive path operable to conduct heat from the backside metal layer to the lid. [(see analysis of claims 1-9)]
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shahan Rahaman whose telephone number is (571)270-1438. The examiner can normally be reached on 7am - 3:30pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nasser Goodarzi can be reached at telephone number (571) 272-4195. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/SHAHAN UR RAHAMAN/Primary Examiner, Art Unit 2426