DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 22 is objected to because of the following informalities: Claim 22 recite “POP” is an abbreviation and first recitation is to be spelled out. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3 and 5 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by CHLOE et al. 20250029932.
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Regarding claim 1, figs. 10U-11V of A package carrier, comprising:
a redistribution circuit layer, having a first surface (as labeled by examiner above) and a second surface ((as labeled by examiner above)) opposite to each other, and comprising a plurality of redistribution circuits (122 and 123), a plurality of conductive vias (132 and 133), a plurality of dielectric layers (112-1, 112-2), and a plurality of output pads 124, wherein the redistribution circuits and the dielectric layers are alternately stacked, the conductive vias are electrically connected to two adjacent redistribution circuits, the conductive vias are flush with the first surface (as labeled by examiner above show first surface and 131 are flush), and the output pads protrude from the second surface;
a plurality of first conductive pillars 121 (see fig. 10R and par [0112]), disposed on the first surface of the redistribution circuit layer (see 111 on first surface and 121 is on 111), and electrically connected to part of the conductive vias (see fig. 10V showing 121 and 131); and
a package mold plate 111 (element 111 is a plate for forming molding layer – mold is a cavity in which a substance is shaped), disposed on the first surface of the redistribution circuit layer, wherein a middle region of the package mold plate has a recess C1 (see fig. 10R), the recess exposes the first conductive pillars (see fig. 10R), the first conductive pillars pass through part of the package mold plate located in the middle region, and a thickness of an edge region of the package mold plate provides mechanical stability (see figs. 11-12 showing as such).
Regarding claim 3, par [0121] – [0125] of Chloe discloses wherein a line width of each of the redistribution circuits is greater than or equal to 0.5 microns and less than or equal to 30 microns.
Regarding claim 5, fig. 10U of Chloe discloses further comprising: a plurality of second conductive pillars 131, penetrating the package mold plate, and electrically connected to the conductive vias of the redistribution circuit layer.
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Regarding claim 1, fig. 11 of Chloe discloses a chip package structure, comprising:
a package carrier, disposed on the circuit board, and electrically connected to the circuit board, wherein the package carrier comprises:
a redistribution circuit layer, having a first surface and a second surface opposite to each other and comprising a plurality of redistribution circuits, a plurality of conductive vias, a plurality of dielectric layers, and a plurality of output pads, wherein the redistribution circuits and the dielectric layers are alternately stacked, the conductive vias are electrically connected to two adjacent redistribution circuits, the conductive vias are flush with the first surface, and the output pads protrude from the second surface;
a plurality of first conductive pillars, disposed on the first surface of the redistribution circuit layer, and electrically connected to part of the conductive vias; and
a package mold plate (as labeled by examiner above), disposed on the first surface of the redistribution circuit layer, wherein a middle region of the package mold plate has a recess C2, the recess exposes the first conductive pillars 121, the first conductive pillars pass through part of the package mold plate located in the middle region, and a thickness of an edge region of the package mold plate provides mechanical stability.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Chloe.
Regarding claim 2, par [0087] of Chloe discloses wherein the thickness exceeds 30 μm and that the line width or space of circuit patterns formed on the upper or lower surface of the first insulating layer 111 may increase. Chloe does not disclose wherein the thickness of the package mold plate is greater than or equal to 100 microns and less than or equal to 600 microns.
In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
As such it would have been obvious to form a carrier wherein the thickness of the package mold plate is greater than or equal to 100 microns and less than or equal to 600 microns in order to form increase line width or space of circuit patterns formed on the upper or lower surface of the first insulating layer.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chloe in view of Liao et al. 20190363056.
Regarding claim 4, fig. 11 of Chloe discloses further comprising: a protective layer, disposed on the second surface of the redistribution circuit layer, and exposing part of the output pads.
Chloe does not disclose that the protective layer is a solder mask.
However, par [0038] of Liao discloses that a bottom protection structure 22 may include a first bottom protection structure 221 and a second bottom protection structure 222. The first bottom protection structure 221 is disposed on the bottom surface 101 of the substrate body 10, and covers a portion of the bottom circuit layer 12. A material of the first bottom protection structure 221 may include a solder mask or a solder resist material.
In view of such teaching, it would have been obvious to form a carrier of Chloe comprising the protective layer is a solder mask such as taught by Liao as solder mask is prior art protect film.
Claim 14-19 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Chloe in view of LAKHERA et al. 20200395332.
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Regarding claim 14 (see rejection of claim 1), fig. 11 of Chloe discloses a chip package structure, comprising:
a package carrier, disposed on the circuit board, and electrically connected to the circuit board, wherein the package carrier comprises:
a redistribution circuit layer, having a first surface and a second surface opposite to each other and comprising a plurality of redistribution circuits, a plurality of conductive vias, a plurality of dielectric layers, and a plurality of output pads, wherein the redistribution circuits and the dielectric layers are alternately stacked, the conductive vias are electrically connected to two adjacent redistribution circuits, the conductive vias are flush with the first surface, and the output pads protrude from the second surface;
a plurality of first conductive pillars, disposed on the first surface of the redistribution circuit layer, and electrically connected to part of the conductive vias; and
a package mold plate (as labeled by examiner above), disposed on the first surface of the redistribution circuit layer, wherein a middle region of the package mold plate has a recess C2, the recess exposes the first conductive pillars 121, the first conductive pillars pass through part of the package mold plate located in the middle region, and a thickness of an edge region of the package mold plate provides mechanical stability; and
a chip 420, disposed in the recess of the package mold plate, and electrically connected to the first conductive pillars 121.
Chloe does not disclose of a circuit board and does not disclose that the output pads protrude from the second surface are electrically connected to the circuit board.
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However, fig. 1 of LAKHERA discloses chip package assembly 102 may be mounted to a printed circuit board 120 to form an electronic device 150.
In view of such teaching, it would have been obvious to form a structure of Chloe further comprising a circuit board and that the output pads which protrude from the second surface are electrically connected to the circuit board in order to form a bigger electronic device such as taught by LAKHERA.
Regarding claim 15, fig. 1 of LAKHERA discloses further comprising: a plurality of solder balls 114, disposed between the circuit board 116 and the package carrier, wherein the output pads of the redistribution circuit layer are electrically connected to the circuit board through the solder balls; and an underfill 126, filled between the circuit board and the package carrier, and covering the solder balls.
As such it would have been obvious to form a structure further comprising: a plurality of solder balls, disposed between the circuit board and the package carrier, wherein the output pads of the redistribution circuit layer are electrically connected to the circuit board through the solder balls; and an underfill, filled between the circuit board and the package carrier, and covering the solder balls in order to form a protected connection.
Regarding claim 16, fig. 11 of Chloe discloses further comprising: an underfill 430, filled between the recess of the package mold plate and the chip, and covering the first conductive pillars.
Regarding claim 17, fig. 12 of Chloe disclose further comprising: a plurality of solder balls 550, disposed on a side of the circuit board relatively away from the package carrier.
Regarding claim 18, Chloe and LAKHERA do not disclose wherein the thickness of the package mold plate is greater than or equal to 100 microns and less than or equal to 600 microns.
However, par [0087] of Chloe discloses wherein the thickness exceeds 30 μm and that the line width or space of circuit patterns formed on the upper or lower surface of the first insulating layer 111 may increase.
In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
As such it would have been obvious to form a carrier wherein the thickness of the package mold plate is greater than or equal to 100 microns and less than or equal to 600 microns in order to form increase line width or space of circuit patterns formed on the upper or lower surface of the first insulating layer.
Regarding claim 19, par [0121] – [0125] of Chloe discloses wherein a line width of each of the redistribution circuits is greater than or equal to 0.5 microns and less than or equal to 30 microns.
Regarding claim 21, fig. 10V of Chloe discloses wherein the package carrier further comprises: a plurality of second conductive pillars 131, penetrating the package mold plate, and electrically connected to the conductive vias of the redistribution circuit layer.
Regarding claim 22, fig. 22 of Chloe discloses further comprising: a POP component 520/530, disposed on the package carrier, and electrically connected to the second conductive pillars, and the resulting structure would have been one wherein the chip is located between the POP component and the circuit board; a
plurality of solder balls 550, disposed between the POP component and the second conductive pillars, wherein the POP component is electrically connected to the second conductive pillars through the solder balls; and an underfill 470/510, filled between the POP component and the package carrier, between the POP component and the chip, and between the recess of the package mold plate and the chip, and covering the first conductive pillars and the solder balls.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Chloe and LAKHERA and Liao.
Regarding claim 20, Chloe and LAKHERA disclose claim 14, but do not disclose wherein the package carrier further comprises: a solder mask, disposed on the second surface of the redistribution circuit layer, and exposing part of the output pads.
However, par [0038] of Liao discloses that a bottom protection structure 22 may include a first bottom protection structure 221 and a second bottom protection structure 222. The first bottom protection structure 221 is disposed on the bottom surface 101 of the substrate body 10, and covers a portion of the bottom circuit layer 12. A material of the first bottom protection structure 221 may include a solder mask or a solder resist material.
In view of such teaching, it would have been obvious to form a carrier of Chloe and LAKHERA comprising the protective layer is a solder mask such as taught by Liao as solder mask is prior art protect film.
Allowable Subject Matter
Claims 6-13 are allowed.
The combination of limitations recited in claim 6 is not taught by the references of record.
Conclusion
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/VONGSAVANH SENGDARA/ Primary Examiner, Art Unit 2893