DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0036181 (Nitta) and US 2002/0124794 (Sakai).
For claim 1, Nitta teaches a method of manufacturing a semiconductor optical device (fig. 1A-3D) including a chip containing a III-V compound semiconductor (fig. 1A; [0026]) and a first substrate (fig. 1B, 20; [0028]),
wherein the chip includes a second substrate (fig. 1A, 10; [0026]) and a semiconductor layer stacked on the second substrate (fig. 1A, 12 and 14; [0026]),
wherein the method comprises:
forming the chip by cutting the second substrate and the semiconductor layer ([0027]);
bonding the semiconductor layer of the chip to the first substrate (fig. 1B; [0028]); and
removing the second substrate by etching the chip bonded to the first substrate (fig. 2B and 3C; [0030] and [0034]).
Nitta does not teach a shape of the chip in plan view does not have a side perpendicular to a first direction, and wherein, in the removing the second substrate, etching proceeds more easily in a second direction crossing the first direction than in the first direction.
However, Sakai teaches a chip has a shape in plan view (fig. 3A) does not have a side perpendicular to a first direction (fig. 3A, the first direction is parallel to lower left and upper right sides of rhombus), and does have a side perpendicular to a second direction crossing the first direction (fig. 3A, the lower left and upper right sides of rhombus are perpendicular to the second direction) such that the sides of the rhombus are formed along cleavage surfaces to easily split and cut the wafer ([0022]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form Nitta’s chip as taught by Sakai in order to easily slit and cut the wafer.
The sides of the combination inherently result in the removing the second substrate, etching proceeds more easily in a second direction crossing the first direction than in the first direction due the resulting shaper of the chip in the combination.
For claim 2, Sakai teaches the chip has a polygonal shape when viewed in plan view (fig. 3A) and has a side inclined (fig. 3A, lower right side or the bottom side including the lower right and lower left side) from a line extending in the second direction (fig. 3A, a line perpendicular to the lower left side).
For claim 3, Sakai teaches the side, which is inclined, includes two sides, the two sides form a vertex, and the vertex has an angle of 60° to 120° (fig. 3A, vertex at bottom of rhombus is 120°; see fig. 1).
For claim 6, Sakai teaches the semiconductor optical device according to wherein the chip has a parallelogram shape when viewed in plan view (fig. 3A).
For claim 7, Sakai teaches two vertices of the chip each have an angle of 45° or more and less than 90° (fig. 3A, left and right vertices are 60°).
For claim 8, the combination does not teach the second substrate and the semiconductor layer are cut by using an optical method. However, the examiner takes official notice that optical methods for cutting were well-known in the art before the effective filing date of the claimed invention.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a well-known optical method for cutting as a simple substitution for the cutting of the previous combination as the substituted components and their functions were known in the art and the substitution would have yielded predictable results. In the present case, the substituted component provides an alternative method of cutting the substrate and semiconductor layer. See MPEP 2143 I.B.
For claim 9, Nitta teaches the second substrate contains indium phosphide (fig. 1A, 10; [0026], wherein the semiconductor layer contains indium gallium arsenide([0026], etch stop layer 12), and wherein, in the removing the second substrate, the second substrate is removed by wet etching using an etchant containing hydrochloric acid ([0030]).
For claim 10, Nitta teaches
the semiconductor layer includes a first semiconductor layer (fig. 1B, 12) and a second semiconductor layer (fig. 1B, 12),
wherein the second substrate (fig. 1B, 10), the first semiconductor layer (fig. 1B, 12), and the second semiconductor layer (fig. 1B, 14) are sequentially stacked on top of one another (fig. 1A and 1B),
wherein, in the bonding, the second semiconductor layer is bonded to the first substrate (fig. 1B, 14 and 20), and
wherein the manufacturing method further comprises:
removing the first semiconductor layer after the removing the second substrate (fig. 3C, first layer 12 in region not covered by 22); and
etching the second semiconductor layer (fig. 3C, second layer 14 is etched in region not covered by 22 [0034]).
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0036181 (Nitta) and US 2002/0124794 (Sakai) and further in view of US 2009/0008654 (Nagai).
For claim 4, the previous combination does not teach the chip has a hexagonal shape when viewed in plan view, wherein two of six sides of the hexagonal shape form a vertex, wherein other two of the six sides form another vertex, and wherein the vertex and the other vertex face each other in the first direction.
However, Nagai teaches a chip may be formed as a rhombus along cleavage planes similar to the previous combination (fig. 5A), or, alternatively, the chip has a hexagonal shape when viewed in plan view (fig. 16B), wherein two of six sides of the hexagonal shape form a vertex (fig. 16B, right two sides of a hexagon), wherein other two of the six sides form another vertex (fig. 16B, left two sides of the hexagon), and wherein the vertex and the other vertex face each other in the first direction (fig. 16B, horizontal direction). Nagai’s hexagonal layout suppresses chipping and cracking at the time of dicing and allows for efficient use of the substrate ([0145]) and is a known alternative layout to the rhombus.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the hexagonal layout of Nagai as a simple substitution for the rhombus layout of previous combination as the substituted components and their functions were known in the art and the substitution would have yielded predictable results. In the present case, the substituted component provides an alternative layout to singulate chips on a substrate. The layout of Nagai has the advantage that it suppresses chipping and cracking at the time of dicing and allows for efficient use of the substrate See MPEP 2143 I.B.
For claim 5, the previous combination does not teach a plurality of the vertices are aligned in the second direction, and wherein at least one of the vertices and at least another one of the vertices face each other in the first direction.
However, Nagai teaches a chip may be formed as a rhombus along cleavage planes similar to the previous combination (fig. 5A) or, alternatively, a plurality of the vertices are aligned in the second direction (fig. 16B, vertices of a hexagon aligned in the vertical direction), and wherein at least one of the vertices and at least another one of the vertices face each other in the first direction (fig. 16B, for example upper left and upper right vertices face each other in the first horizontal direction). Nagai’s hexagonal layout suppresses chipping and cracking at the time of dicing and allows for efficient use of the substrate ([0145]) and is a known alternative layout to the rhombus.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the hexagonal layout of Nagai as a simple substitution for the rhombus layout of previous combination as the substituted components and their functions were known in the art and the substitution would have yielded predictable results. In the present case, the substituted component provides an alternative layout to singulate chips on a substrate. The layout of Nagai has the advantage that it suppresses chipping and cracking at the time of dicing and allows for efficient use of the substrate See MPEP 2143 I.B.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michael W Carter whose telephone number is (571)270-1872. The examiner can normally be reached M-F, 9:00-5:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MinSun Harvey can be reached at 571-272-1835. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Michael Carter/ Primary Examiner, Art Unit 2828
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