DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's response of 04/30/2026 has been acknowledged. Group II, claims 1-6 and 8-10 have been elected.
Claims 1-6 and 8-10are pending and have been examined.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 1-2, 4-6, and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Blessing et al. (US 20070145102 A1 – hereinafter Blessing-102) in view of Terada et al. (US 20220302077 A1 – hereinafter Terada).
Regarding independent claim 1, Blessing-102 teaches:
A bonding method ([0003] – “assembly method is known in the trade as
epoxy die bonding”) of bonding each of a plurality of first objects (2 – Fig. 2 – [0021] – “semiconductor chip 2”) to a first substrate (4 – Fig. 1 – [0021] – “substrate 4”), comprising:
determining, as an offset amount (.DELTA.x.sub.1, .DELTA.y.sub.1 and
.DELTA..theta..sub.1 – Fig. 2 – [0039] – “[0039] – “The deviation of the actual position of the semiconductor chip 2 from its set position is characterised by three quantities .DELTA.x.sub.1, .DELTA.y.sub.1 and .DELTA..theta..sub.1” – hereinafter ‘OFFSET’), an amount to offset a bonding position ([0039] – “P – Fig. 3 – [0039] – “the reference point P”) on the first substrate (4) from a design position (Y.sub.1 – [0026] – “Positioning the bondhead 6 in a predetermined y position so that the two reference marks 12, 13 and 14 and the semiconductor chip 2 are located in the field of view of the first camera 7. This y position is designated as Y.sub.1.”) for each of the plurality of first objects (2 – [0039] – “The deviation of the actual position of the semiconductor chip 2 from its set position is characterised by three quantities .DELTA.x.sub.1, .DELTA.y.sub.1 and .DELTA..theta..sub.1 whereby .DELTA.x.sub.1 and .DELTA.y.sub.1 designate the shifting of a reference point P of the semiconductor chip 2 in x direction or y direction and .DELTA..theta..sub.1 the rotation of the semiconductor chip 2 about the reference point P” – this describes the limitation); and
bonding each of the plurality of first objects (2) to the first substrate (4) based on the offset amount (OFFSET) determined in the determining,
wherein after the bonding, a process of bonding a plurality of second objects which are bonded to a second substrate, to the plurality of first objects bonded to the first substrate is performed,
wherein in the determining, the offset amount (OFFSET) is determined to satisfy a predetermined condition (19 – Fig. 2 – [0040] – “the set position presented with a dashed rectangle 19”) based on arrangement information representing an arrangement of the plurality of second objects on the second substrate, and
wherein the predetermined condition (19) includes a first condition ([0015] – “If at least one component of the third correction vector v.sub.3 is greater than a predetermined limit value, moving at least the axis of motion corresponding to this component to a new, corrected position; and [0015] I) Depositing the semiconductor chip onto the substrate location” – hereinafter ‘Con-1’) to electrically connect each of the plurality of first objects and the first substrate after the bonding is performed, and a second condition to electrically connect each of the plurality of first objects and a corresponding one of the plurality of second objects after the process is performed.
Blessing-102 does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Terada teaches
wherein after the bonding, a process of bonding a plurality of second objects (D2 – Fig. 4 – [0026] – “second device D2 is plural in number”) which are bonded to a second substrate (W2 – Fig. 4 – [0026] – “second substrate W2”), to the plurality of first objects (D1 – Fig. 3 – [0025] – “first device D1”) bonded to the first substrate (W1 – Fig. 3 – [0026] – “first substrate W1”) is performed,
electrically connect each of the plurality of first objects (D1) and the first substrate (W1) after the bonding is performed, and a second condition ([0090] – “A distance between the first substrate W1 and the second substrate W2 is measured with an encoder or the like, and this distance is set to be of a value at which the chip C can be pressed onto the second substrate W2 by the deformation of the tape T.” hereinafter ‘Con-2’) to electrically connect each of the plurality of first objects (D1) and a corresponding one of the plurality of second objects (D3) after the process is performed ([0026] – “The second conductive layer is configured to electrically connect the second device D2 and the first device D1” – this describes the electrically connection limitation).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the second object bonding process as taught by Terada into Blessing-102.
An ordinary artisan would have been motivated to use the known technique of Terada in the manner set forth above to produce the predictable results [0004] – “provide a technique enabling to suppress contamination of a bonding surface of a chip.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 2, Blessing-102 as modified by Terada, teaches claim 1 from which claim 2 depends. Blessing-102 further teaches
wherein the offset amount (OFFSET) includes at least one of a shift
amount (.DELTA..theta..sub.1 – Fig. 2 – [0039] – “[0039] – “.DELTA..theta..sub.1 the rotation of the semiconductor chip 2 about the reference point P– hereinafter ‘OFFSET’) and a rotation amount (.DELTA.x.sub.1, .DELTA.y.sub.1 and .DELTA..theta..sub.1 – Fig. 2 – [0039] – “[0039] – “The deviation of the actual position of the semiconductor chip 2 from its set position is characterised by three quantities .DELTA.x.sub.1, .DELTA.y.sub.1 and .DELTA..theta..sub.1” – hereinafter ‘OFFSET’) with respect to the design position (19) on the first substrate (4).
Regarding claim 4, Blessing-102 as modified by Terada, teaches claim 1 from which claim 4 depends. Blessing-102 does not expressly disclose the limitations of claim 4.
However, in an analogous art, Terada teaches
wherein the arrangement information includes information representing at
least one of a position and rotation ([0089] – “the second holder 52 in the X-axis direction and the Y-axis direction, and rotates it around a vertical axis. Accordingly, horizontal alignment between the first substrate W1 and the second substrate W2 is carried out” – this carries out position and rotation position arrangment) of each of the plurality of second objects (D2) on the second substrate (W2).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the second object bonding process as taught by Terada into Blessing-102.
An ordinary artisan would have been motivated to use the known technique of Terada in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 5, Blessing-102 as modified by Terada, teaches claim 1 from which claim 5 depends. Blessing-102 does not expressly disclose the limitations of claim 5.
However, in an analogous art, Terada teaches
wherein alignment between the first substrate (W1) and the second
substrate (W2) in the process is performed based on a preset target positional relationship ([0044] – “the cassette C1 accommodating therein a plurality of first substrates W1 each of which has the ring frame F attached thereto, the cassette C2 accommodating therein a plurality of second substrates W2, and empty cassettes C3 and C4 are arranged on the preset placing plates 22 of the carry-in/out station 2”) between the first substrate (W1) and the second substrate (W2).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the bonding process as taught by Terada into Blessing-102.
An ordinary artisan would have been motivated to use the known technique of Terada in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 6, Blessing-102 as modified by Terada, teaches claim 1 from which claim 6 depends. Blessing-102 further teaches
An article manufacturing method comprising:
bonding each of a plurality of first objects (2) to a first substrate (4) using a
bonding method defined in claim 1;
processing the first substrate (4) to which the plurality of first objects (2) are bonded; and
manufacturing an article (the semiconductor chip is an article) from the processed first substrate (4).
Regarding independent claim 8, Blessing-102 teaches:
A determination method of determining ([0038] – “Determining the
actual position, i.e. the translatory position and the orientation of the substrate location 3 is done either by evaluating the position of its pads 10 or by evaluating the position of reference marks arranged on the substrate 4” – hereinafter ‘DETER’), as an offset amount (.DELTA.x.sub.1, .DELTA.y.sub.1 and .DELTA..theta..sub.1 – Fig. 2 – [0039] – “[0039] – “The deviation of the actual position of the semiconductor chip 2 from its set position is characterised by three quantities .DELTA.x.sub.1, .DELTA.y.sub.1 and .DELTA..theta..sub.1” – hereinafter ‘OFFSET’), an amount to offset a bonding position on a first substrate (4) from a design position (Y.sub.1 – [0026] – “Positioning the bondhead 6 in a predetermined y position so that the two reference marks 12, 13 and 14 and the semiconductor chip 2 are located in the field of view of the first camera 7. This y position is designated as Y.sub.1.”) for each of a plurality of first objects (2) which are bonded to the first substrate (4),
wherein after each of the plurality of first objects is bonded to the first substrate, a process of bonding a plurality of second objects are bonded to a second substrate, to the plurality of first objects bonded to the first substrate is performed,
wherein the determination method (DETER) includes determining the offset amount (.DELTA.x.sub.1, .DELTA.y.sub.1 and .DELTA..theta..sub.1 – Fig. 2 – [0039] – “[0039] – “The deviation of the actual position of the semiconductor chip 2 from its set position is characterised by three quantities .DELTA.x.sub.1, .DELTA.y.sub.1 and .DELTA..theta..sub.1” – hereinafter ‘OFFSET’) to satisfy a predetermined condition (19 – Fig. 2 – [0040] – “the set position presented with a dashed rectangle 19”) based on arrangement information representing an arrangement of the plurality of second objects on the second substrate, and wherein the predetermined condition includes a first condition ([0015] – “If at least one component of the third correction vector v.sub.3 is greater than a predetermined limit value, moving at least the axis of motion corresponding to this component to a new, corrected position; and [0015] I) Depositing the semiconductor chip onto the substrate location” – hereinafter ‘Con-1’) to electrically connect each of the plurality of first objects and the first substrate after the bonding is performed, and a second condition to electrically connect each of the plurality of first objects and a corresponding one of the plurality of second objects after the process is performed.
Blessing-102 does not expressly disclose the other limitations of claim 8.
However, in an analogous art, Terada teaches
wherein after each of the plurality of first objects (D1 – Fig. 3 – [0025] – “first device D1”) is bonded to the first substrate (W1 – Fig. 3 – [0026] – “first substrate W1”), a process of bonding a plurality of second objects (D2 – Fig. 4 – [0026] – “second device D2 is plural in number”) are bonded to a second substrate (W2 – Fig. 4 – [0026] – “second substrate W2”), to the plurality of first objects (D1) bonded to the first substrate (W1) is performed ([0026] – “The second conductive layer is configured to electrically connect the second device D2 and the first device D1” – this describes this limitation),
representing an arrangement of the plurality of second objects (D2) on the second substrate (W2), and wherein the predetermined condition ([0044] – “the cassette C1 accommodating therein a plurality of first substrates W1 each of which has the ring frame F attached thereto, the cassette C2 accommodating therein a plurality of second substrates W2, and empty cassettes C3 and C4 are arranged on the preset placing plates 22 of the carry-in/out station 2”),
to electrically connect each of the plurality of first objects (D1) and the first substrate (W1) after the bonding is performed, and a second condition ([0090] – “A distance between the first substrate W1 and the second substrate W2 is measured with an encoder or the like, and this distance is set to be of a value at which the chip C can be pressed onto the second substrate W2 by the deformation of the tape T.” hereinafter ‘Con-2’) to electrically connect each of the plurality of first objects (D1) and a corresponding one of the plurality of second objects (D3) after the process is performed ([0026] – “The second conductive layer is configured to electrically connect the second device D2 and the first device D1” – this describes the electrically connection limitation).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the bonding process as taught by Terada into Blessing-102.
An ordinary artisan would have been motivated to use the known technique of Terada in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 9, Blessing-102 as modified by Terada, teaches claim 8 from which claim 9 depends. Blessing-102 does not expressly disclose the limitations of claim 9.
However, in an analogous art, Terada teaches
An information processing apparatus (9 – Fig. 1 – [0041] – “The control
device 9 is, for example, a computer, and includes a CPU (Central Processing Unit) 91 and a recording medium 92 such as a memory”) for executing a determination method ([0103] – “Next, before alignment between the chip C of the first substrate W1 and the second substrate W2 (S66 of FIG. 7) is performed, holding of the second substrate W2 (S64 of FIG. 7) and imaging of the second mark M2 (S65 of FIG. 7) are performed”) defined in claim 8.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the information apparatus as taught by Terada into Blessing-102.
An ordinary artisan would have been motivated to use the known technique of Terada in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 10, Blessing-102 as modified by Terada, teaches claim 8 from which claim 10 depends. Blessing-102 does not expressly disclose the limitations of claim 10.
However, in an analogous art, Terada teaches
A non-transitory computer-readable storage medium (92 – Fig. 1 – [0041] –
“The control device 9 is, for example, a computer, and includes a CPU (Central Processing Unit) 91 and a recording medium 92 such as a memory”) storing a program for causing a computer (9) to execute a determination method according to claim 8.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the storage medium as taught by Terada into Blessing-102.
An ordinary artisan would have been motivated to use the known technique of Terada in the manner set forth above to produce the predictable results as stated above in claim 1.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Blessing-102 in view of Terada and Mitsuishi et al. (US 20200286851 A1 – hereinafter Mitsuishi).
Regarding claim 3, Blessing-102 as modified by Terada, teaches claim 1 from which claim 3 depends. Blessing-102 further teaches
wherein in the determining, a median within a position range of the first
objects (2), which can satisfy the first condition (Con-1) and the second condition, is determined as the offset amount (OFFSET).
Blessing-102 does not expressly disclose the other limitations of claim 3.
However, in an analogous art, Terada teaches
the second condition (Con-2).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the storage medium as taught by Terada into Blessing-102.
An ordinary artisan would have been motivated to use the known technique of Terada in the manner set forth above to produce the predictable results as stated above in claim 1.
Blessing-102 and Terada do not expressly disclose the other limitations of claim 3.
However, in an analogous art, Mitsuishi teaches
wherein in the determining ([0076] – “under control of the individual correction control unit 132, the substrates are individually corrected before carried into the stacking unit 13 (step S12)”), a median ([0178] – “the decision unit 133 may decide, as the common correction amount of the correction that is executed through the common correction control unit 131, an average value, a median value, a mode value or a minimum value of the amount of positional misalignment measured by the first measuring unit 14”) within a position range.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the position determination process as taught by Mitsuishi into Blessing-102 and Terada.
An ordinary artisan would have been motivated to use the known technique of Mitsuishi in the manner set forth above to produce the predictable results of [0007] – “In the stacked substrate, positional misalignment among the substrates is generated due to a variety of causes. Therefore, in order to obtain predetermined positional alignment accuracy, it is necessary to correct diverse types of positional misalignment components.”
Pertinent Art
For the benefits of the Applicant, US 20100040449 A1 and US 20170062257 A1 are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose the combination of limitations including the chip alignment structure.
Conclusion
Any inquiry concerning this communication or earlier communications from the
examiner should be directed to GARY ABEL whose telephone number is (571) 272-0246. The examiner can normally be reached Monday - Friday 8:00 am - 5:00 pm (Eastern).
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/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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