DETAILED ACTION
1. This Office action is in response to the amendment filed on 12/15/2025
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 112
4. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
5. Claims 1, 11 and 16 recites the limitation "a higher voltage" in line 3, line 4 and line 6, respectively. It’s not clear as to which voltage the claimed “higher voltage” is higher than.
6. Claims 2 - 10, 12 - 15 and 17 - 20 each depend, either directly or indirectly, from claims 1, 11 and 16, and therefore these claims are also indefinite for the given reasons given above. For examination purposes, the examiner will interpret “a higher voltage” as any voltage that is higher than or equal to the regulated output voltage used by the regulator to generate a stable output voltage at a desired refence level.
Claim Rejections - 35 USC § 102
7. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
8. Claim(s) 16, 18 and 19 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Lu (US Pub. No. 20250055429 A1); (hereinafter Lu)
Regarding claim 16, Lu [e.g., Fig. 3] discloses a low drop out linear regulator [e.g., LDO 300], comprising: one or more circuit elements to perform ripple identification and ripple modification of a voltage, having a ripple, that is received from a voltage source [e.g., ripple received by paralleled feed-forward current ripple rejection (FFCRR) circuitry, p. 0013 recites "Examples described herein may be used to implement paralleled feed-forward current ripple rejection (FFCRR) circuitry that counteracts the current ripple generated by a pass transistor in a low dropout regulator circuit". It continues, "For example, a pass element of an LDO circuit generates a current ripple. The FFCRR circuit senses the current flow through the pass element, modifies the sensed current, and injects the modified current to the voltage output in order to counteract the current ripple generated by the pass element"], the ripple identification and ripple modification to produce an opposite polarity ripple, from the ripple, having additional gain [e.g., p.0042 recites "In other words, the negative gain amplifier 314 introduces a phase shift of the input signal (e.g., approximately 180 degrees out of phase with sensed current ripple). The negative gain is then achieved by employing an inverting operational amplifier configuration, where the input signal is connected to the inverting terminal"], and supply the opposite polarity ripple to the voltage regulated at a reference voltage level using a higher voltage [e.g., p. 0045 recites "The canceling amplifier 322 acts to reduce unwanted signals or noise from its output. The canceling amplifier 322 employs a feedback mechanism that senses the undesired signal by having the signal input at a first terminal. This input is compared to the desired signal (Vref) input at a second terminal of the canceling amplifier 322. Accordingly, an opposing signal to the undesired signal is produced at Vout"].
Regarding claim 18, Lu [e.g., Fig. 3] discloses wherein at least one of the circuit elements receive a portion of the voltage frequency spectrum [e.g., p. 0005 recites "A power supply rejection ratio (PSRR) is the ratio of the change in supply voltage to the output voltage produced, and is a measure of how well a circuit rejects ripple coming from a power supply. In the case of a low dropout regulator (LDO), PSRR is a measure of the output ripple voltage compared to the input ripple voltage over a wide frequency range (e.g., 10 Hz to 10 MHz)"].
Regarding claim 19, Lu [e.g., Fig. 3] discloses wherein the voltage is further corrected using at least an error amplifier [e.g., error amplifier 202], a loop [e.g., modifying stage 305 and current canceling 317], and a load capacitor [e.g., load capacitor CLOAD].
Claim Rejections - 35 USC § 103
9. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
11. Claim(s) 1, 4 - 7, 9 - 11 and 13 - 15 are rejected under 35 U.S.C. 103 as being unpatentable over Lu (US Pub. No. 20250055429 A1) in view of Wang (US Pub. No. 2013/0049859 A1); (hereinafter Lu and Wang).
Regarding claim 1, Lu [e.g., Fig. 3] discloses a method comprising: regulating an input voltage, received to a linear regulator, as a regulated voltage [e.g., regulating input voltage (Vin) received by LDO 300 to output voltage (Vout)]; receiving a ripple, identified in the regulated voltage, to a suppression element [e.g., ripple received by paralleled feed-forward current ripple rejection (FFCRR) circuitry, p. 0013 recites "Examples described herein may be used to implement paralleled feed-forward current ripple rejection (FFCRR) circuitry that counteracts the current ripple generated by a pass transistor in a low dropout regulator circuit". It continues, "For example, a pass element of an LDO circuit generates a current ripple. The FFCRR circuit senses the current flow through the pass element, modifies the sensed current, and injects the modified current to the voltage output in order to counteract the current ripple generated by the pass element"]; producing, using the suppression element, an opposite polarity ripple having increased gain [e.g., p.0042 recites "In other words, the negative gain amplifier 314 introduces a phase shift of the input signal (e.g., approximately 180 degrees out of phase with sensed current ripple). The negative gain is then achieved by employing an inverting operational amplifier configuration, where the input signal is connected to the inverting terminal”]; applying the opposite polarity ripple at the regulated voltage to at least partially suppress the ripple [e.g., p.0045 recites "The canceling amplifier 322 acts to reduce unwanted signals or noise from its output. The canceling amplifier 322 employs a feedback mechanism that senses the undesired signal by having the signal input at a first terminal. This input is compared to the desired signal (Vref) input at a second terminal of the canceling amplifier 322. Accordingly, an opposing signal to the undesired signal is produced at Vout"]; and providing, using the regulated voltage having the at least partially suppressed ripple [e.g., regulated voltage used to generate Vout], an output voltage from the linear regulator [e.g., LDO 300 provides VOUT].
Lu does not disclose at least providing a higher voltage for use to maintain the regulated voltage at a reference voltage level.
Wang [e.g., Fig. 2] teaches by at least providing a higher voltage [e.g., voltage VDD supplied to error amplifier 152] for use to maintain the regulated voltage at a reference voltage level [e.g., VDD used to maintain regulated VREG at a reference voltage level VREF, p. 0032 recites “The reference voltage, Vref, is typically established at a level that is somewhat less than the system voltage, VDD. In an embodiment, the system voltage, VDD, is a nominal 3.5V and the reference voltage, Vref, is approximately VDD-150 mV. In an embodiment, the approximate value of 150 mV below VDD is chosen such that the pass transistor 232 does not enter the "triode" mode of operation, where its gain degrades drastically and Vreg (and, therefore, RF output of amplifier 154) is no longer controlled by the feedback loop comprising the transistors 232 and 234, the multiplier 242 and the feedback resistor 246, resulting in large switching transients.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Lu with at least providing a higher voltage for use to maintain the regulated voltage at a reference voltage level as suggested by Wang to reduce large switching transients within the pass transistor.
Regarding claim 4, Lu [e.g., Fig. 3] discloses wherein the suppression element [e.g., paralleled feed-forward current ripple rejection (FFCRR) circuitry 208] receives the ripple as a portion of the regulated voltage frequency spectrum [e.g., p. 0005 recites "A power supply rejection ratio (PSRR) is the ratio of the change in supply voltage to the output voltage produced, and is a measure of how well a circuit rejects ripple coming from a power supply. In the case of a low dropout regulator (LDO), PSRR is a measure of the output ripple voltage compared to the input ripple voltage over a wide frequency range (e.g., 10 Hz to 10 MHz)"].
Regarding claim 5, Lu [e.g., Fig. 3] discloses wherein the suppression element is connected to a portion of a pass device [e.g., paralleled feed-forward current ripple rejection (FFCRR) circuitry 208 connected to pass element 206].
Regarding claim 6, Lu [e.g., Fig. 3] discloses wherein the pass device is a NMOS pass device [e.g., pass element 206 shown as a NMOS transistor].
Regarding claim 7, Lu [e.g., Fig. 3] discloses wherein the NMOS pass device is connected to the linear regulator and configured as a source follower [e.g., pass element 206 with output voltage (Vout) connected to source].
Regarding claim 9, Lu [e.g., Fig. 3] discloses wherein regulating the input voltage [e.g., regulating Vin] further comprises: providing, using at least an error amplifier [e.g., error amplifier 202], the regulated voltage having the ripple from the input voltage [e.g., regulated voltage generated by pass transistor 206]; suppressing, using at least a loop of the linear regulator [e.g., current modifying stage 305], a first portion of the ripple of the regulated voltage [e.g., first portion addressed via paralleled feed-forward current ripple rejection (FFCRR) circuitry (LPF 308), p. 0043 recites “In operation, the sensed current modifying stage modifies the sensed current to create a signal that can cancel out the current ripple generated from the Vin source. This is performed by passing the sensed and copied signal from the sensing stage through both high pass and low pass filters in parallel. The passing of the sensed and copied signal through the low pass filter 308 allows for the low frequency signal to pass through while attenuating the high frequency signal. In doing so, the baseline or biasing signal is propagated to the next stage to establish an operating point for further signal processing.”], suppressing, using at least a load capacitor [e.g., load capacitor CLOAD], a second portion of the ripple of the regulated voltage [e.g., load capacitor CLOAD used as a typical smoothing output capacitor]; and suppressing, using the suppression element, at least a third portion of the ripple of the regulated voltage [e.g., third portion of ripple addressed via paralleled feed-forward current ripple rejection (FFCRR) circuitry (HPF 310, amplifier 312 and negative gain amplifier 314), p. 0043 recites “The passing of the sensed and copied signal through the high pass filter 310 and subsequently the amplifier 312 and the negative gain amplifier 314 allows for the high frequency signal to pass through while attenuating the low frequency signal. In doing so, the periodic signal fluctuations (current ripple) are captured. These periodic signal fluctuations are subsequently amplified and inverted for later cancelation. Both pathways are added together for the subsequent signal processing of the canceling stage.”].
Regarding claim 11, Lu [e.g., Fig. 3] discloses a system [e.g., LDO 300], comprising: one or more electrical components configured to: regulate an input voltage, received to a linear regulator, as a regulated voltage [e.g., regulating input voltage (Vin) received by LDO 300 to output voltage (Vout)]; receive a ripple, identified in the regulated voltage, to a suppression element [e.g., ripple received by paralleled feed-forward current ripple rejection (FFCRR) circuitry, p. 0013 recites "Examples described herein may be used to implement paralleled feed-forward current ripple rejection (FFCRR) circuitry that counteracts the current ripple generated by a pass transistor in a low dropout regulator circuit". It continues, "For example, a pass element of an LDO circuit generates a current ripple. The FFCRR circuit senses the current flow through the pass element, modifies the sensed current, and injects the modified current to the voltage output in order to counteract the current ripple generated by the pass element"]; produce, using the suppression element [e.g., using paralleled feed-forward current ripple rejection (FFCRR) circuitry 208], an opposite polarity ripple having increased gain [e.g., p.0041 - 0042 recites "In other words, the negative gain amplifier 314 introduces a phase shift of the input signal (e.g., approximately 180 degrees out of phase with sensed current ripple). The negative gain is then achieved by employing an inverting operational amplifier configuration, where the input signal is connected to the inverting terminal"]; apply the opposite polarity ripple at the regulated voltage to suppress the ripple [e.g., p.0045 recites “The canceling amplifier 322 acts to reduce unwanted signals or noise from its output. The canceling amplifier 322 employs a feedback mechanism that senses the undesired signal by having the signal input at a first terminal. This input is compared to the desired signal (Vref) input at a second terminal of the canceling amplifier 322. Accordingly, an opposing signal to the undesired signal is produced at Vout”]; and provide, using the regulated voltage having the ripple suppressed [e.g., regulated voltage used to generate Vout], an output voltage from the linear regulator [e.g., LDO 300 provides VOUT].
Lu does not disclose at least providing a higher voltage for use to maintain the regulated voltage at a reference voltage level.
Wang [e.g., Fig. 2] teaches by at least providing a higher voltage [e.g., voltage VDD supplied to error amplifier 152] for use to maintain the regulated voltage at a reference voltage level [e.g., VDD used to maintain regulated VREG at a reference voltage level VREF, p. 0032 recites “The reference voltage, Vref, is typically established at a level that is somewhat less than the system voltage, VDD. In an embodiment, the system voltage, VDD, is a nominal 3.5V and the reference voltage, Vref, is approximately VDD-150 mV. In an embodiment, the approximate value of 150 mV below VDD is chosen such that the pass transistor 232 does not enter the "triode" mode of operation, where its gain degrades drastically and Vreg (and, therefore, RF output of amplifier 154) is no longer controlled by the feedback loop comprising the transistors 232 and 234, the multiplier 242 and the feedback resistor 246, resulting in large switching transients.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Lu with at least providing a higher voltage for use to maintain the regulated voltage at a reference voltage level as suggested by Wang to reduce large switching transients within the pass transistor.
Regarding claim 13, Lu [e.g., Fig. 3] discloses wherein the suppression element [e.g., paralleled feed-forward current ripple rejection (FFCRR) circuitry 208] receives the ripple as a portion of the regulated voltage frequency spectrum [e.g., p. 0005 recites "A power supply rejection ratio (PSRR) is the ratio of the change in supply voltage to the output voltage produced, and is a measure of how well a circuit rejects ripple coming from a power supply. In the case of a low dropout regulator (LDO), PSRR is a measure of the output ripple voltage compared to the input ripple voltage over a wide frequency range (e.g., 10 Hz to 10 MHz)"].
Regarding claim 14, Lu [e.g., Fig. 3] discloses providing, using at least an error amplifier [e.g., error amplifier 202], the regulated voltage with the ripple from the input voltage [e.g., regulated voltage generated by pass transistor 206]; suppressing, using at least a loop of the linear regulator [e.g., current modifying stage 305], a first portion of the ripple of the regulated voltage [e.g., first portion addressed via paralleled feed-forward current ripple rejection (FFCRR) circuitry (LPF 308), p. 0043 recites “In operation, the sensed current modifying stage modifies the sensed current to create a signal that can cancel out the current ripple generated from the Vin source. This is performed by passing the sensed and copied signal from the sensing stage through both high pass and low pass filters in parallel. The passing of the sensed and copied signal through the low pass filter 308 allows for the low frequency signal to pass through while attenuating the high frequency signal. In doing so, the baseline or biasing signal is propagated to the next stage to establish an operating point for further signal processing.”]; and suppressing, using at least a load capacitor [e.g., load capacitor CLOAD], a second portion of the ripple of the regulated voltage [e.g., used as a typical smoothing output capacitor].
Regarding claim 15, Lu [e.g., Fig. 3] discloses wherein one or more frequencies of the identified ripple are greater than frequencies of a first portion of the ripple [e.g., high frequency components allowed to pass due to high pass filter 310, p. 0040 recites "The high pass filter 310 is a sub-circuit designed to allow signals with frequencies above a certain cutoff frequency to pass through while attenuating signals below the cutoff frequency. The high pass filter 310 permits the higher-frequency components of a signal to pass through while filtering out the lower-frequency components of a signal. In the context of FIG. 3, the higher frequency components of the signal input to the high pass filter are the copy of the ripple current that are fluctuating from the biasing signal"] and are less than frequencies of a second portion of the ripple [e.g., lower frequency components allowed to pass due to the low pass filter 308, p. 0039 recites "The low pass filter 308 is a sub-circuit that allows signals with frequencies below a certain cutoff frequency to pass through while attenuating signals that are above the cutoff frequency. The low pass filter acts as a frequency-dependent gate, letting lower-frequency components of a signal pass while filtering out the higher- frequency elements. In the context of FIG. 3, the low pass filter allows a biasing current to pass through, or in other words, allows the constant supplied signal, the sensed current, to pass while attenuating the rapid, sensed fluctuations in the signal known as ripple current"].
12. Claim(s) 3 is rejected under 35 U.S.C. 103 as being unpatentable over Lu (US Pub. No. 2025/0055429 A1) in view of Wang (US Pub. No. 2013/0049859 A1) and Shreepathi Bhat (US Pub. No. 2022/0137654 A1); (hereinafter Lu, Wang and Shreepathi Bhat)
Regarding claim 3, Lu [e.g., Fig. 3] discloses the claimed invention except for wherein applying the opposite polarity ripple at the regulated voltage further comprises: delivering the opposite polarity ripple using AC coupling.
Shreepathi Bhat [e.g., Fig. 2] discloses delivering the opposite polarity ripple using AC coupling [e.g., p.0057 lines 1 - 7 recites "The feedforward module 220 receives the (asserted) PSRR signal, VPSRR and the power supply rejection ratio capacitor 288 blocks the direct current (DC) portion of the PSRR signal, VPSRR, such that the noise component of the PSRR signal, VPSRR_AC is provided to the node 286 and amplified by the fourth NFET 282 of the feedforward module 220. In particular, the drain of the fourth NFET 282 that is coupled to the output node 268 of the feedforward module 220 outputs a noise rejection signal, VNOISE_REJ (alternatively referred to as a feedforward signal) is an amplified and inverted version of the PSRR signal, VPSRR_AC, which in turn is an amplified version of the noise in the input voltage, VIN_AC. Conversely, in response to de-assertion of the PSRR signal, VPSRR, the feedforward module 220 de-asserts the noise rejection signal, VNOISE_REJ. In this manner, the dropout detection module 240 and the feedforward module 220 operate in concert to selectively provide a PSRR boost."]
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Lu with delivering the opposite polarity ripple using AC coupling as suggested by Shreepathi Bhat in order to blocks the direct current portion of a signal and extract the noise component.
13. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lu (US Pub. No. 2025/0055429 A1) in view of Wang (US Pub. No. 2013/0049859 A1) and Yang et al (US Patent No. 9,577,613 B2); (hereinafter Lu, Wang and Yang et al).
Regarding claim 8, Lu [e.g., Fig. 3] discloses the claimed invention except for wherein the suppression element includes three GM-GM inverter amplifiers.
Yang et al [e.g., Fig. 4] discloses wherein the suppression element includes three GM-GM inverter amplifiers [e.g., column 10 lines 18 - 23 recites "In FIG. 4, an illustration of the fast push-pull driver 150 having two inverters cascaded is disclosed. However, the scope and spirit of the disclosure may not be limited thereto. For example, another inverter may be additionally connected for an amplification function"].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Lu with wherein the suppression element includes three GM- GM inverter amplifiers as suggested by Yang et al to take advantage amplification characteristics of cascaded inverters.
14. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Lu (US Pub. No. 2025/0055429 A1) in view of Koay et al (US Pub. No. 2022/0308609 A1); (hereinafter Lu and Koay et al).
Regarding claim 20, Lu [e.g., Fig. 3] discloses the claimed invention except for wherein the low drop out linear regulator is comprised in at least one of: a system for performing simulation operations; a system for performing simulation operations to test or validate autonomous machine applications; a system for rendering graphical output; a system for performing deep learning operations; a system implemented using an edge device; a system for generating or presenting virtual reality (VR) content; a system for generating or presenting augmented reality (AR) content; a system for generating or presenting mixed reality (MR) content; a system incorporating one or more Virtual Machines (VMs);a system implemented at least partially in a data center; a system for performing hardware testing using simulation; a system for synthetic data generation; a collaborative content creation platform for 3D assets; or a system implemented at least partially using cloud computing resources.
Koay et al [e.g., Fig. 13] teaches that it is known to wherein the low drop out linear regulator [e.g., LDO Regulator 105] is comprised in at least one of: a system for rendering graphical output [e.g., comprised in system 1305, p. 0076 recites "The system 1305 also includes a user interface 1320 coupled to the controller 830 and an image processor 1330 coupled to the image-sensing circuit 1310. The user interface 1320 is configured to receive an input from the user to capture an image. The user interface 1320 may include a graphical user interface, a button (e.g., shutter button), and/or another type of user interface. The image processor 1330 is configured to receive image data of an image captured by the image-sensing circuit 1310 and process the image data (e.g., perform color correction, noise reduction, etc.). The image processor 1330 may output the processed image to another processor or to a memory for storage"].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Lu with wherein the low drop out linear regulator is comprised in at least one of: a system for performing simulation operations; a system for performing simulation operations to test or validate autonomous machine applications; a system for rendering graphical output; a system for performing deep learning operations; a system implemented using an edge device; a system for generating or presenting virtual reality (VR) content; a system for generating or presenting augmented reality (AR) content; a system for generating or presenting mixed reality (MR) content; a system incorporating one or more Virtual Machines (VMs);a system implemented at least partially in a data center; a system for performing hardware testing using simulation; a system for synthetic data generation; a collaborative content creation platform for 3D assets; or a system implemented at least partially using cloud computing resources to provide a clean regulated voltage to a circuit from a noisy power supply as suggested by Koay et al.
Examiner’s Note
15. Examiner has cited particular columns, paragraphs and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figure may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art disclosed by the Examiner.
16. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Response to Arguments
17. Applicant’s arguments with respect to claim(s) 1, 11 and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
18. Claims 2, 10, 12 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The primary reason for the indication of the allowability of claim 2 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of "wherein producing the opposite polarity ripple further comprises sending the ripple through a first high pass filter; amplifying and inverting the ripple; adjusting a DC biasing of the ripple; and sending the ripple through a second high pass filter".
The primary reason for the indication of the allowability of claim 10 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein one or more frequencies of the third portion of the ripple of the regulated voltage are higher than frequencies of the first portion of the ripple and are lower than frequencies of the second portion of the ripple.”
The primary reason for the indication of the allowability of claim 12 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of "wherein the one or more elements are further to: send the ripple through a first high pass filter; amplify and invert the ripple; adjust a DC biasing of the ripple; and send the ripple through a second high pass filter".
The primary reason for the indication of the allowability of claim 17 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of "wherein the opposite polarity ripple is further produced with a first high pass filter, one or more amplifier inverters, a low speed loop, and a second high pass filter".
Conclusion
19. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
CN 117075670 A1 (Yi et al) discloses an LDO circuit system and an electronic device for solving the problem of damage of output precision caused by unstable power supply with high efficiency and low cost.
20. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
21. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ULARISLAO CORDOVA whose telephone number is (571)272-4690. The examiner can normally be reached Monday-Friday 7:30 - 5:00 ET.
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/ULARISLAO CORDOVA/Examiner, Art Unit 2838
/JEFFREY A GBLENDE/Primary Examiner, Art Unit 2838
Prosecution Insights