DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I and Species I of Figs. 8A-8B in the reply filed on 09/14/2026 and in the Interview Summary on 09/24/2026 is acknowledged.
Claims 7 and 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention or species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 09/14/2026 and in the Interview Summary on 09/24/2026.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/03/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-6 and 9-10 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Lee et al. (US 20220199767 A1).
Regarding claim 1, Lee et al. teach a three-dimensional semiconductor memory device (Fig. 34; [0099]), comprising: a plurality of stack structures (21u, 21d and WL; Fig. 34, [0038, 0036, 0098]) comprising a plurality of interlayer dielectric layers (21u and 21d; Fig. 34, [0038, 0036]) and a plurality of gate electrodes (WL; Fig. 34, [0098]) that are alternately stacked (see Fig. 34) on a substrate (10W; Fig. 34, [0034]); a plurality of vertical channel structures (40; Fig. 34, [0022]) penetrating the plurality of stack structures (21u, 21d and WL); and a separation structure (90; Fig. 34, [0022]) extending in a first direction (the vertical direction in Fig. 34) across between adjacent stack structures (21u, 21d and WL) of the plurality of stack structures (21u, 21d and WL), wherein the separation structure (90) includes: a first portion (an lower portion of 90; see Fig. 34 below) extending in a vertical direction from the substrate (10W) and a second portion (an upper portion of 90; see Fig. 34 below) on the first portion (an lower portion of 90; see Fig. 34 below), the second portion (an upper portion of 90; see Fig. 34 below) including a material (the material of 92) different from ([0100]) a material (the material of 93) of the first portion (an lower portion of 90; see Fig. 34 below), and wherein a level of a top surface of the second portion (an upper portion of 90; see Fig. 34 below) is a same as a level of top surfaces of the plurality of vertical channel structures (40; see Fig. 34 below).
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[AltContent: connector][AltContent: textbox (Second portion of 90)][AltContent: textbox (First portion of 90)][AltContent: connector][AltContent: connector]
Regarding claim 2, Lee et al. teach the three-dimensional semiconductor memory device of claim 1, wherein the separation structure (90) is spaced apart from the plurality of vertical channel structures (40) in a second direction (horizontal direction in Fig. 34), the second direction (horizontal direction in Fig. 34) intersecting the first direction (the vertical direction in Fig. 34).
Regarding claim 3, Lee et al. teach the three-dimensional semiconductor memory device of claim 2, wherein the first portion (an lower portion of 90; see Fig. 34 above) is in contact with the gate electrodes (WL) adjacent to each other in the second direction (horizontal direction in Fig. 34).
Regarding claim 5, Lee et al. teach the three-dimensional semiconductor memory device of claim 1, wherein the first portion (an lower portion of 90; see Fig. 34 above) includes silicon nitride ([0048]), and wherein the second portion (an upper portion of 90; see Fig. 34 above) includes silicon oxide ([0048]).
Regarding claim 6, Lee et al. teach the three-dimensional semiconductor memory device of claim 1, wherein the second portion (an upper portion of 90; see Fig. 34 above) has a shape that is convex toward the substrate (10W, the lower end of the upper portion of 90 is convex toward the substrate 10W; see Fig. 34 above).
Regarding claim 9, Lee et al. teach the three-dimensional semiconductor memory device of claim 1, wherein the separation structure (90) has a largest width at a level (the level of the ST layer; see Fig. 34 above) lower than the top surface of the second portion (an upper portion of 90; see Fig. 34 above).
Regarding claim 10, Lee et al. teach the three-dimensional semiconductor memory device of claim 1, wherein the second portion (an upper portion of 90; see Fig. 34 above) is in an uppermost one of the interlayer dielectric layers (the lower end of an upper portion of 90 is in the uppermost one of the interlayer dielectric layers 21u).
Claim(s) 1, 4 and 8 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Lee et al. (US 20220115390).
Regarding claim 1, Lee et al. teach a three-dimensional semiconductor memory device (Fig. 6; [0120]), comprising: a plurality of stack structures (ILDa, ILDb, ELa and ELb; Fig. 6, [0055]) comprising a plurality of interlayer dielectric layers (ILDa, ILDb; Fig. 6, [0055]) and a plurality of gate electrodes (ELa and ELb; Fig. 6, [0055]) that are alternately stacked (see Fig. 6) on a substrate (100; Fig. 6, [0052]); a plurality of vertical channel structures (VSP used as vertical channels; Fig. 6, [0070]) penetrating the plurality of stack structures (ILDa, ILDb, ELa and ELb); and a separation structure (FL2 and L2 of WC3 separating ILDa and ILDb; Figs. 6 and 7A, [0053, 0110]) extending in a first direction (the vertical direction in Fig. 6) across between adjacent stack structures (ILDa, ILDb, ELa and ELb) of the plurality of stack structures (ILDa, ILDb, ELa and ELb), wherein the separation structure (FL2 and L2 of WC3) includes: a first portion (an lower portion of FL2 and L2 of WC3; see Fig. 6 below) extending in a vertical direction from the substrate (100) and a second portion (an upper portion of FL2 and L2 of WC3; see Fig. 6 below) on the first portion (an lower portion of FL2 and L2 of WC3; see Fig. 6 below), the second portion (an upper portion of FL2 and L2 of WC3; see Fig. 6 below) including a material (the material of L2, silicon nitride; [0107]) different from a material (the material of FL2, polysilicon; [0107]) of the first portion (an lower portion of FL2 and L2 of WC3; see Fig. 6 below), and wherein a level of a top surface of the second portion (an upper portion of FL2 and L2 of WC3; see Fig. 6 below) is a same as a level of top surfaces of the plurality of vertical channel structures (VSP; see Fig. 6 below).
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[AltContent: connector][AltContent: textbox (Second portion of FL2 and L2 of WC3)][AltContent: textbox (First portion of FL2 and L2 of WC3)][AltContent: connector][AltContent: connector]
Regarding claim 4, Lee et al. teach the three-dimensional semiconductor memory device of claim 1, wherein the first portion (an lower portion of FL2 and L2 of WC3; see Fig. 6 above) has a seam (FL2s; Fig. 6, [0106]) therein, and wherein the seam (FL2s) is in contact with the second portion (an upper portion of FL2 and L2 of WC3; see Fig. 6 above).
Regarding claim 8, Lee et al. teach the three-dimensional semiconductor memory device of claim 1, further comprising an interfacial dielectric layer (BLK and L1 of WC3; Figs. 7A and 8, [0117, 0110]) between the plurality of vertical channel structures (VSP) and the gate electrodes (ELa and ELb; Figs. 6, 8), wherein the interfacial dielectric layer (L1 of WC3) extends between the interlayer dielectric layers (ILDa, ILDb) and the separation structure (FL2 and L2 of WC3; Fig. 7A).
Allowable Subject Matter
Claims 13-17 are allowed.
Claims 11-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or suggest, singularly or in combination, at least the limitations of “a selection mold structure on the plurality of stack structures, the selection mold structure including a selection semiconductor layer; and an upper separation structure penetrating the selection mold structure and contacting the second portion” as recited in claim 11 and “a selection mold structure on the plurality of stack structures, the selection mold structure comprising a selection semiconductor layer; an upper separation structure penetrating the selection mold structure and contacting the separation structure; a plurality of upper vertical channel structures penetrating the selection mold structure and correspondingly connected to the plurality of vertical channel structures; and a separation dielectric pattern in the selection mold structure, the separation dielectric pattern penetrating the selection semiconductor layer” as recited in claim 13.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HSIN YI HSIEH whose telephone number is (571)270-3043. The examiner can normally be reached 8:30 - 5:00 pm.
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/HSIN YI HSIEH/Primary Examiner, Art Unit 2899 9/27/2026
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