DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on 07/21/2026 has been entered.
Information Disclosure Statement
3. The Information Disclosure Statement filed on 07/21/2026 has been considered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1,2 and 3 are rejected under 35 USC 103 as being unpatentable over Cahill (US 11742942) in view of Birsan et al; (US 2020/0401540) and further in view of Thomas et al; (Highly Reconfigurable and Integrated Optical Time-Domain Reflectometer Featuring High Spatial Resolution for Short-Reach and Long-Haul Networks- 2021 attached).
Regarding claim 1, Cahill discloses a reflectometer,(an optical time domain reflectometer (OTDR) module 10, see figure 1) comprising: a processing system; ;(processing unit 22, see figure 1) a transmitter and (a transmitter 12, see figure 1) a receiver, wherein the receiver is configured to de-serialize a reflection bitstream from a fiber under test (FUT); (a receiver 14 of the OTDR module 10 then receives light backscattered (Rayleigh backscatter) or reflected (Fresnel reflection) back from various points along the fiber plant 30, see column 3, lines 31-34 and figure 1) and a controller coupled to the processing system, the transmitter, and the receiver, wherein the controller is configured to cause the processing system to perform operations comprising: (the processing unit 22 is in operable communication with the transmitter 12 and the receiver 14 and can include any suitable processing elements, microprocessors, see column 3, lines 15-18 and figure 1) is configured to: sending bits of the de-serialized reflection bitstream to a plurality of processing elements (PEs),( the backscattered and reflected light returned to the OTDR module 10 is then processed by the software and electronics components 20 to produce an OTDR trace that characterizes the fiber plant 30, see column 3, lines 34-38 and figure 1).
However, Cahill does not explicitly disclose sending a signal instructing an address of a block random access memory (BRAM) to be updated, sending results from the plurality of processing elements to a direct memory access (DMA) module, clearing data from the processing elements, decoding the results, and sending the decoded results to a client; and a transceiver comprising: an amplifier wherein the amplifier is configured to generate a logical high signal if a reflected signal in the reflection bitstream is larger than a predetermined threshold.
In a related field of endeavor, Birsan discloses sending a signal instructing an address of a block random access memory (BRAM) to be updated,( DMA controller 102 may be configured to perform DMA transfers of content upon instruction from processor 128 to the system memory (SRAM or DRAM ot BRAM) and may issue an interrupt or other signal to processor 128 that the DMA transfer is finished, see paragraph 34 and figure 1) sending results from the plurality of processing elements to a direct memory access (DMA) module, (DMA bus 108 configured to communicatively connect any suitable elements for DMA transfers and operations, such as DMA controller 102, peripherals 104, 106 based on the instructions form the processor 128, see paragraph 36 and figure 1) clearing data from the processing elements, decoding the results, and sending the decoded results to a client; (contents to be read, written, or otherwise transferred by DMA controller 102 may be stored in an instance of a register bank 126 and further a given DMA transfer require transferring content that is spread across two separate register banks between peripheral A 104 may include register bank 0 120 and register bank 1 121, peripheral B 106 may include register bank 2 124, and system memory 110 may include register bank 3 132, see paragraph 37 and figure 1).
Thus, it would be obvious for one the ordinary skilled in the art before the effective filling date of the invention to combine the DMA controller of Birsan with Cahill to provide intra-chip data transfer between the peripheral devices without using the processor and the motivation is improving the overall system performance, speed, and efficiency.
However, the combination of Cahill and Birsan does not explicitly disclose a transceiver comprising: an amplifier, wherein the amplifier is configured to generate a logical high signal if a reflected signal in the reflection bitstream is larger than a predetermined threshold.
In a related field of endeavor, Thomas discloses a transceiver (Laser diode (DFB-SCL), laser driver, and receiver sub-optical assembly, see figure 1) comprising: an amplifier,(transimpedance amplifier (TIA), see section 2.2 and paragraph 3) wherein the amplifier is configured to generate a logical high signal if a reflected signal in the reflection bitstream is larger than a predetermined threshold ;( The probability distribution function (PDF) of the noise promotes the conversion from voltage to probability based on the number of ‘true’ outputs from the comparator
over a number of samples of a voltage incident on the comparators input (reflected signal comparison) and the number of ‘true’ outputs over a single period of β reference voltages, see section 2.2 and paragraphs 1 and 2).
Thus, it would be obvious for one the ordinary skilled in the art before the effective filling date of the invention to combine the true outputs of Thomas with Cahill and Birsan to provide a number of samples of a voltage incident on the comparators input and the motivation is to decreased cost of the receiver by replacing the need for a costly high-end ADC with a single comparator.
Regarding claim 2, Cahill discloses the reflectometer of claim 1, wherein the reflectometer is a software defined optical time-domain reflectometer (SD-OTDR); (an optical time domain reflectometer (OTDR) module 10 with software and electronics 20, see figure 1).
Regarding claim 3, Cahill discloses the reflectometer of claim 1, further comprising a circulator coupled to the transmitter and to the receiver ;(optical circulator 16 coupled with the transmitter 12 and receiver 14, see figure 14).
Claim 4 is rejected under 35 USC 103 as being unpatentable over Cahill (US 11742942) in view of Birsan et al; (US 2020/0401540), further in view of Thomas et al; (Highly Reconfigurable and Integrated Optical Time-Domain Reflectometer Featuring High Spatial Resolution for Short-Reach and Long-Haul Networks- 2021 attached) and further in view of McClean et al; (US 2024/0068905)
Regarding claim 4, the combination of Cahill, Birsan and Thomas does not explicitly disclose the reflectometer of claim 3, further comprising: an angled physical connector (APC) coupled to the circulator and the FUT, wherein the FUT comprises a single mode optical fiber with two angled physical connector (APC) mattings coupled to the APC.
In a related field of endeavor, McClean discloses the reflectometer (pluggable OTDR, see figure 5) of claim 3, further comprising: an angled physical connector (APC) coupled to the circulator;(pluggable OTDR 100, where in this case optical ports 122, 124 comprise a pair of “angled physical connectors” (APCs) and denoted as 122/APC, 124/APC and an optical circulator 16 is used to control/direct the signal flows between optical transmitter 12, optical receiver 14, see paragraphs 16 and 22 and figures 4 and 5) and the (FUT),(fiber span 20, see figure 4) wherein the FUT comprises a single mode optical fiber with two angled physical connector (APC) mattings coupled to the APC ;(pluggable OTDR 100, where in this case optical ports 122, 124 comprise a pair of “angled physical connectors” (APCs) and denoted as 122/APC, 124/APC, see paragraph 22 and figure 5).
Thus, it would be obvious for one the ordinary skilled in the art before the effective filling date of the invention to combine the angled physical connector of McClean with Cahill, Birsan and Thomas to minimize unwanted back reflections from entering laser or fiber span and motivation is increased efficiency in determining the fault location.
Claims 5,6 and 7 are rejected under 35 USC 103 as being unpatentable over Cahill (US 11742942) in view of Birsan et al; (US 2020/0401540), in view of Thomas et al; (Highly Reconfigurable and Integrated Optical Time-Domain Reflectometer Featuring High Spatial Resolution for Short-Reach and Long-Haul Networks- 2021 attached).
and further in view of Zhong et al; (TW 201301786A).
Regarding claim 5, Cahill does not explicitly disclose the reflectometer of claim 1, wherein the controller comprises: a data processing array, wherein the data processing array includes the plurality of processing elements; a probe controller coupled to the data processing array; the DMA module, wherein the DMA module is coupled to the data processing array and to a memory accessible by the client; and the BRAM, wherein the BRAM is coupled to the probe controller and the transmitter.
In a related field of endeavor, Birsan discloses the reflectometer of claim 1, wherein the controller ;(processor 128, see figure 1) comprises: a data processing array, wherein the data processing array includes the plurality of processing elements,(processor 128 coupled with the memory 110 with plurality of DMA descriptors 112,114,116, see figure 1) wherein the DMA module is coupled to the data processing array (the DMA controller 102 may be configured to perform DMA transfers of content upon instruction from processor 128, see paragraph 34 and figure 1) and to a memory accessible by the client;(plurality of peripherals A,B and C with memories; see figure 1) and the BRAM, wherein the BRAM is coupled ,( DMA controller 102 may be configured to perform DMA transfers of content upon instruction from processor 128 to the system memory (SRAM or DRAM ot BRAM) and may issue an interrupt or other signal to processor 128 that the DMA transfer is finished, see paragraph 34 and figure 1).
Thus, it would be obvious for one the ordinary skilled in the art before the effective filling date of the invention to combine the DMA controller of Birsan with Cahill and Thomas to provide intra-chip data transfer between the peripheral devices without using the processor and the motivation is improving the overall system performance, speed, and efficiency.
However, the combination of Cahill, Birsan and Thomas does not explicitly disclose a probe controller coupled to the data processing array; is coupled to the probe controller and the transmitter.
In a related field of endeavor, Zhong discloses a probe controller coupled to the data processing array; is coupled to the probe controller and the transmitter;(the test sub-module 122 described above may include an OTDR test controller 126 and an OTDR probe 127. The OTDR test controller 126 is connected to the service processing module 111 through a communication interface and is further connected to the light source driver 124 and light source 121, see page 5 and paragraph 6).
Thus, it would be obvious for one the ordinary skilled in the art before the effective filling date of the invention to combine the probe controller of Zhong with Cahill, Birsan and Thomas to collect the reflected signal from the optical coupler and provide the test data to the OTDR test controller and the motivation is to provide extract the test data for fault detection and positioning.
Regarding claim 6, Cahill discloses the reflectometer of claim 5, wherein the controller is further configured to: sending bits of the de-serialized reflection bitstream,( the backscattered and reflected light returned to the OTDR module 10 is then processed by the software and electronics components 20 to produce an OTDR trace that characterizes the fiber plant 30, see column 3, lines 34-38 and figure 1).
However, the combination of Cahill, Thomas and Zhong does not explicitly disclose cause the processing system to perform operations comprising; to the data processing array, wherein the data processing array is configured to send the bits to the PEs.
In a related field of endeavor, Birsan discloses cause the processing system to perform operations comprising; to the data processing array, wherein the data processing array is configured to send the bits to the Pes ,(processor 128 coupled with the memory 110 with plurality of DMA descriptors 112,114,116, see figure 1). Motivation same as claim 6.
Regarding claim 7, Cahill does not explicitly disclose the reflectometer of claim 6, wherein the controller is further configured to cause the processing system to perform operations comprising: sending a control signal from the data processing array to the probe controller, wherein the probe controller is configured to send the signal instructing the address of the BRAM to be updated.
In a related field of endeavor, Birsan discloses the reflectometer of claim 6, wherein the controller is further configured to cause the processing system to perform operations comprising: the address of the BRAM to be updated ,( DMA controller 102 may be configured to perform DMA transfers of content upon instruction from processor 128 to the system memory (SRAM or DRAM ot BRAM) and may issue an interrupt or other signal to processor 128 that the DMA transfer is finished, see paragraph 34 and figure 1). Motivation same as claim 6.
However, the combination of Cahill, Birsan and Thomas does not explicitly disclose send a control signal from the data processing array to the probe controller, wherein the probe controller is configured to send the signal instructing.
In a related field of endeavor, Zhong discloses send a control signal from the data processing array to the probe controller, wherein the probe controller is configured to send the signal instructing;(the test sub-module 122 described above may include an OTDR test controller 126 and an OTDR probe 127. The OTDR test controller 126 is connected to the service processing module 111 through a communication interface and is further connected to the light source driver 124 and light source 121, see page 5 and paragraph 6).
Thus, it would be obvious for one the ordinary skilled in the art before the effective filling date of the invention to combine the probe controller of Zhong with Cahill, Birsan and Thomas to collect the reflected signal from the optical coupler and provide the test data to the OTDR test controller and the motivation is to provide extract the test data for fault detection and positioning.
Claim 8 is rejected under 35 USC 103 as being unpatentable over Cahill (US 11742942) in view of Birsan et al; (US 2020/0401540) and further in view of Thomas et al; (Highly Reconfigurable and Integrated Optical Time-Domain Reflectometer Featuring High Spatial Resolution for Short-Reach and Long-Haul Networks- 2021 attached).
Regarding claim 8, Cahill discloses a reflectometer ,(an optical time domain reflectometer (OTDR) module 10, see figure 1) comprising: a transceiver; (a transmitter 12, and receiver 14, see figure 1) ; wherein the transceiver is configured to de-serialize a reflection bitstream from a fiber under test (FUT), (a receiver 14 of the OTDR module 10 then receives light backscattered (Rayleigh backscatter) or reflected (Fresnel reflection) back from various points along the fiber plant 30, see column 3, lines 31-34 and figure 1) and a controller coupled to the transceiver ;(the processing unit 22 is in operable communication with the transmitter 12 and the receiver 14 and can include any suitable processing elements, microprocessors, see column 3, lines 15-18 and figure 1) wherein the controller is configured to: sending bits of the de-serialized reflection bitstream to a plurality of processing elements (PEs),( the backscattered and reflected light returned to the OTDR module 10 is then processed by the software and electronics components 20 to produce an OTDR trace that characterizes the fiber plant 30, see column 3, lines 34-38 and figure 1).
However, Cahill does not explicitly disclose cause a processor to perform operations comprising: sending a signal instructing an address of a block random access memory (BRAM) to be updated, sending results from the plurality of processing elements to a direct memory access (DMA) module, clearing data from the processing elements, decode the results, and sending the decoded results to a client, an amplifier, wherein the amplifier is configured to generate a logical high signal if a reflected signal in the reflection bitstream is larger than a predetermined threshold.
In a related field of endeavor, Birsan discloses cause a processor to perform operations comprising: sending a signal instructing an address of a block random access memory (BRAM) to be updated, ( DMA controller 102 may be configured to perform DMA transfers of content upon instruction from processor 128 to the system memory (SRAM or DRAM ot BRAM) and may issue an interrupt or other signal to processor 128 that the DMA transfer is finished, see paragraph 34 and figure 1) sending results from the plurality of processing elements to a direct memory access (DMA) module, (DMA bus 108 configured to communicatively connect any suitable elements for DMA transfers and operations, such as DMA controller 102, peripherals 104, 106 based on the instructions form the processor 128, see paragraph 36 and figure 1) clearing data from the processing elements, decoding the results, and send the decoded results to a client; (contents to be read, written, or otherwise transferred by DMA controller 102 may be stored in an instance of a register bank 126 and further a given DMA transfer require transferring content that is spread across two separate register banks between peripheral A 104 may include register bank 0 120 and register bank 1 121, peripheral B 106 may include register bank 2 124, and system memory 110 may include register bank 3 132, see paragraph 37 and figure 1).
Thus, it would be obvious for one the ordinary skilled in the art before the effective filling date of the invention to combine the DMA controller of Birsan with Cahill to provide intra-chip data transfer between the peripheral devices without using the processor and the motivation is improving the overall system performance, speed, and efficiency.
However, the combination of Cahill and Birsan does not explicitly disclose an amplifier, wherein the amplifier is configured to generate a logical high signal if a reflected signal in the reflection bitstream is larger than a predetermined threshold.
In a related field of endeavor, Thomas discloses an amplifier,(transimpedance amplifier (TIA), see section 2.2 and paragraph 3) wherein the amplifier is configured to generate a logical high signal if a reflected signal in the reflection bitstream is larger than a predetermined threshold ;( The probability distribution function (PDF) of the noise promotes the conversion from voltage to probability based on the number of ‘true’ outputs from the comparator over a number of samples of a voltage incident on the comparators input (reflected signal comparison) and the number of ‘true’ outputs over a single period of β reference voltages, see section 2.2 and paragraphs 1 and 2).
Thus, it would be obvious for one the ordinary skilled in the art before the effective filling date of the invention to combine the true outputs of Thomas with Cahill and Birsan to provide a number of samples of a voltage incident on the comparators input and the motivation is to decreased cost of the receiver by replacing the need for a costly high-end ADC with a single comparator.
Claims 9,10 and 11 are rejected under 35 USC 103 as being unpatentable over Cahill (US 11742942) in view of Birsan et al; (US 2020/0401540), further in view of Thomas et al; (Highly Reconfigurable and Integrated Optical Time-Domain Reflectometer Featuring High Spatial Resolution for Short-Reach and Long-Haul Networks- 2021 attached) and further in view of Zhong et al; (TW 201301786A).
Regarding claim 9, Cahill does not explicitly disclose the reflectometer of claim 8, wherein the controller comprises: a data processing array, wherein the data processing array includes the plurality of PEs; a probe controller coupled to the data processing array; the DMA module, wherein the DMA module is coupled to the data processing array and to a memory accessible by the client; and the BRAM, wherein the BRAM is coupled to the probe controller and the transmitter.
In a related field of endeavor, Birsan discloses the reflectometer of claim 8, wherein the controller ;(processor 128, see figure 1) comprises: a data processing array, wherein the data processing array includes the plurality of PEs; (processor 128 coupled with the memory 110 with plurality of DMA descriptors 112,114,116, see figure 1) the DMA module, wherein the DMA module is coupled to the data processing array (the DMA controller 102 may be configured to perform DMA transfers of content upon instruction from processor 128, see paragraph 34 and figure 1) and to a memory accessible by the client;(plurality of peripherals A,B and C with memories; see figure 1) and the BRAM, wherein the BRAM is coupled to ,( DMA controller 102 may be configured to perform DMA transfers of content upon instruction from processor 128 to the system memory (SRAM or DRAM ot BRAM) and may issue an interrupt or other signal to processor 128 that the DMA transfer is finished, see paragraph 34 and figure 1).
Thus, it would be obvious for one the ordinary skilled in the art before the effective filling date of the invention to combine the DMA controller of Birsan with Cahill and Thomas to provide intra-chip data transfer between the peripheral devices without using the processor and the motivation is improving the overall system performance, speed, and efficiency.
However, the combination of Cahill, Birsan and Thomas does not explicitly disclose the probe controller and the transmitter, a probe controller coupled to the data processing array.
In a related field of endeavor, Zhong discloses the probe controller and the transmitter, a probe controller coupled to the data processing array ;(the test sub-module 122 described above may include an OTDR test controller 126 and an OTDR probe 127. The OTDR test controller 126 is connected to the service processing module 111 through a communication interface and is further connected to the light source driver 124 and light source 121, see page 5 and paragraph 6).
Thus, it would be obvious for one the ordinary skilled in the art before the effective filling date of the invention to combine the probe controller of Zhong with Cahill, Birsan and Thomas to collect the reflected signal from the optical coupler and provide the test data to the OTDR test controller and the motivation is to provide extract the test data for fault detection and positioning.
Regarding claim 10, Cahill discloses the reflectometer of claim 9, wherein is configured to: receive the bits; and send the bits to the Pes; ,( the backscattered and reflected light returned to the OTDR module 10 is then processed by the software and electronics components 20 to produce an OTDR trace that characterizes the fiber plant 30, see column 3, lines 34-38 and figure 1).
However, the combination of Cahill, Thomas and Zhong does not explicitly disclose the data processing array.
In a related field of endeavor, Birsan discloses processing array ,(processor 128 coupled with the memory 110 with plurality of DMA descriptors 112,114,116, see figure 1). Motivation same as claim 9.
Regarding claim 11, Cahill does not explicitly disclose the reflectometer of claim 10, wherein the controller is further configured to cause the processor to perform operations comprising: sending a control signal from the data processing array to the probe controller, wherein the probe controller is configured to send the signal instructing the address of the BRAM to be updated.
In a related field of endeavor, Birsan discloses the reflectometer of claim 10, wherein the controller is further configured to cause the processor to perform operations comprising: sending a control signal from the data processing array, send the signal instructing the address of the BRAM to be updated; ( DMA controller 102 may be configured to perform DMA transfers of content upon instruction from processor 128 to the system memory (SRAM or DRAM ot BRAM) and may issue an interrupt or other signal to processor 128 that the DMA transfer is finished, see paragraph 34 and figure 1). Motivation same as claim 9.
However, the combination of Cahill, Birsan and Thomas does not explicitly disclose the probe controller, wherein the probe controller is configured to.
In a related field of endeavor, Zhong the probe controller, wherein the probe controller is configured to ;(the test sub-module 122 described above may include an OTDR test controller 126 and an OTDR probe 127. The OTDR test controller 126 is connected to the service processing module 111 through a communication interface and is further connected to the light source driver 124 and light source 121, see page 5 and paragraph 6).
Thus, it would be obvious for one the ordinary skilled in the art before the effective filling date of the invention to combine the probe controller of Zhong with Cahill, Birsan and Thomas to collect the reflected signal from the optical coupler and provide the test data to the OTDR test controller and the motivation is to provide extract the test data for fault.
Claims 12, 13, 14, and 18 are rejected under 35 USC 103 as being unpatentable over Cahill (US 11742942) in view of Birsan et al; (US 2020/0401540), further in view of Zhong et al; (TW 201301786A) and further in view of Thomas et al; (Highly Reconfigurable and Integrated Optical Time-Domain Reflectometer Featuring High Spatial Resolution for Short-Reach and Long-Haul Networks- 2021 attached).Regarding claim 12, Cahill discloses a system on a chip (SoC), ,(an optical time domain reflectometer (OTDR) module 10 on optical transmitter 12 and receiver 14, see figure 1) comprising: a transceiver, wherein the transceiver is configured to de-serialize a reflection bitstream from a fiber under test (FUT); (a transmitter 12 and a receiver 14 of the OTDR module 10 then receives light backscattered (Rayleigh backscatter) or reflected (Fresnel reflection) back from various points along the fiber plant 30, see column 3, lines 31-34 and figure 1) and a controller coupled to the transceiver, wherein the controller;(the processing unit 22 is in operable communication with the transmitter 12 and the receiver 14 and can include any suitable processing elements, microprocessors, see column 3, lines 15-18 and figure 1) comprises: a data processing array coupled to the transceiver, wherein the data processing array comprises a plurality of processing elements (PEs), ( the backscattered and reflected light returned to the OTDR module 10 is then processed by the software and electronics components 20 to produce an OTDR trace that characterizes the fiber plant 30, see column 3, lines 34-38 and figure 1), and wherein the data processing array is configured to perform operations comprising: receiving the de-serialized reflection bitstream, sending the de-serialized reflection bitstream to the PEs, (a transmitter 12 and a receiver 14 of the OTDR module 10 then receives light backscattered (Rayleigh backscatter) or reflected (Fresnel reflection) back from various points along the fiber plant 30 and reflected light returned to the OTDR module 10 is then processed by the software and electronics components 20 to produce an OTDR trace that characterizes the fiber plant 30, see column 3, lines, see column 3, lines 31-38 and figure 1).
However, Cahill does not explicitly disclose receiving laser control values from a client, wherein the laser control values correspond to a laser; sending the laser control values to a laser control module, and sending results from the plurality of processing elements to a direct memory access (DMA) module; the laser control module configured to program a laser driver based on the values; and the direct memory access (DMA) module, wherein the DMA module is coupled to the data processing array and to a memory accessible by the client, and wherein the DMA module is configured to send the results to the memory accessible by the client and an amplifier, wherein the amplifier is configured to generate a logical high signal if a reflected signal in the reflection bitstream is larger than a predetermined threshold.
In a related field of endeavor, Birsan discloses sending results from the plurality of processing elements to a direct memory access (DMA) module; and the direct memory access (DMA) module,( DMA controller 102 may be configured to perform DMA transfers of content upon instruction from processor 128 to the system memory (SRAM or DRAM ot BRAM) and may issue an interrupt or other signal to processor 128 that the DMA transfer is finished, see paragraph 34 and figure 1), wherein the DMA module is coupled to the data processing array and to a memory accessible by the client, (DMA bus 108 configured to communicatively connect any suitable elements for DMA transfers and operations, such as DMA controller 102, peripherals 104, 106 based on the instructions form the processor 128, see paragraph 36 and figure 1) and wherein the DMA module is configured to send the results to the memory accessible by the client (contents to be read, written, or otherwise transferred by DMA controller 102 may be stored in an instance of a register bank 126 and further a given DMA transfer require transferring content that is spread across two separate register banks between peripheral A 104 may include register bank 0 120 and register bank 1 121, peripheral B 106 may include register bank 2 124, and system memory 110 may include register bank 3 132, see paragraph 37 and figure 1).
Thus, it would be obvious for one the ordinary skilled in the art before the effective filling date of the invention to combine the DMA controller of Birsan with Cahill to provide intra-chip data transfer between the peripheral devices without using the processor and the motivation is improving the overall system performance, speed, and efficiency.
However, the combination of Cahill and Birsan does not explicitly disclose receiving laser control values from a client, wherein the laser control values correspond to a laser; sending the laser control values to a laser control module, the laser control module configured to program a laser driver based on the values, and an amplifier, wherein the amplifier is configured to generate a logical high signal if a reflected signal in the reflection bitstream is larger than a predetermined threshold.
In a related field of endeavor, Zhong discloses receiving laser control values from a client, wherein the laser control values correspond to a laser; sending the laser control values to a laser control module, the laser control module configured to program a laser driver based on the values ;(the OTDR test controller 126 can receive the OTDR test command from the service processing module 111 through the above communication interface, and correspondingly start the OTDR test and provide the OTDR test signal to the light source driver 124, and the OTDR test signal may be modulated to the output light of the light source 123 and output to the optical distribution network 130 through the optical coupler 113, and the OTDR test signal is in each of the optical fiber links, see page 5 and paragraph 6, page 6 and paragraph 1 and figure 2).
Thus, it would be obvious for one the ordinary skilled in the art before the effective filling date of the invention to combine the laser controller of Zhong with Cahill and Birsan to provide the drive signal to the laser based on the received test and/or control signal and the motivation is to provide extract the test data for fault detection and positioning.
However, the combination of Cahill, Birsan and Zhong does not explicitly disclose an amplifier, wherein the amplifier is configured to generate a logical high signal if a reflected signal in the reflection bitstream is larger than a predetermined threshold.
In a related field of endeavor, Thomas discloses an amplifier, (transimpedance amplifier (TIA), see section 2.2 and paragraph 3) wherein the amplifier is configured to generate a logical high signal if a reflected signal in the reflection bitstream is larger than a predetermined threshold ;(the probability distribution function (PDF) of the noise promotes the conversion from voltage to probability based on the number of ‘true’ outputs from the comparator over a number of samples of a voltage incident on the comparators input (reflected signal comparison) and the number of ‘true’ outputs over a single period of β reference voltages, see section 2.2 and paragraphs 1 and 2).
Thus, it would be obvious for one the ordinary skilled in the art before the effective filling date of the invention to combine the true outputs of Thomas with Cahill, Birsan and Zhong to provide a number of samples of a voltage incident on the comparators input and the motivation is to decreased cost of the receiver by replacing the need for a costly high-end ADC with a single comparator
Regarding claim 13, the combination of Cahill, Birsan and Thomas does not explicitly disclose the SoC of claim 12, wherein the values are configured to enable a bias of the laser and a modulation of the laser to be set.
In a related field of endeavor, Zhong discloses the SoC of claim 12, wherein the values are configured to enable a bias of the laser and a modulation of the laser to be set; (light source driver 124 may include a controller 131, an optical power monitoring unit 132, a bias current adjustment unit 133, a modulation current adjustment unit 134, and a modulation circuit 135, see page 6, paragraph 3 and figure 3). Motivation same as claim 12.
Regarding claim 14, the combination of Cahill, Birsan and Thomas does not explicitly disclose the SoC of claim 12, wherein the values are further configured to enable equalization, eye crossing, and de-emphasis of the laser.
In a related field of endeavor, Zhong discloses the SoC of claim 12, wherein the values are further configured to enable equalization, eye crossing, and de-emphasis of the laser; (light source driver 124 may include a controller 131, an optical power monitoring unit 132, a bias current adjustment unit 133, a modulation current adjustment unit 134, and a modulation circuit 135, see page 6, paragraph 3 and figure 3). Motivation same as claim 12.
Regarding claim 18, Zhong discloses the SoC of claim 12, wherein the SoC further comprises: a receiver optical sub-assembly (ROSA) ;(OTDR with receiver 14, see figure 1).
Claims 15 and 17 are rejected under 35 USC 103 as being unpatentable over Cahill (US 11742942) in view of Birsan et al; (US 2020/0401540) and further in view of Zhong et al; (TW 201301786A), further in view of Thomas et al; (Highly Reconfigurable and Integrated Optical Time-Domain Reflectometer Featuring High Spatial Resolution for Short-Reach and Long-Haul Networks- 2021 attached) and further in view of Shan et al; (CN 108180978A).
Regarding claim 15, the combination of Cahill, Birsan, Zhong and Thomas does not explicitly disclose the SoC of claim 12, wherein the SoC further comprises: a plurality of circulators.
In a related field of endeavor, Shan discloses the SoC of claim 12, wherein the SoC further comprises: a plurality of circulators ;( OTDR technology detecting optical fibre vibration, in fibre optical network with first circulator 5, second circulator 7 and third circulator 9, see figure 1).
Thus, it would be obvious for one the ordinary skilled in the art before the effective filling date of the invention to combine the plurality of circulators of Shan with Cahill, Birsan, Zhong and Thomas to provide coupling of the plurality of optical signals at various locations of the optical network and the motivation is to provide increased efficiency in detection fibre loss at various location of the fibre network.
Regarding claim 17, the combination of Cahill, Birsan, Zhong and Thomas does not explicitly disclose the SoC of claim 12, wherein the SoC further comprises: a distributive feedback semiconductor laser (DFB-SCL) coupled to the laser driver.
In a related field of endeavor, Shan discloses the SoC of claim 12, wherein the SoC further comprises: a distributive feedback semiconductor laser (DFB-SCL) coupled to the laser driver; (the laser diode 1 is a DFB laser diode or a DBR laser diode OTDR technology detecting optical fibre vibration, see page 6 and line 8 and figure 1).
Thus, it would be obvious for one the ordinary skilled in the art before the effective filling date of the invention to combine the distributed feedback laser of Shan with Cahill, Birsan, Zhong and Thomas to provide stable operating characteristics and operating wavelength for transmitting the OTDR test pulse and motivation is to provide highly stable operating wavelength.
Claims 19 and 20 are rejected under 35 USC 103 as being unpatentable over Cahill (US 11742942) in view of Birsan et al; (US 2020/0401540) and further in view of Zhong et al; (TW 201301786A), further in view of Thomas et al; (Highly Reconfigurable and Integrated Optical Time-Domain Reflectometer Featuring High Spatial Resolution for Short-Reach and Long-Haul Networks- 2021 attached) and further in view of So et al; (US 5179420).
Regarding claim 19, the combination of Cahill, Birsan, Zhong and Thomas does not explicitly disclose the SoC of claim 12, wherein the SoC further comprises: a thermos-electric cooler controller (TEC_CTRL).
In a related field of endeavor, Shaan discloses the SoC of claim 12, wherein the SoC further comprises: a thermos-electric cooler controller (TEC_CTRL) ;( the tunable optical source 10 of the OTDR, the temperature of the semiconductor laser 40 is controlled by the control unit 16, via the thermo-electric cooler 44, see column 5, lines 46-49 and figure 2).
Thus, it would be obvious for one the ordinary skilled in the art before the effective filling date of the invention to combine the thermos electric cooler of So with Cahill, Birsan, Zhong and Thomas to produce the optical signal with variable, controlled, wavelengths (frequency) and the motivation is to provide wavelength (frequency) dependent loss information for the optical fiber path being tested.
Regarding claim 20, the combination of Cahill, Birsan, Zhong and Thomas does not explicitly disclose the SoC of claim 12, wherein the laser control module is configured to program the laser driver to adjust a frequency of the laser by varying its temperature.
In a related field of endeavor, Shaan discloses the SoC of claim 12, wherein the laser control module is configured to program the laser driver to adjust a frequency of the laser by varying its temperature ;( the tunable optical source 10 of the OTDR, the temperature of the semiconductor laser 40 is controlled by the control unit 16, via the thermo-electric cooler 44, see column 5, lines 46-49 and figure 2). Motivation same as claim 19.
Allowable Subject Matter
Claim 21 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
3 .The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is reproduced below.
a. Pedersen et al; (US 2024/0320174) discloses a direct memory access (DMA) controller (112) is coupled to the bus system at a bus connection point and BRAM (106
108) coupled to the bus system, see figure 1.
b. McClean et al; (US 2024/0068905) discloses a pluggable OTDR that utilizes a specific architecture that separates its passive optical elements from the remaining active optical and electrical elements, see figure 2.
c. Thomas et al (Software defined optical time-domain reflectometer -2022 attached) discloses Software defined optical time-domain reflectometer with direct memory access module and block RAM, see figure 1.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMRITBIR K SANDHU whose telephone number is (571)270-1894. The examiner can normally be reached M-F 9am to 5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kenneth Vanderpuye can be reached at 571-272-3078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AMRITBIR K SANDHU/ Primary Examiner, Art Unit 2634
Prosecution Insights