DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species C in the reply filed on 4/17/2026 is acknowledged.
Applicant stated that Species C includes claims 1-15 and 17-20. However, Examiner disagrees. It is noted that claim 9 corresponds to species D; claim 11 corresponds to Species E; Claim 12 corresponds to Species F; Claims 13 and 15 correspond to Species G; Claim 14 corresponds to Species H; and claim 17 corresponds to Species K.
As such, claims 9, 11-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 4/17/2026.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/04/2024 and 11/27/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 7, 8, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (2021/0210022; hereinafter Chang) in view of Lim et al. (US 2018/0336814; hereinafter Lim).
Regarding claim 1:
Chang discloses a display panel, comprising a substrate, a display region and a non-display region (see Figs. 2-3, and 19),
wherein the display region comprises a plurality of data lines (see Fig. 2; data lines D), and the non-display region comprises a demultiplexing circuit, a fanout wire, and a clock signal line (see Figs. 3 and 19); an input terminal of the demultiplexing circuit is electrically connected to the fanout wire, an output terminal of the demultiplexing circuit is electrically connected to a data line of the data lines (see Fig. 19; the lines in fanout region is directly inputted into the demultiplexing circuit 20A-2), and a control terminal of the demultiplexing circuit is electrically connected to the clock signal line (see Fig. 3 and paragraph [0049]).
Chang does not disclose the display panel further comprises an isolation signal line, the isolation signal line comprises an isolation portion, and an orthographic projection of the isolation portion on a plane in which the substrate is located is between an orthographic projection of the clock signal line on the plane in which the substrate is located and an orthographic projection of the fanout wire on the plane in which the substrate is located.
In the same field of endeavor, Lim discloses a display panel (see Figs. 1-6) comprising:
an isolation signal line, the isolation signal line comprises an isolation portion (see Fig. 5; shielding line SLL), and an orthographic projection of the isolation portion on a plane in which the substrate is located is between an orthographic projection of the clock signal line on the plane in which the substrate is located and an orthographic projection of the fanout wire on the plane in which the substrate is located (see Figs. 2-6; SL1 or SLL is between VL4 (equivalent to clock signal lines) and fanout lines DTL).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to combine the teaching of Chang and Lim such that the display panel further comprises an isolation signal line, the isolation signal line comprises an isolation portion, and an orthographic projection of the isolation portion on a plane in which the substrate is located is between an orthographic projection of the clock signal line on the plane in which the substrate is located and an orthographic projection of the fanout wire on the plane in which the substrate is located. The combination would have yielded a predictable result of realizing a display panel with improved display quality by preventing noise from interfering with the data signal being transmitted by the transmitting lines (see Lim, paragraph [0063]).
Regarding claim 7:
Chang and Lim disclose all the features in claim 1. Lim further discloses the display panel, wherein the isolation signal line comprises a fixed potential signal line (see paragraph [0090]; “A ground voltage is applied to the first shielding line SL1 and the second shielding line SL2”; ground voltage is a fixed potential signal).
Regarding claim 8:
Chang and Lim disclose all the feature in claim 7. Lim further disclose the display panel, wherein the isolation signal line comprises at least one of a display test signal line, a common voltage signal line, and an electrostatic lead-out wire (see paragraph [0090]; line connected to the ground voltage is interpreted as an electrostatic lead-out wire).
Regarding claim 18:
Claim 18 recites similar limitations as in claim 1. Hence, claim 18 is rejected under the same reason as discussed above in claim 1.
Claim(s) 2-6 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of Lim as applied to claim 1 above, and further in view of Deng et al. (CN115729004A; hereinafter Deng).
Regarding claim 2:
Chang and Lim disclose all the features in claim 1. Chang and Lim do not disclose the first output terminal group and the second output terminal group are arranged in a first direction, wherein the first direction is parallel to the plane in which the substrate is located; and in the first direction, at least a portion of the clock signal line is located between the first output terminal group and the second output terminal group.
In the same field of endeavor, Deng discloses a display panel (see Fig. 12), wherein the display panel comprises a first fanout wire group and a second fanout wire group (see Fig. 12; signal lines 10 on the left side and signal lines 10 on the right side); and the first fanout wire group and the second fanout wire group each comprise a plurality of fanout wires (see Fig. 12; there a plurality of signal lines 10 in each group); the display panel further comprises a first output terminal group and a second output terminal group, each of the first output terminal group and the second output terminal group comprises a plurality of output bonding terminals, the plurality of fanout wires in the first fanout wire group are electrically connected to the plurality of output bonding terminals in the first output terminal group, and the plurality of fanout wires in the second fanout wire group are electrically connected to the output bonding terminals in the second output terminal group (see Fig. 12; output bonding pads 201 on the left side corresponds to the output bonding terminals in the first output terminal group; output bonding pads 201 on the right side corresponds to the output bonding terminals in the second output terminal group); and the first output terminal group and the second output terminal group are arranged in a first direction (see Fig. 12; the first output terminal group and the second output terminal group are arranged in the x direction), wherein the first direction is parallel to the plane in which the substrate is located (see Fig. 12); and in the first direction, at least a portion of the clock signal line is located between the first output terminal group and the second output terminal group (see Fig. 12; signal lines 40 corresponds to the clock signal, which is located between the first output terminal group and the second output terminal group).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to combine the teaching of Chang, Lim and Deng such that the display panel comprises a first fanout wire group and a second fanout wire group, and the first fanout wire group and the second fanout wire group each comprise a plurality of fanout wires; the display panel further comprises a first output terminal group and a second output terminal group, each of the first output terminal group and the second output terminal group comprises a plurality of output bonding terminals, the plurality of fanout wires in the first fanout wire group are electrically connected to the plurality of output bonding terminals in the first output terminal group, and the plurality of fanout wires in the second fanout wire group are electrically connected to the output bonding terminals in the second output terminal group; and the first output terminal group and the second output terminal group are arranged in a first direction, wherein the first direction is parallel to the plane in which the substrate is located; and in the first direction, at least a portion of the clock signal line is located between the first output terminal group and the second output terminal group. The combination would have yielded a predictable result of shielding signal interference between the clock signal lines that are located in the middle region and the data lines that are located on both sides of the clock signal lines.
Regarding claim 3:
Chang, Lim and Deng disclose all the features in claim 2. Chang further discloses the display panel, wherein the display panel comprises a first driver chip and a second driver chip, wherein the first driver chip is bound and electrically connected to the first output terminal group (see Fig. 19; D-IC on the left side is a first driver chip, which is bound and electrically connected to the first output terminal group in the left fanout region), and the second driver chip is bound and electrically connected to the second output terminal group (see Fig. 19; D-IC on the right side is a second driver chip, which is bound and electrically connected to the second output terminal group in the right fanout region).
Regarding claim 4:
Chang and Lim disclose all the features in claim 1. Chang and Lim do not disclose the display panel, wherein a film layer in which the isolation portion is located is not out of a film layer range defined by a film layer in which the fanout wire is located and a film layer in which the clock signal line is located.
In the same field of endeavor, Deng discloses a display panel, wherein a film layer in which the isolation portion is located is not out of a film layer range defined by a film layer in which the fanout wire is located and a film layer in which the clock signal line is located (see English translation, page 7, 3rd paragraph and page 9, 3rd paragraph; Deng specifies that film layer position of the isolation portion is not specifically limited and can be same or different layer from the other signal line).
As such, before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to combine the teaching of Chang, Lim, and Deng such that a film layer in which the isolation portion is located is not out of a film layer range defined by a film layer in which the fanout wire is located and a film layer in which the clock signal line is located. The combination would have yielded a predictable of result of improving display quality by shielding interference between the clock signal lines and the data signal lines.
Regarding claim 5:
Chang, Lim, and Deng disclose all the features in claim 4. Deng further disclose the display panel, wherein the isolation portion is arranged in a same layer as at least one of the fanout wire and the clock signal line (see English translation, page 9, 3rd paragraph; Deng specifies that film layer position of the isolation portion can be same layer as the other signal line).
Regarding claim 6:
Chang, Lim, and Deng disclose all the features in claim 4. Chang, Lim and Deng do not expressly disclose the display panel, wherein the fanout wire and the clock signal line are arranged in different layers, and the film layer in which the isolation portion is located is between the film layer in which the fanout wire is located and the film layer in which the clock signal line is located.
However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to arrange the film layer in which the isolation portion is located between the film layer in which the fanout wire is located and the film layer in which the clock signal line is located in order to shield the signals from each other, where the claimed differences involved to the substitution of interchangeable or replaceable equivalents and the reason for the selection of one equivalent for another was not to solve an existent problem, such substitution has been judicially determined to have been obvious. In re Ruff, 118, USPQ, 343 (CCPA 1958). This supporting is based on a recognition that the claimed difference exist not a result of an attempt by applicant to solve a problem but merely amounts to selection of expedients known to the artisan of ordinary skill as design choices.
Regarding claim 19:
Claim 19 recites similar limitations as in claim 2. Hence, claim 19 is rejected under the same reasons as discussed above in claim 2.
Regarding claim 20:
Claim 20 recites similar limitations as in claim 3. Hence, claim 20 is rejected under the same reasons as discussed above in claim 3.
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
In regards to claim 10, none of the reference of record alone or in combination discloses or suggests the display panel according to claim 8, wherein the display test signal line comprises at least one of a display test switch signal line and a display test data signal line.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Xu et al. (US 2024/0047480) discloses a display panel with projection of a plurality of output terminals not overlapping projection of a plurality of input terminals to prevent interference.
Zheng et al. (US 2022/0216290) discloses a display device comprises at least one shielded wire located between the touch control lead wire and the data lead wire, and the at least one shielded wire is grounded or connected to a fixed potential.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LIXI CHOW SIMPSON whose telephone number is (571)272-7571. The examiner can normally be reached Mon-Fri 7:00am-3:00pm.
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/LIXI C SIMPSON/ Primary Examiner, Art Unit 2625
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