DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendments, filed 4/1/2026, have been entered and made of record. Claims 1, 4, 7, 10, 13 and 20 have been amended. Claims 1-20 are pending.
Response to Arguments
Applicant’s arguments in the Remarks filed on 4/1/2026 have been considered but are moot in view of the new ground(s) of rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Wang in view of Gajjala and Carroll
Claims 1-3 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al.(USPubN 2022/0360799; hereinafter Wang) in view of Gajjala et al.(USPubN 2022/0345392; hereinafter Gajjala) further in view of Carroll(USPubN 2008/0068458).
As per claim 1, Wang teaches an electronic device for processing and playing a video transmitted from an input device(“A computing device performs a method of decoding video data by receiving bitstream encoding a chroma block, a corresponding luma block, neighboring luma samples, and neighboring chroma samples” in Abs, Fig. 1), the electronic device comprising:
a plurality of video processors configured to perform processing operations based on a test video including a plurality of frames received from the input device to generate a sampling video including the plurality of frames, wherein each of the plurality of frames includes at least one pattern; and a processor configured to receive the sampling video from the plurality of video processor (“In a typical video coding process, a video sequence typically includes an ordered set of frames or pictures. Each frame may include three sample arrays, denoted SL, SCb, and SCr. SL is a two-dimensional array of luma samples. SCb is a two-dimensional array of Cb chroma samples. SCr is a two-dimensional array of Cr chroma samples. In other instances, a frame may be monochrome and therefore includes only one two-dimensional array of luma samples.” In Para.[0060], “each CTU may comprise one coding tree block (CTB) of luma samples, two corresponding coding tree blocks of chroma samples, and syntax elements used to code the samples of the coding tree blocks. The syntax elements describe properties of different types of units of a coded block of pixels and how the video sequence can be reconstructed at the video decoder 30, including inter or intra prediction, intra prediction mode, motion vectors, and other parameters. In monochrome pictures or pictures having three separate color planes, a CTU may comprise a single coding tree block and syntax elements used to code the samples of the coding tree block. A coding tree block may be an N×N block of samples” in Para.[0061], “motion estimation unit 42 determines the inter prediction mode for a current video frame by generating a motion vector, which indicates the displacement of a prediction unit (PU) of a video block within the current video frame relative to a predictive block within a reference video frame, according to a predetermined pattern within a sequence of video frames. Motion estimation, performed by motion estimation unit 42, is the process of generating motion vectors, which estimate motion for video blocks. A motion vector, for example, may indicate the displacement of a PU of a video block within a current video frame or picture relative to a predictive block within a reference frame (or other coded unit) relative to the current block being coded within the current frame (or other coded unit). The predetermined pattern may designate video frames in the sequence as P frames or B frames. Intra BC unit 48 may determine vectors, e.g., block vectors, for intra BC coding in a manner similar to the determination of motion vectors by motion estimation unit 42 for inter prediction, or may utilize motion estimation unit 42 to determine the block vector.” in Para.[0035], “Video encoder 20 and video decoder 30 each may be implemented as any of a variety of suitable encoder circuitry, such as one or more microprocessors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), discrete logic, software, hardware, firmware or any combinations thereof. When implemented partially in software, an electronic device may store instructions for the software in a suitable, non-transitory computer-readable medium and execute the instructions in hardware using one or more processors to perform the video coding/decoding operations disclosed in the present disclosure” in Para.[0029], The video sequence can be interpreted as a test video because it includes set of frames and received from a camera. The encoded frames can be a sampling video because it includes the plurality of frames and it’s from the plurality of video processors. The predetermined pattern are included in the plurality of frames.),
Wang is silent about wherein the processor is configured to determine an output order of each of the plurality of frames of the sampling video and whether the sampling video is output normally or not, based on the at least one pattern, wherein the processor is further configured to determine whether an error has occurred in at least one of the input device and the plurality of video processors, based on the at least one pattern, and wherein the at least one pattern corresponds to each of the output order of each of the plurality of frames and whether the sampling video is output normally or not.
Gajjala teaches wherein the processor is configured to determine an output order of each of the plurality of frames of the sampling video and whether the sampling video is output normally or not, based on the at least one pattern, and wherein the at least one pattern corresponds to whether the sampling video is output normally or not (“the test frame format comprises a header, payload and a trailer. The payload information includes payload test frame information including the sequence number, the transmit timestamp, the payload checksum, the flow identifier, and the control information. The payload may include additional data, such as a bit pattern, e.g., pseudorandom binary sequence (PRBS) pattern, to be analyzed for bit error measurements. When the test device 200 receives the aggregated streams, such as the received streams shown in FIG. 5, the test device 200 decodes the payload test frame information to determine the stream identifiers for each received test frame. The test device 200 maps each test frame to a test stream, which enables the test device 200 to determine Y.1564 KPIs for the LAG, such as frame loss ratio, bandwidth, latency, latency variation, etc.” in Para.[0036], “the LAG is tested and if any issues are detected, such as a KPI of the LAG being outside a threshold, each port of the LAG may be independently tested in a non-LAG mode to identify a cause of the problem and what to do to remediate it. Non-lag mode means each port is configured for an independent link, such as separate Ethernet links that are not aggregated. KPIs for the LAG, such as frame loss, delay, delay variation, etc., are measured and shown. If thresholds are set, the KPIs can be shown as pass or fail. In order to measure the KPIs, out of sequence errors caused by the test frame scrambling shown in FIG. 5 are suppressed based on the test stream identifiers embedded in the test frames. Also, lost frames can be determined for LAG applications even though the test frames are scrambled,” in Para.[0042], The test streams can be interpreted as the sampling video because it includes test frames and is output normal or not based on the pattern in payload of test frames.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings Wang with the above teachings of Gajjala in order to improve video data capturing technology and more refined video encoding and transmitting.
Carroll teaches wherein the processor is further configured to determine whether an error has occurred in at least one of the input device and the plurality of video processors, based on the at least one pattern, and wherein the at least one pattern corresponds to each of the output order of each of the plurality of frames(“the processor may decompress a logarithmically compressed video image to a linear video image. In some embodiments, the video image may be a Society of Motion Pictures and Television Engineers (SMPTE) standard video image. The plurality of instructions may further cause the processor to modify a video parameter of the video image. The plurality of instructions may also cause the processor to display the video image based on the video parameter on the display device. The video image may be displayed according to a predetermined display format or standard having a predefined pixel width and pixel height. The plurality of instructions may further cause the processor to retrieve an authorization code from a remote computer. The processor may allow access to a function or feature of the video monitoring system based on the authorization code and/or record an amount of time in which the video monitoring system is used based on the authorization code. The plurality of instructions may also cause the processor to transmit the video image to a remote video device such as a video recording device and/or a video display device capable of displaying the video image. In some embodiments, the video image may be transmitted over a network. The plurality of instructions may further cause the processor to retrieve a predefined video parameter value. The processor may modify the video parameter of the video image based on the predefined video parameter value. The plurality of instructions may also cause the processor to determine a color range of a portion of the image and display indicia of the color range on the display device. The plurality of instructions may yet further cause the processor to transmit control data to the video camera based on the video image. The plurality of instructions may also cause the processor to determine an error condition of the video image and provide an alert based on the error condition. The error condition may be determined based on, for example, the compliance of the video image with a predefined display standard. The plurality of instructions may also cause the processor to determine video image data based on the video image and incorporate the video parameter into the video image data” in Para.[0006], The video parameters can be interpreted as at least one pattern.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings Wang and Gajjala with the above teachings of Carroll in order to improve user’s viewing experience.
As per claim 2, Wang, Gajjala and Carroll teach all of limitation of claim 1.
Wang teaches wherein the processor is configured to check an output order of a current frame among the frames, based on a first pattern of the at least one pattern indicating the output order of each of the plurality of frames(“when the output order corresponding to the current frame is not sequential to an output order corresponding to a previous frame, determine that an output order error has occurred” in Para.[0060], “A video frame may include an integer number of CTUs ordered consecutively in a raster scan order from left to right and from top to bottom.” in Para.[0061]).
Wang is silent about when the output order corresponding to the current frame is not sequential to an output order corresponding to a previous frame, determine that an output order error has occurred.
Gajjala teaches when the output order corresponding to the current frame is not sequential to an output order corresponding to a previous frame, determine that an output order error has occurred(“KPIs for the LAG, such as frame loss, delay, delay variation, etc., are measured and shown. If thresholds are set, the KPIs can be shown as pass or fail. In order to measure the KPIs, out of sequence errors caused by the test frame scrambling shown in FIG. 5 are suppressed based on the test stream identifiers embedded in the test frames. Also, lost frames can be determined for LAG applications even though the test frames are scrambled, such as shown in FIG. 5.” In Para.[0042]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings Wang with the above teachings of Gajjala in order to improve video data capturing technology and more refined video encoding and transmitting.
As per claim 3, Wang, Gajjala and Carroll teach all of limitation of claim 2.
Wang is silent about wherein the first pattern comprises a binary pattern.
Gajjala teaches wherein the first pattern comprises a binary pattern (“The payload may include additional data, such as a bit pattern, e.g., pseudorandom binary sequence (PRBS) pattern, to be analyzed for bit error measurements.” In Para.[0036]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings Wang with the above teachings of Gajjala in order to improve video data capturing technology and more refined video encoding and transmitting.
As per claim 6, Wang, Gajjala and Carroll teach all of limitation of claim 1.
Wang teaches wherein each of the plurality of video processors comprises an input module configured to standardize the test video to generate a first sampling video, and the processor is configured to receive the first sampling video from the input module and, when at least one of an output order error of the first sampling video and an abnormal output of the first sampling video occurs, determine that an error occurs in the input device(“after receiving video data, partition unit 45 within prediction processing unit 41 partitions the video data into video blocks. This partitioning may also include partitioning a video frame into slices, tiles, or other larger coding units (CUs) according to a predefined splitting structures such as quad-tree structure associated with the video data. The video frame may be divided into multiple video blocks (or sets of video blocks referred to as tiles). Prediction processing unit 41 may select one of a plurality of possible predictive coding modes, such as one of a plurality of intra predictive coding modes or one of a plurality of inter predictive coding modes, for the current video block based on error results (e.g., coding rate and the level of distortion). Prediction processing unit 41 may provide the resulting intra or inter prediction coded block to summer 50 to generate a residual block and to summer 62 to reconstruct the encoded block for use as part of a reference frame subsequently.” In Para.[0033], The error result can be interpreted as an abnormal output has occurred).
Wang in view of Gajjala, Carroll and Spears
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al.(USPubN 2022/0360799; hereinafter Wang) in view of Gajjala et al.(USPubN 2022/0345392; hereinafter Gajjala) further in view of Carroll(USPubN 2008/0068458) further in view of Spears et al.(USPubN 2014/0267780; hereinafter Spears).
As per claim 4, Wang, Gajjala and Carroll teach all of limitation of claim 1.
Wang, Gajjala and Carroll are silent about wherein the processor is configured to compare a predetermined pixel value with a pixel value of a pixel of a predetermined position among pixels implementing a second pattern representing a plurality of colors and determine whether the sampling video is output normally or not, based on a comparison.
Spears teaches wherein the processor is configured to compare a predetermined pixel value with a pixel value of a pixel of a predetermined position among pixels implementing a second pattern representing a plurality of colors and determine whether the sampling video is output normally or not, based on a comparison(“comparing the values of rendered pixels in the captured frame 86 to values of corresponding test pixels in the test pattern to identify one or more video quality errors in the frame. Values of the test pixels in the test pattern may be accessed, for example, from the XML file 84 that corresponds to the test pattern 54. In one example where the test pattern is generated by the gaming device 18, at 246 the method 200 includes randomly sampling rendered pixels of the generated test pattern.” in Para.[0033]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings Wang, Gajjala and Carroll with the above teachings of Spears in order to improve video quality significantly.
As per claim 5, Wang, Gajjala and Carroll teach all of limitation of claim 1.
Wang, Gajjala and Carroll are silent about wherein the at least one pattern comprises the second pattern, wherein the second pattern included in each of the plurality of frames is the same.
Spears teaches wherein the at least one pattern comprises the second pattern, wherein the second pattern included in each of the plurality of frames is the same (“comparing the values of rendered pixels in the captured frame 86 to values of corresponding test pixels in the test pattern to identify one or more video quality errors in the frame. Values of the test pixels in the test pattern may be accessed, for example, from the XML file 84 that corresponds to the test pattern 54. In one example where the test pattern is generated by the gaming device 18, at 246 the method 200 includes randomly sampling rendered pixels of the generated test pattern.” in Para.[0033], Same pixel value can in each of the plurality of frames.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings Wang, Gajjala and Carroll with the above teachings of Spears in order to improve video quality significantly.
Wang in view of Gajjala, Carroll and Babkin
Claims 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al.(USPubN 2022/0360799; hereinafter Wang) in view of Gajjala et al.(USPubN 2022/0345392; hereinafter Gajjala) further in view of Carroll(USPubN 2008/0068458) further in view of Babkin et al.(USPubN 2021/0351867; hereinafter Babkin).
As per claim 7, Wang, Gajjala and Carroll teach all of limitation of claim 1.
Wang, Gajjala and Carroll are silent about wherein the processor is configured to receive the sampling video from each of the plurality of video processors and determine whether at least one of an output order error and an abnormal output of each of the sampling video from the plurality of video processors, and determine whether an error occurs in a target video processor among the video processors, based on whether an error has occurred in one of the video processors which performs the processing operations on the test video prior to the target video processor outputting a sampling video where at least one of the output order error and the abnormal output has occurred.
Babkin teaches wherein the processor is configured to receive the sampling video from each of the plurality of video processors and determine whether at least one of an output order error and an abnormal output of each of the sampling video from the plurality of video processors, and determine whether an error occurs in a target video processor among the video processors, based on whether an error has occurred in one of the video processors which performs the processing operations on the test video prior to the target video processor outputting a sampling video where at least one of the output order error and the abnormal output has occurred (“systems and methods for detecting errors in video communicated between computing systems. More particularly, the present disclosure is directed to utilizing post-decoding error detection code verification on both encoding and decoding computing systems to properly ensure that transmitted video files are uncorrupted. As an example, an encoding computing system can receive a captured video frame (e.g., a single frame of a captured video file, etc.) and encode the video file according to an encoding scheme. The encoding computing system can then decode the video file and generate a frame error detection code based on the decoded video frame (e.g., using an error detection code generation scheme, etc.). The encoding computing system can send the encoded video frame and the frame error detection code to a decoding computing system (e.g., using a real-time transport protocol packet and associated extension field, etc.). The decoding computing system can decode the encoded video frame according to the encoding scheme to generate an additional frame error detection code. The decoding computing system can then compare the two frame error detection codes to determine if the decoded video frame is corrupted (e.g., based on detected errors, etc.).” in Para.[0017]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings Wang, Gajjala and Carroll with the above teachings of Babkin in order to improve video quality significantly.
As per claim 8, Wang, Gajjala and Carroll teach all of limitation of claim 1.
Wang, Gajjala and Carroll are silent about wherein the processor is configured to receive a final sampling video from a final video processor among the video processors that performs the processing operations last among the plurality of video processors and determine whether an error has occurred in at least one of the input device and the plurality of video processors, based on an output order of each of a plurality of frames of the final sampling video and whether the final sampling video is output normally or not.
Babkin teaches wherein the processor is configured to receive a final sampling video from a final video processor among the video processors that performs the processing operations last among the plurality of video processors and determine whether an error has occurred in at least one of the input device and the plurality of video processors, based on an output order of each of a plurality of frames of the final sampling video and whether the final sampling video is output normally or not (“systems and methods for detecting errors in video communicated between computing systems. More particularly, the present disclosure is directed to utilizing post-decoding error detection code verification on both encoding and decoding computing systems to properly ensure that transmitted video files are uncorrupted. As an example, an encoding computing system can receive a captured video frame (e.g., a single frame of a captured video file, etc.) and encode the video file according to an encoding scheme. The encoding computing system can then decode the video file and generate a frame error detection code based on the decoded video frame (e.g., using an error detection code generation scheme, etc.). The encoding computing system can send the encoded video frame and the frame error detection code to a decoding computing system (e.g., using a real-time transport protocol packet and associated extension field, etc.). The decoding computing system can decode the encoded video frame according to the encoding scheme to generate an additional frame error detection code. The decoding computing system can then compare the two frame error detection codes to determine if the decoded video frame is corrupted (e.g., based on detected errors, etc.).” in Para.[0017]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings Wang, Gajjala and Carroll with the above teachings of Babkin in order to improve video quality significantly.
As per claim 9, Wang, Gajjala, Carroll and Babkin teach all of limitation of claim 8.
Wang, Gajjala and Carroll are silent about wherein the processor is configured to, when an output order error of each of a plurality of frames of the final sampling video does not occur and a normal output of the final sampling video has occurred, determine that no error has occurred in the input device and the plurality of video processors.
Babkin teaches wherein the processor is configured to, when an output order error of each of a plurality of frames of the final sampling video does not occur and a normal output of the final sampling video has occurred, determine that no error has occurred in the input device and the plurality of video processors (“systems and methods for detecting errors in video communicated between computing systems. More particularly, the present disclosure is directed to utilizing post-decoding error detection code verification on both encoding and decoding computing systems to properly ensure that transmitted video files are uncorrupted. As an example, an encoding computing system can receive a captured video frame (e.g., a single frame of a captured video file, etc.) and encode the video file according to an encoding scheme. The encoding computing system can then decode the video file and generate a frame error detection code based on the decoded video frame (e.g., using an error detection code generation scheme, etc.). The encoding computing system can send the encoded video frame and the frame error detection code to a decoding computing system (e.g., using a real-time transport protocol packet and associated extension field, etc.). The decoding computing system can decode the encoded video frame according to the encoding scheme to generate an additional frame error detection code. The decoding computing system can then compare the two frame error detection codes to determine if the decoded video frame is corrupted (e.g., based on detected errors, etc.).” in Para.[0017], “At 502, the method 500 can include determining, based on the error data, that the encoded video frame is corrupted. More particularly, a decoding computing system can determine, based on the error data exceeding one or more error thresholds, that an encoded video frame is a corrupted video frame. The decoding computing system can determine that there are a number and/or severity of error(s) associated with the differences between a first and second video frame such that the encoded video frame is corrupted. As an example, an error threshold may specify that exceeding a certain number of errors indicates that the encoded video frame is corrupted. As another example, the error threshold may specify that exceeding a certain number of pixel differences indicates that the encoded video frame is corrupted. The error threshold can be any arbitrary threshold associated with a severity and/or number of errors in the encoded video frame.” In Para.[0090]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings Wang, Gajjala and Carroll with the above teachings of Babkin in order to improve video quality significantly.
As per claim 10, Wang, Gajjala, Carroll and Babkin teach all of limitation of claim 8.
Wang, Gajjala and Carroll are silent about wherein the processor is configured to, when at least one of an output order error and an abnormal output of the final sampling video has occurred, determine whether an error has occurred in at least one of the input device and the plurality of video processors, based on whether an error has occurred in a video processor among the plurality of video processors which performs the processing operations on the test video prior to the final video processor.
Babkin teaches wherein the processor is configured to, when at least one of an output order error and an abnormal output of the final sampling video has occurred, determine whether an error has occurred in at least one of the input device and the plurality of video processors, based on whether an error has occurred in a video processor among the plurality of video processors which performs the processing operations on the test video prior to the final video processor (“systems and methods for detecting errors in video communicated between computing systems. More particularly, the present disclosure is directed to utilizing post-decoding error detection code verification on both encoding and decoding computing systems to properly ensure that transmitted video files are uncorrupted. As an example, an encoding computing system can receive a captured video frame (e.g., a single frame of a captured video file, etc.) and encode the video file according to an encoding scheme. The encoding computing system can then decode the video file and generate a frame error detection code based on the decoded video frame (e.g., using an error detection code generation scheme, etc.). The encoding computing system can send the encoded video frame and the frame error detection code to a decoding computing system (e.g., using a real-time transport protocol packet and associated extension field, etc.). The decoding computing system can decode the encoded video frame according to the encoding scheme to generate an additional frame error detection code. The decoding computing system can then compare the two frame error detection codes to determine if the decoded video frame is corrupted (e.g., based on detected errors, etc.).” in Para.[0017]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings Wang, Gajjala and Carroll with the above teachings of Babkin in order to improve video quality significantly.
Wang in view of Gajjala and Rusko
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al.(USPubN 2022/0360799; hereinafter Wang) in view of Gajjala et al.(USPubN 2022/0345392; hereinafter Gajjala) further in view of Carroll(USPubN 2008/0068458) further in view of Rusko et al.(USPubN 2023/0306601; hereinafter Rusko).
As per claim 12, Wang, Gajjala and Carroll teach all of limitation of claim 1.
Wang, Gajjala and Carroll are silent about further comprising a display panel configured to display the video, wherein the processor is configured to, when an error occurs in at least one of the input device and the plurality of video processors, control the display panel to display a notification indicating that the error occurs.
Rusko teaches further comprising a display panel configured to display the video, wherein the processor is configured to, when an error occurs in at least one of the input device and the plurality of video processors, control the display panel to display a notification indicating that the error occurs(“the instructions are executable to identify a segmentation error of a selected segmentation of the set of segmentations based on the selected segmentation not passing a rationality check and display a notification indicating the identified segmentation error” in Para.[0135]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings Wang, Gajjala and Carroll with the above teachings of Rusko in order to improve user experience of video consuming.
Allowable Subject Matter
Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 13-20 are allowed.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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