DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable over O’Sullivan et al., US 2019/0355659n (corresponding to US11,380,616).
In re Claim 1, O’Sullivan discloses a semiconductor package comprising: a first redistribution structure 220 including a first insulating layer 223 and first conductive patterns (222, 230); a connection substrate (marked as CS in Fig. A) disposed on the first redistribution structure 220, and including a base layer 210 and a through electrode (213, 214) penetrating the base layer 210 (Fig. 2A), wherein the base layer 210 includes a first material (silicon dioxide, [0033]); a molding layer 215 at least partially surrounding the connection substrate 210 and disposed on the first redistribution structure 220, wherein the molding layer 215 includes a second material (epoxy resin, [0032]); a second redistribution structure ((260, 240, 252, 280) marked as 2RS in Fig. A) disposed on the molding layer 215 and the connection substrate CP (Figs. 2G and A), and including a second insulating layer 280 and second conductive patterns (214, 260); and a plurality of semiconductor devices 250 (Fig. 3C) spaced apart from each other on the second redistribution structure 2RS (Fig. A), wherein a first thermal expansion coefficient of the first material (silicon dioxide) of the base layer 210 is inherently less than a second thermal expansion coefficient of the second material (epoxy resin) of the molding layer 215, and wherein an upper surface of the base layer 210 and an upper surface of the molding layer 215 (Figs. 1-3 and A; [0022 – 0051). It is inherently because the thermal expansion coefficient of silicon dioxide is approximately 5.6 x 10-7 per degree Kelvin (see Silicon Dioxide Properties at B. El-Kareh. Fundamentals of Semiconductor Processing Technologies. Kluwer Academic Publishers, 1995).
While the thermal expansion coefficient of epoxy resin is 62×10.sup.−6/K (see for example, Inoue, US 11,482,982: column 4, lines 62-64).
Let’s note that the references about the thermal expansion coefficients are presented here only as evidence of inherency (See MPEP2131.01.III).
O’Sullivan does not explicitly indicate that an upper surface of the base layer 212 is substantially coplanar with an upper surface of the molding layer 215, while O’Sullivan specifies that 215 may be thinned or fully removed from the non-active side of IC chip 205 ([0034]).
The difference between the Applicant’s Claim 1 and O’Sullivan’s reference is in a ratio of thicknesses of the base layer 212 and the molding layer 215. It is known in the art that a thickness of a layer is a result effective variable – because volume depends on it. Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, it would have been an obvious matter of design choice of one of ordinary skill in the semiconductor art to use the layers 222 and 215 of an equal thickness, so the upper surface of the base layer 212 is substantially coplanar with an upper surface of the molding layer 215, since such a modification would have involved a mere change in the size of a component. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984) (MPEP2144.04.IV.A).
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Fig, A. O’Sullivan’s Fig. 3B annotated to show the details cited
In re Claim 2, O’Sullivan does not explicitly indicate the base layer 212 ([0033]) comprises glass. However, it is well known in the art that the silicon dioxide is a glass.
In re Claim 3, O’Sullivan does not explicitly indicate the base layer 212 ([0033]) comprises ceramic. However, it is well-known in the art that the silicon dioxide is ceramic
In re Claim 4, O’Sullivan discloses the semiconductor package of claim 1, wherein the second insulating layer 280 extends along the upper surface of the base layer 212 and the upper surface of the molding layer 215 (Fig. 3C).
In re Claim 5, O’Sullivan discloses all limitations of Claim 5, including that the base layer 212 comprises glass (see the rejection of Claim 2 above), the molding layer 215 comprises an epoxy molding compound ([0032]), except for that the second insulating layer 280 comprises polyimide. The difference between the Applicant’s Claim 5 and O’Sullivan’s reference is in the specified material of the second insulating layer 280. Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, it would have been an obvious matter of design choice of one of ordinary skill in the semiconductor art to use the second insulating layer 280 comprising polyimide, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416 (See MPEP2144.07).
In re Claim 6, O’Sullivan discloses the semiconductor package of claim 1, wherein the second conductive patterns 260 comprise a conductive via pattern extending in the second insulating layer 280 and contacting an upper surface 214 of the through electrode (213, 214, UP) (Fig. 2G).
In re Claim 7, O’Sullivan discloses the semiconductor package of claim 6, wherein a horizontal width of the conductive via pattern 260 decreases as it approaches the upper surface 214 of the through electrode (213, 214, UP) (Fig. 2G).
In re Claim 8, O’Sullivan discloses the semiconductor package of claim 7, wherein the upper surface (214, UP) (Fig. A) of the through electrode (213, 214) (Fig. 2G) comprises a first (lower) portion 214 and a second (upper) portion UP, wherein the first (lower) portion 214 is in contact with the conductive via pattern 260, and the second (upper) portion UP is in contact with the second insulating layer 280.
In re Claim 9, O’Sullivan discloses all limitations of Claim 9, including that the connection substrate CS is connected to the first redistribution structure 220, except for that it is connected through a first connection bump. It would have been obvious to one of ordinary skill in the art at the time the invention was made to connect through a connection bump since it was known in the art that it is well-known and routine technique. (MPEP2144.I.)
In re Claim 14, O’Sullivan discloses a semiconductor package comprising: a first redistribution structure 220 including a first insulating layer 223 and first conductive patterns 222; a connection substrate CS (Fig. A) disposed on the first redistribution structure 220, and including a base layer 210 and a through electrode (213, 214, UP) configured to penetrate the base layer 210; a molding layer 215 at least partially surrounding the connection substrate CS on the first redistribution structure 220 and including an epoxy mold compound [0032]); a second redistribution structure 2RS disposed on the molding layer 215 and the connection substrate CS, and including a second insulating layer 280 and second conductive patterns (260, UP); and a plurality of semiconductor devices 250 (Fig. 3C) spaced apart from each other on the second redistribution structure 2RS, wherein an upper surface of the base layer 210 is substantially coplanar with an upper surface of the molding layer 215 ([0034]), and wherein the second insulating layer 280 extends along the upper surface of the base layer 210 and the upper surface of the molding layer 215 (Figs. 1-3 and A; [0022 – 0051). O’Sullivan does not explicitly indicate that wherein the base layer 210 made of silicon dioxide ([0033]) comprises glass. It would have been obvious to one of ordinary skill in the art at the time the invention was made to use the silicon dioxide as glass since it was known in the art that it is well-known and routine practice to use the silicon dioxide in a glass form. (MPEP2144.I.)
In re Claim 15, O’Sullivan discloses the semiconductor package of Claim 14, wherein the second conductive patterns comprise a conductive via pattern (213, 214) extending in the second insulating layer 280 and contacting an upper surface 214 of the through electrode (213, 214), and wherein a horizontal width of the conductive via pattern (260, UP) decreases as it approaches the upper surface 214 of the through electrode (213, 214) (Fig. A).
Allowable Subject Matter
Claims 10-13 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reason for indicating allowable subject matter
In re Claim 10: The prior art of record cited by the current office action, alone or in combination, fail to anticipate or render obvious such limitation of claim 10 as: “a bridge circuit pattern configured to electrically connect between each of the plurality of semiconductor devices”, in combination with limitations of Claim 1 on which it depends.
In re Claim 16, The prior art of record cited by the current office action, alone or in combination, fail to anticipate or render obvious such limitation of claim 16 as: “the second conductive patterns further comprise a seed metal pattern provided between the conductive via pattern and the upper surface of the through electrode”, in combination with limitations of Claim 15 on which it depends.
Claims 17-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
In re Claim 17 prior-art fails to disclose a method of isolating gates in a semiconductor package comprising “a bridge chip mounted on the first redistribution structure and spaced apart from the connection substrate in a lateral direction, wherein the bridge chip includes a bridge circuit pattern; second connection bumps disposed between the bridge chip and the first redistribution structure; a plurality of conductive pillars disposed on the bridge chip, and electrically connected to the bridge circuit pattern.” Therefore, the claimed device differs from prior art devices on this point and there is no evidence it would have been obvious to make this change.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NIKOLAY K YUSHIN whose telephone number is (571)270-7885. The examiner can normally be reached Monday-Friday (7-7 PST).
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/NIKOLAY K YUSHIN/Primary Examiner, Art Unit 2893