Prosecution Insights
Last updated: July 17, 2026
Application No. 18/403,965

VOLTAGE SUPERVISOR

Non-Final OA §102§112§Other
Filed
Jan 04, 2024
Priority
Jan 14, 2020 — IN 202041001565 +1 more
Examiner
BEHM, HARRY RAYMOND
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
80%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
87%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allowance Rate
925 granted / 1163 resolved
+11.5% vs TC avg
Moderate +7% lift
Without
With
+7.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
42 currently pending
Career history
1194
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
77.3%
+37.3% vs TC avg
§102
6.2%
-33.8% vs TC avg
§112
0.9%
-39.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1163 resolved cases

Office Action

§102 §112 §Other
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on 6/3/2026 has been entered. Response to Arguments Applicant states in the remarks filed 6/3/26 that in view of the Notice of Allowance, Applicant believes the claims as further amended are still allowable. Examiner does not agree that the claims are in condition for allowance, would have been allowed if submitted earlier or the previous office action indicated the present claims would be allowable. New grounds of rejection have been made below. Claim Rejections - 35 USC § 112 2nd The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 2-4, 6-7 and 22-26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 2 incorrectly recites the seventh transistor is coupled between the fifth transistor and the second resistor, but should recite on lines 4-5, “a seventh transistor coupled between the sixth transistor and the second resistor”. The claim is indefinite when interpreted in light of the specification, because Figure 1 clearly shows the seventh transistor coupled between the sixth transistor and the second resistor, not between the fifth transistor and the second resistor. For the purpose of examination, the claim limitation shall be interpreted as a seventh transistor coupled between the sixth transistor and the second resistor. Similarly for claim 22. Claim 24 incorrectly depends from claim 21, lacks antecedent basis for the claimed second resistor and should depend from claim 22 (as claims 6-7 depend from claim 2). The claim is indefinite because of the incorrect dependency and lack of antecedent basis. For the purpose of examination, the claim shall be construed as depending from claim 22. Claim Rejections - 35 USC § 112 4th The following is a quotation of 35 U.S.C. 112(d): (d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph: Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. Claims 9-10 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to contain a reference to a claim previously set forth. Claim 9 improperly depends from cancelled claim 8, and should depend from claim 7. For the purpose of examination, claim 9 shall be considered as depending from claim 7. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 5 and 21 are rejected under 35 U.S.C. 102a1 as being anticipated by Lahiri (US 2014/0103900). With respect to claim 1, Lahiri discloses a system comprising: a first transistor (Fig. 7 14) coupled between a voltage input (Fig. 7 Vdd) and a terminal (Fig. 7 34), the first transistor configurable to provide a first current (Fig. 7 I2) responsive to a first voltage (Fig. 7 voltage 34) at the terminal; a second transistor (Fig. 7 42) and a resistor (Fig. 7 resistor at VBG) coupled between the voltage input and the terminal, the second transistor configurable to provide a second current (Fig. 7 I3) responsive to a difference (Fig. 8 Vdd – voltage 34) between a second voltage (Fig. 7 Vdd) at the voltage input and the first voltage; a third transistor (Fig. 7 94) coupled between the terminal and a ground terminal (Fig. 7 ground symbol); a fourth transistor (Fig. 7 12) coupled between the voltage input and a monitor output (Fig. 7 node 12-16), the fourth transistor having a control terminal (Fig. 7 gate 12) coupled to control terminals of the first and second transistors; and a fifth transistor (Fig. 7 92) coupled between the monitor output and the ground terminal, the fifth transistor having a control terminal (Fig. 7 base 92) coupled to the control terminal of the third transistor. With respect to claim 5, Lahiri discloses the system of claim 1, wherein the first, second and fourth transistors are of an opposite type (Fig. 7 MOS) from the third and firth transistors (Fig. 7 BJT). With respect to claim 1, Lahiri additionally discloses a system comprising: a first transistor (Fig. 8 12) coupled between a voltage input (Fig. 8 Vdd) and a terminal (Fig. 8 102), the first transistor configurable to provide a first current (Fig. 8 I1) responsive to a first voltage (Fig. 8 voltage 102) at the terminal; a second transistor (Fig. 8 42) and a resistor (Fig. 8 20) coupled between the voltage input and the terminal, the second transistor configurable to provide a second current (Fig. 8 I3) responsive to a difference (Fig. 8 Vdd – voltage 102) between a second voltage (Fig. 8 Vdd) at the voltage input and the first voltage; a third transistor (Fig. 8 104) coupled between the terminal and a ground terminal (Fig. 8 ground symbol); a fourth transistor (Fig. 8 14) coupled between the voltage input and a monitor output (Fig. 8 102), the fourth transistor having a control terminal (Fig. 8 gate 14) coupled to control terminals of the first and second transistors; and a fifth transistor (Fig. 8 106) coupled between the monitor output and the ground terminal, the fifth transistor having a control terminal (Fig. 8 gate 106) coupled to the control terminal of the third transistor. With respect to claim 5, Lahiri discloses the system of claim 1, wherein the first, second and fourth transistors are of an opposite type (Fig. 8 PMOS) from the third and firth transistors (Fig. 8 NMOS). With respect to claim 21, Lahiri discloses an apparatus comprising: a power supply (Fig. 7 90 or Fig. 8 100) having a power output (Fig. 7 VBG or Fig. 8 I0); a voltage monitor circuit having a voltage input (Fig. 7 or 8 Vdd) and a monitor output (Fig. 7 output 12-16 or Fig. 8 output 12-16), the voltage input coupled to the power output, and the voltage monitoring circuit including the circuit as set forth in claim 1 above. Allowable Subject Matter Claims 2 and 22 are rejected as indefinite, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if the indefiniteness type rejections stated above were overcome. The following is a statement of reasons for the indication of allowable subject matter: The prior art does not disclose or suggest, in combination with the limitations of the base claim and any intervening claims, primarily, a reference generator including a diode-connected sixth transistor coupled to the voltage input, a second resistor coupled to the ground terminal, and a seventh transistor coupled between the sixth transistor and the second resistor, a control terminal of the sixth transistor coupled to the control terminals of the first, second, and fourth transistors: an eighth transistor coupled between the first transistor and the terminal, a control terminal of the eighth transistor coupled to a control terminal of the seventh transistor; and a nineth transistor coupled between the fourth transistor and the fifth transistor, a control terminal of the nineth transistor coupled to the control terminal of the eighth transistor. The aforementioned limitations in combination with all remaining limitations of the respective claims are believed to render the aforementioned indicated claim and any dependent claims thereof patentable over the art of record. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HARRY RAYMOND BEHM whose telephone number is (571)272-8929. The examiner can normally be reached M-F: 8-5 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu Tran can be reached at 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HARRY R BEHM/Primary Examiner, Art Unit 2838
Read full office action

Prosecution Timeline

Jan 04, 2024
Application Filed
Jun 03, 2026
Request for Continued Examination
Jun 09, 2026
Response after Non-Final Action
Jun 17, 2026
Non-Final Rejection mailed — §102, §112, §Other (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
80%
Grant Probability
87%
With Interview (+7.2%)
2y 5m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1163 resolved cases by this examiner. Grant probability derived from career allowance rate.

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