DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of invention I in the reply filed on 23 March 2026 is acknowledged. The traversal is on the ground(s) that no serious search and/or examination burden exists. This is not found persuasive because, as cited in the restriction requirement, burden is established in that there is a separate classification of the subject matter and a separate field of search as the device claims do not require queries to the selective removal, the guidelines for establishing burden being set forth in MPEP 808.02.
The requirement is still deemed proper and is therefore made FINAL.
Claims 13-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 23 March 2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 2019/0164985 A1).
Regarding claim 1, Lee discloses a memory device (Fig 14-17), comprising: a vertical stack of layers (SS1, SS2) formed from repeating iterations of a group of layers (L1, L2, L3 & L4), the group of layers comprising: a first dielectric material layer (ILD1), a semiconductor material layer (SL), and a second dielectric material layer, the second dielectric material layer having a conductive line (CL1, which is also the bit line BL) formed in a horizontal plane therein; and the vertical stack of layers having a plurality of interconnection locations (CNT1, as shown in Fig 14, there is contact to the BL in L2 and one to the BL in L4) with a corresponding access depth to a corresponding conductive line at corresponding distances from a reference location of the vertical stack, wherein the corresponding access depth is different for each of the plurality of interconnection locations.
Regarding claim 10, Lee discloses that the memory device is a three-dimensional (3D) dynamic random access memory device (¶26-¶31, a three-dimensional memory device using capacitors as the data storage element is a 3D-DRAM).
Allowable Subject Matter
Claims 18-20 are allowed.
Claims 2-9, 11 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
While Lee discloses the memory device of claim 1, neither Lee nor other prior art discloses the memory device having the claimed 3-layer structure with the horizontal conductive line in the second dielectric material layer with the access devices being electrically coupled to the conductive line at the interconnection locations as required by claim 2, or having the first through third portions as required by claims 11 and 18.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL P SHOOK whose telephone number is (571)270-7890. The examiner can normally be reached 9:00 am - 5:00 pm, Mon-Fri.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WILLIAM KRAIG can be reached at (571)272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL P SHOOK/Primary Examiner, Art Unit 2896
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