Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on May 29, 2026, under 37 CFR 1.312 has been entered. The applicant’s amendment to the claims overcomes all rejections under 35 U.S.C. 112(b) described in the previous Office action, and thus the rejections are withdrawn.
Response to Arguments
Applicant's arguments filed June 22, 2026, have been fully considered but they are not persuasive.
Regarding rejections under 35 U.S.C. 102 and 103, the applicant argues that the art applied in the original rejections, namely, Hosotani et. al., Pub. No. US 2020/0176033, hereafter referred to as Hosotani, Kusai et. al., Pub. No. US 2013/0200450, hereafter referred to as Kusai, and Kiyotoshi et. al., Pub. No. US 2009/0294836, hereafter referred to as Kiyotoshi 2009, were improper and that they do not teach that the surfaces of the semiconductor layers are convex.
In response, the features that the applicant is arguing are not taught by the above references were not originally claimed but were only recited in the specification. While interpretation of the claims may be guided by the specification, limitations may not be imported from the specification (See MPEP 2111.01 II: ““Though understanding the claim language may be aided by explanations contained in the written description, it is important not to import into a claim limitations that are not part of the claim. For example, a particular embodiment appearing in the written description may not be read into a claim when the claim language is broader than the embodiment.” Superguide Corp. v. DirecTV Enterprises, Inc., 358 F.3d 870, 875, 69 USPQ2d 1865, 1868 (Fed. Cir. 2004).”). The applicant’s argument amounts to importing limitations from the specification.
In light of the above argument, the examiner maintains that the original rejections of claims 1 and 5 under 35 U.S.C. 102(a)(2) as being anticipated by Hosotani, claims 2, 16, and 20 under 35 U.S.C. 103 as being unpatentable over Hosotani in view of Kusai, claims 3, 6-10, 12, and 14 under 35 U.S.C. 103 as being unpatentable over Hosotani in view of Kiyotoshi, claims 4, 11, 13, and 15 under 35 U.S.C. 103 as being unpatentable over Hosotani and Kiyotoshi in view of Kusai, and claims 17-19 under 35 U.S.C. 103 as being unpatentable over Hosotani and Kusai in view of Kiyotoshi, were proper. However, in light of the applicant’s amendments, these rejections are rendered moot and have necessitated the new grounds of rejection detailed below.
Claim Objections
Claim 8 is objected to because of the following informalities: in line 28, “a contact surface…” should be “and a contact surface…”. Appropriate correction is required.
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Reproduction of Fig. 2 of Hosotani.
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Fig. 11 of Hosotani, reproduced with annotations added by the examiner.
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Fig. 12 of Hosotani, reproduced above with annotations added by the examiner.
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Fig. 55 of Kiyotoshi 2008, reproduced with annotations added by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-6, 8, 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Hosotani in view of Kiyotoshi et. al., Pub. No. US 2008/0073635, hereafter referred to as Kiyotoshi 2008.
Regarding claim 1, Hosotani teaches “A semiconductor memory device” (Hosotani Fig. 2), “comprising: a plurality of structures” (Hosotani Fig. 11, semiconductor layers 31 and insulating layers 32) “including a plurality of insulation layers” (Hosotani [0118]; Fig. 12, insulating layer 53) “and a plurality of semiconductor layers” (Hosotani [0048]; Fig. 12, semiconductor layers 31) “alternately stacked in a vertical direction” (Hosotani Fig. 12, z axis), “the plurality of structures being spaced apart from one another in a horizontal direction” (Hosotani Fig. 11, y axis), “an interlayer insulation layer between the plurality of structures” (Hosotani [0126]; Fig. 11, memory trench MT, and Fig. 12, insulating layer 55), “a plurality of gate electrodes respectively in a plurality of gate trenches passing through the interlayer insulation layer in the vertical direction, between the plurality of structures” (Hosotani [0101], Figs. 11 and 12, word line pillar 33), “and a plurality of vertical insulation layers respectively on sidewalls of the plurality of gate trenches” (Hosotani [0101]; Fig. 12, insulating layer 34), “wherein: each gate electrode of the plurality of gate electrodes is connected to a corresponding semiconductor layer of the plurality of semiconductor layers by the plurality of vertical insulation layers” (Hosotani Fig. 12; word line pillar 33, semiconductor layers 31, insulating layer 34, charge storage layer 35, insulating layer 36; note that the semiconductor layers are connected to the gate electrode through the insulating layer 34, the charge storage layer 35, and the insulating layer 36), “each gate electrode of the plurality of gate electrodes includes a plurality of first portions overlapping the plurality of insulation layers in the horizontal direction” (Hosotani Fig. 12, portions of the word line pillar 33 next to the insulating layers 53, hereafter referred to as the first portions) “and a plurality of second portions overlapping the plurality of semiconductor layers in the horizontal direction” (Hosotani Fig. 12, portions of the word line pillar 33 next to the semiconductor layers 31, hereafter referred to as the second portions), “and a first width of each first portion of the plurality of first portions in the horizontal direction is greater than a second width of each second portion of the plurality of second portions in the horizontal direction” (Hosotani Fig. 12; each first portion has a greater width than the second portion below it).
Hosotani, however, does not teach “and a contact surface between a sidewall of each of the plurality of gate trenches and a sidewall of a corresponding semiconductor layer of the plurality of semiconductor layers is a convex surface protruding toward a corresponding gate trench of the plurality of gate trenches.”
Kiyotoshi 2008, on the other hand, does teach “and a contact surface between a sidewall of each of the plurality of gate trenches” (Kiyotoshi 2008 [0223]: “The conventional lithography technique and wet etching technique are used to form gaps as templates of gate electrodes by etch back. Then, thermal oxide films/silicon nitride films/silicon oxide films 907 are sequentially formed, and P-doped polysilicon films 908 are filled and processed by CMP, thereby forming MONOS memory cells.”; Fig. 55, p-doped polysilicon films 908) “and a sidewall of a corresponding semiconductor layer of the plurality of semiconductor layers is a convex surface protruding toward a corresponding gate trench of the plurality of gate trenches” (Kiyotoshi 2008 [0223]; Fig. 55, note that the surfaces of the epitaxial silicon films 902 are convex towards the p-doped polysilicon films 908). Kiyotoshi 2008 further teaches that the purpose of the convex shapes of the epitaxial silicon films is to improve the write/erase characteristics of the device (Kiyotoshi 2008 [0219]).
The shapes of the epitaxial silicon films, the silicon oxide films (Kiyotoshi 2008 [0223]; Fig. 55, silicon oxide films 903), and p-doped polysilicon films in Kiyotoshi 2008 can be incorporated into the device of Hosotani by using the same shapes for the semiconductor layers, insulating layers, and gate electrodes, respectively.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have used the shapes of the semiconductor layers, insulating layers, and gate electrodes of Kiyotoshi 2008 in the device of Hosotani because doing so would improve the performance of the resulting memory cell and it would be a simple substitution of one element for another.
Regarding claim 3, the combination of Hosotani and Kiyotoshi 2008 described in the discussion of claim 1 further teaches “The semiconductor memory device as claimed in claim 1, wherein each semiconductor layer of the plurality of semiconductor layers includes a first portion overlapping the plurality of insulation layers in the vertical direction” (Kiyotoshi 2008 [0223]; Fig. 55, note that there is a portion of the epitaxial silicon films 902 that overlaps the silicon oxide films 903) “and a second portion that does not overlap the plurality of insulation layers in the vertical direction” (Kiyotoshi 2008 [0223]; Fig. 55, note that there is a portion of the epitaxial silicon films 902 that does not overlap the silicon oxide films 903).
Regarding claim 4, the combination of Hosotani and Kiyotoshi 2008 as applied to claim 1 above further teaches “The semiconductor memory device as claimed in claim 3, wherein the second portion of each semiconductor layer of the plurality of semiconductor layers has a shape that is rounded at a boundary with the plurality of gate trenches” (Kiyotoshi 2008 [0223]; Fig. 55, note that the surfaces of the epitaxial silicon films 902 that contact the p-doped polysilicon films 908 through the insulating films 907 are rounded).
Regarding claim 5, the combination of Hosotani and Kiyotoshi 2008 described in the discussion of claim 1 further teaches “The semiconductor memory device as claimed in claim 1, wherein the plurality of gate trenches are offset in the horizontal direction” (Hosotani Fig. 11).
Regarding claim 6, the combination of Hosotani and Kiyotoshi 2008 described in the discussion of claim 1 further teaches “The semiconductor memory device as claimed in claim 1, wherein the second width decreases toward an upper surface of each semiconductor layer of the plurality of semiconductor layers from a lower surface of each semiconductor layer of the plurality of semiconductor layers, and then increases” (Kiyotoshi 2008 [0223]; Fig. 55, note that the widths of the portions of the p-doped polysilicon films 908 next to the epitaxial silicon films 902 decrease toward their respective upper surfaces and then increase).
Regarding claim 8, Hosotani teaches “A semiconductor memory device” (Hosotani Fig. 2), “comprising: a first structure” (Hosotani Fig. 11, bottommost semiconductor layer 31 and insulating layer 32) “including a plurality of first insulation layers” (Hosotani [0118]; Fig. 12, insulating layer 53) “and a plurality of first semiconductor layers” (Hosotani [0048]; Fig. 12, semiconductor layers 31), “which are alternately stacked in a vertical direction” (Hosotani Fig. 12); “a second structure” (Hosotani Fig. 11, second from bottom semiconductor layer 31 and insulating layer 32) “including a plurality of second insulation layers” (Hosotani [0118]; Fig. 12, insulating layer 53) “and a plurality of second semiconductor layers” (Hosotani [0048]; Fig. 12, semiconductor layers 31), “which are alternately stacked in the vertical direction” (Hosotani Fig. 12), “the second structure being spaced apart from the first structure in a first horizontal direction” (Hosotani Fig. 11, y axis); “a third structure” (Hosotani Fig. 11, second from top semiconductor layer 31 and insulating layer 32) “including a plurality of third insulation layers” (Hosotani [0118]; Fig. 12, insulating layer 53) “and a plurality of third semiconductor layers” (Hosotani [0048]; Fig. 12, semiconductor layers 31), “which are alternately stacked in the vertical direction” (Hosotani Fig. 12), “the third structure being spaced apart from the second structure in the first horizontal direction” (Hosotani Fig. 11, y axis); “a first interlayer insulation layer between the first structure and the second structure” (Hosotani Fig. 11, bottommost memory trench MT, and Fig. 12, insulating layer 55); “a second interlayer insulation layer between the second structure and the third structure” (Hosotani Fig. 11, middle memory trench MT, and Fig. 12, insulating layer 55); “a plurality of first gate electrodes respectively in a plurality of first gate trenches” (Hosotani Fig. 11, second set of word line pillars from bottom 33) “aligned in a second horizontal direction intersecting with the first horizontal direction” (Hosotani Fig. 11, x axis), “passing through the first interlayer insulation layer in the vertical direction” (Hosotani Fig. 11, z axis, and Fig. 12, word line pillar 33), “and connected to the plurality of first semiconductor layers and the plurality of second semiconductor layers by a plurality of vertical insulation layers on inner sidewalls of the plurality of first gate trenches” (Hosotani Figs. 11 and 12, word line pillar 33, semiconductor layers 31, insulating layer 34, charge storage layer 35, insulating layer 36; note that the word line pillar 33 is connected to the semiconductor layers 31 by the insulating layer 34, the charge storage layer 35, and the insulating layer 36); “and a plurality of second gate electrodes respectively in a plurality of second gate trenches” (Hosotani Fig. 11, middle set of gate electrodes 33) “aligned in the second horizontal direction” (Hosotani Fig. 11, x axis), “passing through the second interlayer insulation layer in the vertical direction” (Hosotani Fig. 11, z axis, and Fig. 12, gate electrode 33), “and connected to the plurality of second semiconductor layers and the plurality of third semiconductor layers by the plurality of vertical insulation layers on inner sidewalls of the plurality of second gate trenches” (Hosotani Figs. 11 and 12, word line pillar 33, semiconductor layers 31, insulating layer 34, charge storage layer 35, insulating layer 36; see note above), and “wherein: a center of each first gate electrode of the plurality of first gate electrodes and a center of each second gate electrode of the plurality of second gate electrodes are offset in the first horizontal direction” (Hosotani Fig. 11)
Hosotani, however, does not teach “a width of each first semiconductor layer of the plurality of first semiconductor layers in the first horizontal direction is greater than a width of each first insulation layer of the plurality of first insulation layers in the first horizontal direction, a contact surface between a sidewall of each first gate trench of the plurality of first gate trenches and a sidewall of a corresponding first semiconductor layer of the plurality of first semiconductor layers is a convex surface protruding toward a corresponding first gate trench of the plurality of first gate trenches.”
Kiyotoshi 2008, on the other hand, does teach “a width of each first semiconductor layer of the plurality of first semiconductor layers in the first horizontal direction” (Kiyotoshi 2008 [0233]; Fig. 55, epitaxial silicon films 902) “is greater than a width of each first insulation layer of the plurality of first insulation layers in the first horizontal direction” (Kiyotoshi 2008 [0233]; Fig. 55, silicon oxide films 903; note that the epitaxial silicon films 902 are wider than the silicon oxide films 903), “a contact surface between a sidewall of each first gate trench of the plurality of first gate trenches and a sidewall of a corresponding first semiconductor layer of the plurality of first semiconductor layers is a convex surface protruding toward a corresponding first gate trench of the plurality of first gate trenches” (Kiyotoshi 2008 [0233]; Fig. 55, note that the surfaces of the epitaxial silicon films 902 are convex and protrude toward the p-doped polysilicon films 908). Kiyotoshi 2008 further teaches that the purpose of the convex shapes of the epitaxial silicon films is to improve the write/erase characteristics of the device (Kiyotoshi 2008 [0219]).
The shapes of the epitaxial silicon films, the silicon oxide films, and p-doped polysilicon films in Kiyotoshi 2008 can be incorporated into the device of Hosotani by using the same shapes for the semiconductor layers, insulating layers, and gate electrodes, respectively.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have used the shapes of the semiconductor layers, insulating layers, and gate electrodes of Kiyotoshi 2008 in the device of Hosotani because doing so would improve the performance of the resulting memory cell and it would be a simple substitution of one element for another.
Regarding claim 12, the combination of Hosotani and Kiyotoshi 2008 described in the discussion of claim 8 further teaches “The semiconductor memory device as claimed in claim 8, wherein each semiconductor layer of the plurality of semiconductor layers includes a first portion overlapping the plurality of insulation layers in the vertical direction” (Kiyotoshi 2008 [0223]; Fig. 55, note that there is a portion of the epitaxial silicon films 902 that overlaps the silicon oxide films 903) “and a second portion that does not overlap the plurality of insulation layers in the vertical direction” (Kiyotoshi 2008 [0223]; Fig. 55, note that there is a portion of the epitaxial silicon films 902 that does not overlap the silicon oxide films 903).
Regarding claim 13, the combination of Hosotani and Kiyotoshi 2008 as applied to claim 8 above further teaches “The semiconductor memory device as claimed in claim 12, wherein the second portion of each first semiconductor layer of the plurality of first semiconductor layers has a shape that is rounded at a boundary with the plurality of first gate trenches” (Kiyotoshi 2008 [0223]; Fig. 55, note that the surfaces of the epitaxial silicon films 902 that contact the p-doped polysilicon films 908 through the insulating films 907 are rounded).
Regarding claim 14, the combination of Hosotani and Kiyotoshi 2008 described in the discussion of claim 8 further teaches “The semiconductor memory device as claimed in claim 8, wherein: each gate electrode of the plurality of gate electrodes includes a plurality of first portions overlapping the plurality of insulation layers in the first horizontal direction” (Hosotani Fig. 12, portions of the conductive layer 33 next to the insulating layers 53, hereafter referred to as the first portions) “and a plurality of second portions overlapping the plurality of semiconductor layers in the first horizontal direction” (Hosotani Fig. 12, portions of the conductive layer 33 next to the semiconductor layers 31, hereafter referred to as the second portions), “and a first width of each first portion of the plurality of first portions in the horizontal direction is greater than a second width of each second portion of the plurality of second portions in the first horizontal direction” (Kiyotoshi 2008 [0223]; Fig. 55, note that the portions of the p-doped polysilicon films 908 next to the silicon oxide films 905 are wider that the portions next to the epitaxial silicon films 902).
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Fig. 4B of Kiyotoshi 2009, reproduced above with annotations added by the examiner.
Claims 7 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Hosotani and Kiyotoshi 2008 in further view of Kiyotoshi 2009.
Regarding claim 7, the combination of Hosotani and Kiyotoshi 2008 described in the discussion of claim 1 teaches “The semiconductor memory device as claimed in claim 1”, but does not teach “wherein each vertical insulation layer of the plurality of vertical insulation layers includes a blocking dielectric layer, a charge storage layer, and a tunneling dielectric layer, that are sequentially arranged on each of outer sidewalls of the plurality of gate electrodes.” Hosotani does, however, disclose a blocking dielectric layer (Hosotani Fig. 12, insulating layer 34; also see [0101]: “The insulating layer 34 functions as a block insulating film of the memory cell transistor MC.”) and both a charge storage layer (Hosotani [0102]; Fig. 12, charge storage layer 35) and a tunnel insulating film (Hosotani [0102]; Fig. 12, insulating layer 36; also see [0100]: “The insulating layer… functions as an etching stopper in forming an insulating layer 36 (tunnel insulating film)…”) disposed only next to the semiconductor layer 31.
Kiyotoshi 2009, on the other hand, does teach “wherein each vertical insulation layer of the plurality of vertical insulation layers includes a blocking dielectric layer” (Kiyotoshi 2009 Fig. 4B, second insulating film 62; also see [0067]: “The second insulating film 62 may function as a block insulating film.”), “a charge storage layer” (Kiyotoshi 2009 [0067]; Fig. 4B, charge storage layer 60), “and a tunneling dielectric layer” (Kiyotoshi 2009 Fig. 4B, first insulating film 61; also see [0067]: “The first insulating film 61 may function as a tunnel insulating film.”), “that are sequentially arranged on each of outer sidewalls of the plurality of gate electrodes” (Kiyotoshi Fig. 4B).
The three-part vertical insulation layer of Kiyotoshi 2009 can be incorporated into the combined apparatus of Hosotani and Kiyotoshi 2008 described in the discussion of claim 1 by extending the existing tunnel insulating film and charge storage layer of the combined apparatus of Hosotani and Kiyotoshi 2008 to also cover the insulating layers as in Kiyotoshi.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to use the three-part vertical insulation layer of Kiyotoshi 2009 in the combined apparatus of Hosotani and Kiyotoshi 2008 described in the discussion of claim 1 because it can also serve the purpose that the insulating layer and (fragmentary) charge storage layer and tunnel insulator of the combined apparatus of Hosotani and Kiyotoshi 2008 described in the discussion of claim 1 serves, and is a simple combination of elements of the two references.
Regarding claim 10, the combination of Hosotani and Kiyotoshi 2008 described in the discussion of claim 8 teaches “The semiconductor memory device as claimed in claim 9”, but does not teach “wherein each vertical insulation layer of the plurality of vertical insulation layers includes a blocking dielectric layer, a charge storage layer, and a tunneling dielectric layer, which are sequentially arranged on each of outer sidewalls of the plurality of first gate electrodes.” Hosotani does, however, disclose a blocking dielectric layer (Hosotani Fig. 12, insulating layer 34; also see [0101]) and both a charge storage layer (Hosotani [0102]; Fig. 12, charge storage layer 35) and a tunnel insulating film (Hosotani [0102]; Fig. 12, insulating layer 36; also see [0100]) disposed only next to the semiconductor layer 31.
Kiyotoshi 2009, on the other hand, does teach “wherein each vertical insulation layer of the plurality of vertical insulation layers includes a blocking dielectric layer” (Kiyotoshi 2009 Fig. 4B, second insulating film 62; also see [0067]), “a charge storage layer” (Kiyotoshi 2009 [0067]; Fig. 4B, charge storage layer 60), “and a tunneling dielectric layer” (Kiyotoshi 2009 Fig. 4B, first insulating film 61; also see [0067]), “that are sequentially arranged on each of outer sidewalls of the plurality of gate electrodes” (Kiyotoshi Fig. 4B).
The three-part vertical insulation layer of Kiyotoshi 2009 can be incorporated into the combined apparatus of Hosotani and Kiyotoshi 2008 described in the discussion of claim 8 by extending the existing tunnel insulating film and charge storage layer of Hosotani to also cover the insulating layers as in Kiyotoshi 2009.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to use the three-part vertical insulation layer of Kiyotoshi 2009 in the combined apparatus of Hosotani and Kiyotoshi 2008 described in the discussion of claim 8 because it can also serve the purpose that the insulating layer and (fragmentary) charge storage layer and tunnel insulator of the combined apparatus of Hosotani and Kiyotoshi 2008 described in the discussion of claim 8 serves, and is a simple combination of elements of the two references.
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Fig. 24 of Kusai, reproduced with annotation added by the examiner.
Claims 15-16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hosotani and Kiyotoshi 2008 in further view of Kusai.
Regarding claim 15, the combined apparatus of Hosotani and Kiyotoshi 2008 as applied to claim 8 above teaches “The semiconductor memory device as claimed in claim 14”, but does not teach “wherein a width of each first portion of the plurality of first portions of each first gate electrode of the plurality of first gate electrodes in the second horizontal direction is equal to a width of each second portion of the plurality of second portions of each first gate electrode of the plurality of first gate electrodes in the second horizontal direction.”
Kusai, on the other hand, does teach “a width of each first portion of the plurality of first portions in a second horizontal direction is equal to a width of each second portion of the plurality of second portions in the second horizontal direction” (Kusai Fig. 24, reproduced above with annotation added by the examiner, gate electrode 18).
The flat profile of the gates in Kusai in the second horizontal direction can be incorporated into the combined apparatus of Hosotani and Kiyotoshi 2008 as applied to claim 8 above as a flat profile of the gate electrodes of the combined apparatus of Hosotani and Kiyotoshi 2008 in the second horizontal direction.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to use the flat gate profile of Kusai in the combined apparatus of Hosotani and Kiyotoshi 2008 as applied to claim 8 above because the flat profile would allow the gates to take up less space than the wedge shape taught by the combination of Hosotani and Kiyotoshi 2008 as applied to claim 8 above, and would be a simple substitution of one gate shape for another.
Regarding claim 16, Hosotani teaches “A semiconductor memory device” (Hosotani Fig. 2), “comprising: a plurality of structures” (Hosotani Fig. 11, semiconductor layers 31 and insulating layers 53) “including a plurality of insulation layers” (Hosotani [0118]; Fig. 12, insulating layer 53) “and a plurality of semiconductor layers” (Hosotani [0048]; Fig. 12, semiconductor layers 31) “alternately stacked in a vertical direction” (Hosotani Fig. 12), “the plurality of structures being spaced apart from one another in a first horizontal direction” (Hosotani Fig. 11, y axis), “an interlayer insulation layer between the plurality of structures” (Hosotani [0126]; Fig. 12, insulating layer 55), “a plurality of gate electrodes respectively in a plurality of gate trenches passing through the interlayer insulation layer in the vertical direction, between the plurality of structures” (Hosotani [0101], Fig. 12, conductive layer 33), “and a plurality of vertical insulation layers respectively on inner sidewalls of the plurality of gate trenches” (Hosotani [0101]; Fig. 12, insulating layer 34), “wherein: each gate electrode of the plurality of gate electrodes is connected to a corresponding semiconductor layer of the plurality of semiconductor layers by the plurality of vertical insulation layers” (Hosotani Figs. 11 and 12, word line pillar 33, semiconductor layers 31, insulating layer 34, charge storage layer 35, insulating layer 36; note that the word line pillar 33 is connected to the semiconductor layers 31 by the insulating layer 34, the charge storage layer 35, and the insulating layer 36), “each gate electrode of the plurality of gate electrodes includes a plurality of first portions overlapping the plurality of insulation layers in the first horizontal direction” (Hosotani Fig. 12, portions of the conductive layer 33 next to the insulating layers 55, hereafter referred to as the first portions) “and a plurality of second portions overlapping the plurality of semiconductor layers in the first horizontal direction” (Hosotani Fig. 12, portions of the conductive layer 33 next to the semiconductor layers 31, hereafter referred to as the second portions), “and a first width of each first portion of the plurality of first portions in the horizontal direction is greater than a second width of each second portion of the plurality of second portions in the first horizontal direction” (Hosotani Fig. 12; each first portion has a greater width than the second portion below it), and “the plurality of gate trenches are arranged in zigzags in a plan view” (Hosotani Fig. 11).
Hosotani, however, does not teach “a width of each first portion of the plurality of first portions in a second horizontal direction is equal to a width of each second portion of the plurality of second portions in the second horizontal direction… and each semiconductor layer of the plurality of semiconductor layers has a shape that is convex toward the plurality of gate trenches at a contact surface with the plurality of gate trenches.”
Kiyotoshi 2008, on the other hand, does teach “each semiconductor layer of the plurality of semiconductor layers has a shape that is convex toward the plurality of gate trenches at a contact surface with the plurality of gate trenches” (Kiyotoshi 2008 [0223]; Fig. 55, note that the surfaces of the epitaxial silicon films 902 are convex towards the p-doped polysilicon films 908). Kiyotoshi 2008 further teaches that the purpose of the convex shapes of the epitaxial silicon films is to improve the write/erase characteristics of the device (Kiyotoshi 2008 [0219]).
The shapes of the epitaxial silicon films, the silicon oxide films (Kiyotoshi 2008 [0223]; Fig. 55, silicon oxide films 903), and p-doped polysilicon films in Kiyotoshi 2008 can be incorporated into the device of Hosotani by using the same shapes for the semiconductor layers, insulating layers, and gate electrodes, respectively.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have used the shapes of the semiconductor layers, insulating layers, and gate electrodes of Kiyotoshi 2008 in the device of Hosotani because doing so would improve the performance of the resulting memory cell and it would be a simple substitution of one element for another.
The combination of Hosotani and Kiyotoshi 2008, however, does not teach “a width of each first portion of the plurality of first portions in a second horizontal direction is equal to a width of each second portion of the plurality of second portions in the second horizontal direction”.
Kusai, on the other hand, does teach “a width of each first portion of the plurality of first portions in a second horizontal direction is equal to a width of each second portion of the plurality of second portions in the second horizontal direction” (Kusai Fig. 24, reproduced above with annotations added by the examiner, gate electrode 18).
The flat profile of the gates in Kusai in the second horizontal direction can be incorporated into the apparatus of Hosotani as a flat profile of the gate electrodes of the apparatus of Hosotani in the second horizontal direction.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to use the flat gate profile of Kusai in the apparatus of Hosotani because the flat profile would allow the gates to take up less space than the wedge shape taught by Hosotani, and would be a simple substitution of one gate shape for another.
Regarding claim 18, the combination of Hosotani, Kiyotoshi 2008, and Kusai described in the discussion of claim 16 further teaches “The semiconductor memory device as claimed in claim 16, wherein each semiconductor layer of the plurality of semiconductor layers includes a first portion overlapping the plurality of insulation layers in the vertical direction” (Kiyotoshi 2008 [0223]; Fig. 55, note that there is a portion of the epitaxial silicon films 902 that overlaps the silicon oxide films 903) “and a second portion that does not overlap the plurality of insulation layers in the vertical direction” (Kiyotoshi 2008 [0223]; Fig. 55, note that there is a portion of the epitaxial silicon films 902 that does not overlap the silicon oxide films 903).
Regarding claim 19, the combination of Hosotani, Kiyotoshi 2008, and Kusai described in the discussion of claim 16 further teaches “The semiconductor memory device as claimed in claim 16, wherein the second width decreases toward an upper surface of each semiconductor layer of the plurality of semiconductor layers from a lower surface of each semiconductor layer of the plurality of semiconductor layers, and then increases” (Kiyotoshi 2008 [0223]; Fig. 55, note that the widths of the portions of the p-doped polysilicon films 908 next to the epitaxial silicon films 902 decrease toward their respective upper surfaces and then increase).
Regarding claim 20, the combination of Hosotani, Kiyotoshi 2008, and Kusai described in the discussion of claim 16 further teaches “wherein a portion, contacting each semiconductor layer of the plurality of semiconductor layers” (Kiyotoshi [0233]; Fig. 55, epitaxial silicon films 902), “of each vertical insulation layer of the plurality of vertical insulation layers has a rounded shape.” (Kiyotoshi [0233]; Fig. 55, note that the portions of the insulating film 907 contacting the epitaxial silicon films 902 has a rounded shape).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Hosotani, Kiyotoshi 2008, and Kusai, in further view of Kiyotoshi 2009.
Regarding claim 17, the combined apparatus of Hosotani, Kiyotoshi 2008, and Kusai described in the discussion of claim 16 teaches “The semiconductor memory device as claimed in claim 16”, but does not teach “wherein each vertical insulation layer of the plurality of vertical insulation layers includes a blocking dielectric layer, a charge storage layer, and a tunneling dielectric layer, which are sequentially arranged on each outer sidewall of the plurality of gate electrodes.” Said apparatus does, however, disclose a blocking dielectric layer (Hosotani Fig. 12, insulating layer 34; also see [0101]) and both a charge storage layer (Hosotani [0102]; Fig. 12, charge storage layer 35) and a tunnel insulating film (Hosotani [0102]; Fig. 12, insulating layer 36; also see [0100]) disposed only next to the semiconductor layer.
Kiyotoshi 2009, on the other hand, does teach “wherein each vertical insulation layer of the plurality of vertical insulation layers includes a blocking dielectric layer” (Kiyotoshi 2009 Fig. 4B, second insulating film 62; also see [0067]), “a charge storage layer” (Kiyotoshi 2009 [0067]; Fig. 4B, charge storage layer 60), “and a tunneling dielectric layer” (Kiyotoshi 2009 Fig. 4B, first insulating film 61; also see [0067]), “that are sequentially arranged on each of outer sidewalls of the plurality of gate electrodes” (Kiyotoshi 2009 Fig. 4B).
The three-part vertical insulation layer of Kiyotoshi 2009 can be incorporated into the combined apparatus of Hosotani, Kiyotoshi 2008, and Kusai described in the discussion of claim 16 by extending the existing tunnel insulating film and charge storage layer of said combined apparatus to also cover the insulating layers as in Kiyotoshi 2009.
It would have been obvious to one of ordinary skill in the art before the effective filing date to use the three-part vertical insulation layer of Kiyotoshi 2009 in the combined apparatus of Hosotani, Kiyotoshi 2008, and Kusai described in the discussion of claim 16 because it can also serve the purpose that the insulating layer and (fragmentary) charge storage layer and tunnel insulator of said combined apparatus serves, and is a simple combination of elements of the three references.
Conclusion
Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/R.E.T./Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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