Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7, 9-10, and 16-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the applicant recites the limitations, “the plurality of gate electrodes connected to the plurality of semiconductor layers” and “a plurality of vertical insulation layers respectively on sidewalls of the plurality of gate trenches”, which appear to be contradictory to one another, as it would not be possible to directly connect the semiconductor layers to the gate electrodes due to the presence of the vertical insulation layer. Furthermore, the specification states that “Herein, the gate electrode 33 being connected to the semiconductor layer 31 may denote that the gate electrode 33 and the semiconductor layer 31 are connected with each other through another element although not directly contacting each other” ([0068]), but fails to specify what this other element may be. As a result, there is uncertainty as to how the semiconductor layers are connected to the gate electrodes, which renders the claim indefinite.
Claims 2-7 are also rejected due to their dependence on claim 1, as they inherit the deficiencies of claim 1 described above.
Regarding claim 9, the applicant recites the limitation, “further comprising a plurality of vertical insulation layers respectively on inner sidewalls of the plurality of first gate trenches”, which appears to contradict the limitations, “a plurality of first gate electrodes… connected to the plurality of first semiconductor layers and the plurality of second semiconductor layers” and “a plurality of second gate electrodes… connected to the plurality of second semiconductor layers and the plurality of third semiconductor layers”, inherited from claim 8 because, as pointed out in the discussion of claim 1, it is not possible to directly connect the semiconductor layers to the gate electrodes due to the presence of the vertical insulation layers. Furthermore, as pointed out in the discussion of claim 1, the specification states that the gate electrodes may be indirectly connected to the semiconductor layers through another element ([0068]), but fails to specify what this element may be, thus rendering the claim indefinite.
Claim 10 is also rejected due to its dependence on claim 9, as it inherits the deficiencies of claim 9 described above.
Regarding claim 16, the applicant recites the limitations, “the plurality of gate electrodes being connected to the plurality of semiconductor layers” and “a plurality of vertical insulation layers respectively on sidewalls of the plurality of gate trenches”, which appear to be contradictory to one another because, as pointed out in the discussion of claim 1, it is not possible to directly connect the semiconductor layers to the gate electrodes due to the presence of the vertical insulation layers. Furthermore, as pointed out in the discussion of claim 1, the specification states that the gate electrodes may be indirectly connected to the semiconductor layers through another element ([0068]), but fails to specify what this element may be, thus rendering the claim indefinite.
Claims 17-20 are also rejected due to their dependence on claim 16, as they inherit the deficiencies of claim 16 described above.
The applicant may overcome these rejections by either
Amending the affected claims to recite an additional element that provides an indirect connection between the gate electrodes and the semiconductor layers, or
Reciting one or more means by which this indirect connection may be made in the specification.
For examination purposes, it will be assumed that a connection between the semiconductor layers and the gate electrodes is present if the semiconductor layers contact the vertical insulation layers disposed around the gate electrodes, possibly via a charge storage layer and an additional insulating layer.
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Reproduction of Fig. 2 of Hosotani.
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Fig. 11 of Hosotani, reproduced with annotations added by the examiner.
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Fig. 12 of Hosotani, reproduced above with annotations added by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 5 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Hosotani et. al., Pub. No. US 2020/0176033, hereafter referred to as Hosotani.
Regarding claim 1, Hosotani teaches all of the limitations of the claim in Figs. 2, 11, and 12, reproduced above with annotations added by the examiner: “A semiconductor memory device” (Fig. 2), “comprising: a plurality of structures” (Fig. 11, semiconductor layers 31 and insulating layers 32) “including a plurality of insulation layers” ([0118]; Fig. 12, insulating layer 53) “and a plurality of semiconductor layers” ([0048]; Fig. 12, semiconductor layers 31) “alternately stacked in a vertical direction” (Fig. 12, z axis), “the plurality of structures being spaced apart from one another in a horizontal direction” (Fig. 11, y axis), “an interlayer insulation layer between the plurality of structures” ([0126]; Fig. 11, memory trench MT, and Fig. 12, insulating layer 55), “a plurality of gate electrodes respectively in a plurality of gate trenches passing through the interlayer insulation layer in the vertical direction, between the plurality of structures” ([0101], Figs. 11 and 12, word line pillar 33), “the plurality of gate electrodes connected to the plurality of semiconductor layers” (Fig. 12; word line pillar 33, semiconductor layers 31, insulating layer 34, charge storage layer 35, insulating layer 36; note that it is assumed for examination purposes that a connection between the word line pillar and the semiconductor layers is present if they both contact a vertical insulation layer), “and a plurality of vertical insulation layers respectively on sidewalls of the plurality of gate trenches” ([0101]; Fig. 12, insulating layer 34), “wherein: each gate electrode of the plurality of gate electrodes includes a plurality of first portions overlapping the plurality of insulation layers in the horizontal direction” (Fig. 12, portions of the word line pillar 33 next to the insulating layers 53, hereafter referred to as the first portions) “and a plurality of second portions overlapping the plurality of semiconductor layers in the horizontal direction” (Fig. 12, portions of the word line pillar 33 next to the semiconductor layers 31, hereafter referred to as the second portions), “and a first width of each first portion of the plurality of first portions in the horizontal direction is greater than a second width of each second portion of the plurality of second portions in the horizontal direction” (Fig. 12; each first portion has a greater width than the second portion below it).
Regarding claim 5, Hosotani further teaches “wherein the plurality of gate trenches are offset in the horizontal direction” (Fig. 11).
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Fig. 4B of Kiyotoshi, reproduced above with annotations added by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
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Fig. 5 of Kusai, reproduced with annotations added by the examiner.
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Fig. 24 of Kusai, reproduced with annotation added by the examiner.
Claims 2, 16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hosotani in view of Kusai et. al., Pub. No. US 2013/0200450, hereafter referred to as Kusai.
Regarding claim 2, Hosotani teaches “The semiconductor memory device as claimed in claim 1”, but does not teach “wherein a contact surface between a sidewall of each of the plurality of gate trenches and a sidewall of a corresponding semiconductor layer of the plurality of semiconductor layers is a curved surface”.
Kusai, on the other hand, does teach “wherein a contact surface between a sidewall of each of the plurality of gate trenches” (Kusai [0102]; Fig. 5, reproduced above with annotations added by the examiner, gate oxide layer 15) “and a sidewall of a corresponding semiconductor layer of the plurality of semiconductor layers” (Kusai [0095]; Fig. 5, semiconductor layers 12-1, 12-2, and 12-3) “is a curved surface” (Kusai Fig. 5).
The curved surfaces of the semiconductor layers of Kusai may be incorporated into the apparatus of Hosotani as curved surfaces on the semiconductor layers of said apparatus that are in contact with the vertical insulating layers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to introduce the curved surfaces taught by Kusai on the semiconductor layers of apparatus of Hosotani because it would increase the contact area with the gate trench and thus reduce contact resistance, and it would be a simple substitution of one semiconductor layer shape for another.
Regarding claim 16, Hosotani teaches “A semiconductor memory device” (Hosotani Fig. 2), “comprising: a plurality of structures” (Hosotani Fig. 11, semiconductor layers 31 and insulating layers 53) “including a plurality of insulation layers” (Hosotani [0118]; Fig. 12, insulating layer 53) “and a plurality of semiconductor layers” (Hosotani [0048]; Fig. 12, semiconductor layers 31) “alternately stacked in a vertical direction” (Hosotani Fig. 12), “the plurality of structures being spaced apart from one another in a first horizontal direction” (Hosotani Fig. 11, y axis), “an interlayer insulation layer between the plurality of structures” (Hosotani [0126]; Fig. 12, insulating layer 55), “a plurality of gate electrodes respectively in a plurality of gate trenches passing through the interlayer insulation layer in the vertical direction, between the plurality of structures” (Hosotani [0101], Fig. 12, conductive layer 33), “the plurality of gate electrodes connected to the plurality of semiconductor layers” (Hosotani Figs. 11 and 12, word line pillar 33, semiconductor layers 31, insulating layer 34, charge storage layer 35, insulating layer 36; note that it is assumed for examination purposes that a connection between the word line pillar and the semiconductor layers is present if the semiconductor layers contact the insulating layer), “a plurality of vertical insulation layers respectively on sidewalls of the plurality of gate trenches” (Hosotani [0101]; Fig. 12, insulating layer 34) , “wherein: each gate electrode of the plurality of gate electrodes includes a plurality of first portions overlapping the plurality of insulation layers in the first horizontal direction” (Hosotani Fig. 12, portions of the conductive layer 33 next to the insulating layers 55, hereafter referred to as the first portions) “and a plurality of second portions overlapping the plurality of semiconductor layers in the first horizontal direction” (Hosotani Fig. 12, portions of the conductive layer 33 next to the semiconductor layers 31, hereafter referred to as the second portions), “and a first width of each first portion of the plurality of first portions in the horizontal direction is greater than a second width of each second portion of the plurality of second portions in the first horizontal direction” (Hosotani Fig. 12; each first portion has a greater width than the second portion below it), and “the plurality of gate trenches are arranged in zigzags in a plan view” (Hosotani Fig. 11), but does not teach “a width of each first portion of the plurality of first portions in a second horizontal direction is equal to a width of each second portion of the plurality of second portions in the second horizontal direction… and each semiconductor layer of the plurality of semiconductor layers has a shape that is rounded at a contact surface with the plurality of gate trenches.”
Kusai, on the other hand, does teach “a width of each first portion of the plurality of first portions in a second horizontal direction is equal to a width of each second portion of the plurality of second portions in the second horizontal direction” (Kusai Fig. 24, reproduced above with annotations added by the examiner, gate electrode 18) “and each semiconductor layer of the plurality of semiconductor layers” (Kusai [0095]; Fig. 5, semiconductor layers 12-1, 12-2, and 12-3) “has a shape that is rounded at a contact surface with the plurality of gate trenches” (Kusai [0102]; Fig. 5, gate oxide layer 15).
The flat profile of the gates in Kusai in the second horizontal direction can be incorporated into the apparatus of Hosotani as a flat profile of the gate electrodes of the apparatus of Hosotani in the second horizontal direction and the rounded edges on the semiconductor layers of Kusai can be incorporated into the combined apparatus of Hosotani and Kiyotoshi as rounded edges on the semiconductor layers of said combined apparatus.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to use the flat gate profile of Kusai in the apparatus of Hosotani because the flat profile would allow the gates to take up less space than the wedge shape taught by Hosotani, and would be a simple substitution of one gate shape for another. Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the application to use the rounded edges of the semiconductor layers of Kusai in the apparatus of Hosotani because it would increase the contact area between the semiconductor layers and the vertical insulation layers and thus decrease the contact resistance, and is a simple substitution of one edge shape for another.
Regarding claim 20, the combined apparatus of Hosotani and Kusai described in the discussion of claim 16 further teaches “wherein a portion, contacting each semiconductor layer of the plurality of semiconductor layers” (Kusai [0095]; Fig. 5, semiconductor layers 12-1, 12-2, and 12-3), “of each vertical insulation layer of the plurality of vertical insulation layers has a rounded shape.” (Kusai [0102]; Fig. 5, gate oxide layer 15).
Claims 3, 6-10, 12, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Hosotani in view of Kiyotoshi et. al., Pub. No. US 2009/0294836, hereafter referred to as Kiyotoshi.
Regarding claim 3, Hosotani teaches “The semiconductor memory device as claimed in claim 1”, but does not teach “wherein each semiconductor layer of the plurality of semiconductor layers includes a first portion overlapping the plurality of insulation layers in the vertical direction and a second portion that does not overlap the plurality of insulation layers in the vertical direction”.
Kiyotoshi, on the other hand, does teach “wherein each semiconductor layer of the plurality of semiconductor layers” (Kiyotoshi Fig. 4B, reproduced above with annotations added by the examiner, semiconductor layers 50) “includes a first portion overlapping the plurality of insulation layers” (Kiyotoshi Fig. 4B, insulating layers 55) “in the vertical direction” (Kiyotoshi Fig. 4B, z axis) “and a second portion that does not overlap the plurality of insulation layers in the vertical direction” (Kiyotoshi Fig. 4B, semiconductor layers 50, insulating layers 55; also see paragraph [0069]: “The faces 55v (the side faces) of the stacked insulating layers 55 perpendicular to the major surface 41 on the second spacing 52 side are provided recessed toward the first spacing 51 side as viewed from the second spacing 52 than are the faces 50v (the side faces) of the stacked semiconductor layers 50 perpendicular to the major surface 41 on the second spacing 52 side.”).
The semiconductor and insulating layers of Kiyotoshi can be implemented as substitutes for the corresponding layers in the apparatus of Hosotani.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to substitute the semiconductor and insulating layers of Kiyotoshi into the apparatus of Hosotani because the shapes of the gate electrodes of said combined apparatus would better accommodate semiconductor layers that are wider than the insulating layers and it would be a simple substitution of one set of semiconductor and insulating layers for another.
Regarding claim 6, Hosotani teaches “The semiconductor memory device as claimed in claim 1”, but does not teach “wherein the second width decreases toward an upper surface of each semiconductor layer of the plurality of semiconductor layers from a lower surface of each semiconductor layer of the plurality of semiconductor layers, and then increases.”
Kiyotoshi, on the other hand, does teach “wherein the second width decreases toward an upper surface of each semiconductor layer of the plurality of semiconductor layers from a lower surface of each semiconductor layer of the plurality of semiconductor layers, and then increases” (Kiyotoshi Fig. 4B, gate electrode 70, second portion).
The shape of the gate electrodes of Kiyotoshi can be implemented as a substitute for that of the gate electrodes in Hosotani.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to substitute the shape of the gate electrodes of Kiyotoshi into the apparatus of Hosotani because the shape disclosed by Kiyotoshi would result in a smaller footprint for the gate, would increase the contact area between the gate and the semiconductor layers, and it would be a simple substitution of one gate shape for another.
Regarding claim 7, Hosotani teaches “The semiconductor memory device as claimed in claim 1”, but does not teach “wherein each vertical insulation layer of the plurality of vertical insulation layers includes a blocking dielectric layer, a charge storage layer, and a tunneling dielectric layer, that are sequentially arranged on each of outer sidewalls of the plurality of gate electrodes.” Hosotani does, however, disclose a blocking dielectric layer (Hosotani Fig. 12, insulating layer 34; also see [0101]: “The insulating layer 34 functions as a block insulating film of the memory cell transistor MC.”) and both a charge storage layer (Hosotani [0102]; Fig. 12, charge storage layer 35) and a tunnel insulating film (Hosotani [0102]; Fig. 12, insulating layer 36; also see [0100]: “The insulating layer… functions as an etching stopper in forming an insulating layer 36 (tunnel insulating film)…”) disposed only next to the semiconductor layer 31.
Kiyotoshi, on the other hand, does teach “wherein each vertical insulation layer of the plurality of vertical insulation layers includes a blocking dielectric layer” (Kiyotoshi Fig. 4B, second insulating film 62; also see [0067]: “The second insulating film 62 may function as a block insulating film.”), “a charge storage layer” (Kiyotoshi [0067]; Fig. 4B, charge storage layer 60), “and a tunneling dielectric layer” (Kiyotoshi Fig. 4B, first insulating film 61; also see [0067]: “The first insulating film 61 may function as a tunnel insulating film.”), “that are sequentially arranged on each of outer sidewalls of the plurality of gate electrodes” (Kiyotoshi Fig. 4B).
The three-part vertical insulation layer of Kiyotoshi can be incorporated into the combined apparatus of Hosotani and Kiyotoshi described in the discussion of claim 1 by extending the existing tunnel insulating film and charge storage layer of Hosotani to also cover the insulating layers as in Kiyotoshi.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to use the three-part vertical insulation layer of Kiyotoshi in the combined apparatus of Hosotani and Kiyotoshi described in the discussion of claim 1 because it can also serve the purpose that the insulating layer and (fragmentary) charge storage layer and tunnel insulator of Hosotani serves, and is a simple combination of elements of the two references.
Regarding claim 8, Hosotani teaches “A semiconductor memory device” (Hosotani Fig. 2), “comprising: a first structure” (Hosotani Fig. 11, bottommost semiconductor layer 31 and insulating layer 32) “including a plurality of first insulation layers” (Hosotani [0118]; Fig. 12, insulating layer 53) “and a plurality of first semiconductor layers” (Hosotani [0048]; Fig. 12, semiconductor layers 31), “which are alternately stacked in a vertical direction” (Hosotani Fig. 12); “a second structure” (Hosotani Fig. 11, second from bottom semiconductor layer 31 and insulating layer 32) “including a plurality of second insulation layers” (Hosotani [0118]; Fig. 12, insulating layer 53) “and a plurality of second semiconductor layers” (Hosotani [0048]; Fig. 12, semiconductor layers 31), “which are alternately stacked in the vertical direction” (Hosotani Fig. 12), “the second structure being spaced apart from the first structure in a first horizontal direction” (Hosotani Fig. 11, y axis); “a third structure” (Hosotani Fig. 11, second from top semiconductor layer 31 and insulating layer 32) “including a plurality of third insulation layers” (Hosotani [0118]; Fig. 12, insulating layer 53) “and a plurality of third semiconductor layers” (Hosotani [0048]; Fig. 12, semiconductor layers 31), “which are alternately stacked in the vertical direction” (Hosotani Fig. 12), “the third structure being spaced apart from the second structure in the first horizontal direction” (Hosotani Fig. 11, y axis); “a first interlayer insulation layer between the first structure and the second structure” (Hosotani Fig. 11, bottommost memory trench MT, and Fig. 12, insulating layer 55); “a second interlayer insulation layer between the second structure and the third structure” (Hosotani Fig. 11, middle memory trench MT, and Fig. 12, insulating layer 55); “a plurality of first gate electrodes respectively in a plurality of first gate trenches” (Hosotani Fig. 11, second set of word line pillars from bottom 33) “aligned in a second horizontal direction intersecting with the first horizontal direction” (Hosotani Fig. 11, x axis), “passing through the first interlayer insulation layer in the vertical direction” (Hosotani Fig. 11, z axis, and Fig. 12, word line pillar 33), “and connected to the plurality of first semiconductor layers and the plurality of second semiconductor layers” (Hosotani Figs. 11 and 12, word line pillar 33, semiconductor layers 31, insulating layer 34, charge storage layer 35, insulating layer 36; note that it is assumed that a connection between the word line pillar and the semiconductor layers is present if the semiconductor layers contact the vertical insulating layer); “and a plurality of second gate electrodes respectively in a plurality of second gate trenches” (Hosotani Fig. 11, middle set of gate electrodes 33) “aligned in the second horizontal direction” (Hosotani Fig. 11, x axis), “passing through the second interlayer insulation layer in the vertical direction” (Hosotani Fig. 11, z axis, and Fig. 12, gate electrode 33), “and connected to the plurality of second semiconductor layers and the plurality of third semiconductor layers” (Hosotani Figs. 11 and 12, word line pillar 33, semiconductor layers 31, insulating layer 34, charge storage layer 35, insulating layer 36; see note above), and “wherein: a center of each first gate electrode of the plurality of first gate electrodes and a center of each second gate electrode of the plurality of second gate electrodes are offset in the first horizontal direction” (Hosotani Fig. 11), but does not teach “a width of each first semiconductor layer of the plurality of first semiconductor layers in the first horizontal direction is greater than a width of each first insulation layer of the plurality of first insulation layers in the first horizontal direction.”
Kiyotoshi, on the other hand, does teach “a width of each first semiconductor layer of the plurality of first semiconductor layers in the first horizontal direction” (Kiyotoshi [0028]; Fig. 4B, semiconductor layers 50) “is greater than a width of each first insulation layer of the plurality of first insulation layers in the first horizontal direction” (Kiyotoshi Fig. 4B, insulating layers 55; also see paragraph [0069]).
The semiconductor and insulating layers of Kiyotoshi can be implemented as substitutes for the corresponding layers in Hosotani.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to substitute the semiconductor and insulating layers of Kiyotoshi for the corresponding layers of Hosotani because the semiconductor and insulating layers of Kiyotoshi can serve the same purpose as those of Hosotani and it would be a simple substitution of one element for another.
Regarding claim 9, the combined apparatus of Hosotani and Kiyotoshi described in the discussion of claim 8 further teaches “further comprising a plurality of vertical insulation layers respectively on inner sidewalls of the plurality of first gate trenches” (Hosotani [0101]; Fig. 12, insulating layer 34).
Regarding claim 10, the combined apparatus of Hosotani and Kiyotoshi described in the discussion of claim 8 teaches “The semiconductor memory device as claimed in claim 9”, but does not teach “wherein each vertical insulation layer of the plurality of vertical insulation layers includes a blocking dielectric layer, a charge storage layer, and a tunneling dielectric layer, which are sequentially arranged on each of outer sidewalls of the plurality of first gate electrodes.” Hosotani does, however, disclose a blocking dielectric layer (Hosotani Fig. 12, insulating layer 34; also see [0101]) and both a charge storage layer (Hosotani [0102]; Fig. 12, charge storage layer 35) and a tunnel insulating film (Hosotani [0102]; Fig. 12, insulating layer 36; also see [0100]) disposed only next to the semiconductor layer 31.
Kiyotoshi, on the other hand, does teach “wherein each vertical insulation layer of the plurality of vertical insulation layers includes a blocking dielectric layer” (Kiyotoshi Fig. 4B, second insulating film 62; also see [0067]), “a charge storage layer” (Kiyotoshi [0067]; Fig. 4B, charge storage layer 60), “and a tunneling dielectric layer” (Kiyotoshi Fig. 4B, first insulating film 61; also see [0067]), “that are sequentially arranged on each of outer sidewalls of the plurality of gate electrodes” (Kiyotoshi Fig. 4B).
The three-part vertical insulation layer of Kiyotoshi can be incorporated into the combined apparatus of Hosotani and Kiyotoshi described in the discussion of claim 8 by extending the existing tunnel insulating film and charge storage layer of Hosotani to also cover the insulating layers as in Kiyotoshi.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to use the three-part vertical insulation layer of Kiyotoshi in the combined apparatus of Hosotani and Kiyotoshi described in the discussion of claim 8 because it can also serve the purpose that the insulating layer and (fragmentary) charge storage layer and tunnel insulator of Hosotani serves, and is a simple combination of elements of the two references.
Regarding claim 12, the combined apparatus of Hosotani and Kiyotoshi described in the discussion of claim 8 teaches “The semiconductor memory device as claimed in claim 8”, but does not teach “wherein each first semiconductor layer of the plurality of first semiconductor layers includes a first portion overlapping the plurality of first insulation layers in the vertical direction and a second portion that does not overlap the plurality of first insulation layers in the vertical direction.”
Kiyotoshi, on the other hand, does teach “wherein each first semiconductor layer of the plurality of first semiconductor layers includes a first portion overlapping the plurality of insulation layers in the vertical direction” (Kiyotoshi Fig. 4B, semiconductor layers 50, insulating layers 55) “and a second portion that does not overlap the plurality of insulation layers in the vertical direction” (Kiyotoshi Fig. 4B, semiconductor layers 50, insulating layers 55; also see paragraph [0069]).
The arrangement of the semiconductor and insulating layers of Kiyotoshi can be implemented as the arrangement of the corresponding layers in the combined apparatus of Hosotani and Kiyotoshi described in the discussion of claim 8.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to substitute the arrangement of the semiconductor and insulating layers of Kiyotoshi for that of the corresponding layers of the combination of Hosotani and Kiyotoshi described in the discussion of claim 8 because the arrangement disclosed in Kiyotoshi would result in a smaller footprint of the semiconductor and insulating layers and it would be a simple combination of elements of the two disclosures.
Regarding claim 14, the combined apparatus of Hosotani and Kiyotoshi described in the discussion of claim 8 further teaches “wherein: each gate electrode of the plurality of gate electrodes includes a plurality of first portions overlapping the plurality of insulation layers in the first horizontal direction” (Hosotani Fig. 12, portions of the conductive layer 33 next to the insulating layers 53, hereafter referred to as the first portions) “and a plurality of second portions overlapping the plurality of semiconductor layers in the first horizontal direction” (Hosotani Fig. 12, portions of the conductive layer 33 next to the semiconductor layers 31, hereafter referred to as the second portions), “and a first width of each first portion of the plurality of first portions in the horizontal direction is greater than a second width of each second portion of the plurality of second portions in the first horizontal direction” (Hosotani Fig. 12; each first portion has a greater width than the second portion below it).
Claims 4, 11, 13, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Hosotani and Kiyotoshi as applied to claims 3, 6-10, 12, and 14 above, and further in view of Kusai.
Regarding claim 4, the combined apparatus of Hosotani and Kiyotoshi described in the discussion of claim 3 teaches “The semiconductor memory device as claimed in claim 3”, but does not teach “wherein the second portion of each semiconductor layer of the plurality of semiconductor layers has a shape that is rounded at a boundary with the plurality of gate trenches.”
Kusai, on the other hand, teaches a plurality of semiconductor layers (Kusai [0095]; Fig. 5, semiconductor layers 12-1, 12-2, and 12-3) with surfaces that are rounded at the boundaries of the plurality of gate trenches (Kusai [0102]; Fig. 5, gate oxide layer 15).
The curved surfaces of the semiconductor layers of Kusai may be incorporated into the combined apparatus of Hosotani and Kiyotoshi described in the discussion of claim 3 as curved surfaces on the second portions of the semiconductor layers of said apparatus that are in contact with the vertical insulating layers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to introduce the curved surfaces taught by Kusai on the semiconductor layers of the combined apparatus of Hosotani and Kiyotoshi described in the discussion of claim 3 because it would increase the contact area with the gate trench and thus reduce contact resistance, and it would be a simple substitution of one semiconductor layer shape for another. The combined apparatus now teaches “wherein the second portion of each semiconductor layer of the plurality of semiconductor layers has a shape that is rounded at a boundary with the plurality of gate trenches.”
Regarding claim 11, the combined apparatus of Hosotani and Kiyotoshi described in the discussion of claim 8 teaches “The semiconductor memory device as claimed in claim 8”, but does not teach “wherein a contact surface between a sidewall of each first gate trench of the plurality of first gate trenches and a sidewall of a corresponding first semiconductor layer of the plurality of first semiconductor layers is a curved surface.”
Kusai, on the other hand, does teach “wherein a contact surface between a sidewall of each of the plurality of gate trenches” (Kusai [0102]; Fig. 5, gate oxide layer 15) “and a sidewall of a corresponding semiconductor layer of the plurality of semiconductor layers” (Kusai [0095]; Fig. 5, semiconductor layers 12-1, 12-2, and 12-3) “is a curved surface” (Kusai Fig. 5).
The curved surfaces of the semiconductor layers of Kusai may be incorporated into the combined apparatus of Hosotani and Kiyotoshi described in the discussion of claim 8 as curved surfaces on the semiconductor layers of said apparatus that are in contact with the vertical insulating layers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to introduce the curved surfaces taught by Kusai on the semiconductor layers of the combined apparatus of Hosotani and Kiyotoshi described in the discussion of claim 8 because it would increase the contact area with the gate trench and thus reduce contact resistance, and it would be a simple substitution of one semiconductor layer shape for another.
Regarding claim 13, the combined apparatus of Hosotani and Kiyotoshi described in the discussion of claim 12 teaches “The semiconductor memory device as claimed in claim 12”, but does not teach “wherein the second portion of each first semiconductor layer of the plurality of first semiconductor layers has a shape that is rounded at a boundary with the plurality of first gate trenches.”
Kusai, on the other hand, teaches a plurality of semiconductor layers (Kusai [0095]; Fig. 5, semiconductor layers 12-1, 12-2, and 12-3) with surfaces that are rounded at the boundaries of the plurality of gate trenches (Kusai [0102]; Fig. 5, gate oxide layer 15).
The curved surfaces of the semiconductor layers of Kusai may be incorporated into the combined apparatus of Hosotani and Kiyotoshi described in the discussion of claim 12 as curved surfaces on the second portions of the semiconductor layers of said apparatus that are in contact with the vertical insulating layers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to introduce the curved surfaces taught by Kusai on the semiconductor layers of the combined apparatus of Hosotani and Kiyotoshi described in the discussion of claim 12 because it would increase the contact area with the gate trench and thus reduce contact resistance, and it would be a simple substitution of one semiconductor layer shape for another. The combined apparatus now teaches “wherein the second portion of each semiconductor layer of the plurality of semiconductor layers has a shape that is rounded at a boundary with the plurality of gate trenches.”
Regarding claim 15, the combined apparatus of Hosotani and Kiyotoshi described in the discussion of claim 14 teaches “The semiconductor memory device as claimed in claim 14”, but does not teach “wherein a width of each first portion of the plurality of first portions of each first gate electrode of the plurality of first gate electrodes in the second horizontal direction is equal to a width of each second portion of the plurality of second portions of each first gate electrode of the plurality of first gate electrodes in the second horizontal direction.”
Kusai, on the other hand, does teach “a width of each first portion of the plurality of first portions in a second horizontal direction is equal to a width of each second portion of the plurality of second portions in the second horizontal direction” (Kusai Fig. 24, reproduced above with annotation added by the examiner, gate electrode 18).
The flat profile of the gates in Kusai in the second horizontal direction can be incorporated into the combined apparatus of Hosotani and Kiyotoshi described in the discussion of claim 14 as a flat profile of the gate electrodes of the combined apparatus of Hosotani and Kiyotoshi in the second horizontal direction.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to use the flat gate profile of Kusai in the combined apparatus of Hosotani and Kiyotoshi described in the discussion of claim 14 because the flat profile would allow the gates to take up less space than the wedge shape taught by Hosotani, and would be a simple substitution of one gate shape for another.
Claims 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Hosotani and Kusai as applied to claims 2 and 16 above, and further in view of Kiyotoshi.
Regarding claim 17, the combined apparatus of Hosotani and Kusai described in the discussion of claim 16 teaches “The semiconductor memory device as claimed in claim 16”, but does not teach “wherein each vertical insulation layer of the plurality of vertical insulation layers includes a blocking dielectric layer, a charge storage layer, and a tunneling dielectric layer, which are sequentially arranged on each outer sidewall of the plurality of gate electrodes.” Said apparatus does, however, disclose a blocking dielectric layer (Hosotani Fig. 12, insulating layer 34; also see [0101]) and both a charge storage layer (Hosotani [0102]; Fig. 12, charge storage layer 35) and a tunnel insulating film (Hosotani [0102]; Fig. 12, insulating layer 36; also see [0100]) disposed only next to the semiconductor layer.
Kiyotoshi, on the other hand, does teach “wherein each vertical insulation layer of the plurality of vertical insulation layers includes a blocking dielectric layer” (Kiyotoshi Fig. 4B, second insulating film 62; also see [0067]), “a charge storage layer” (Kiyotoshi [0067]; Fig. 4B, charge storage layer 60), “and a tunneling dielectric layer” (Kiyotoshi Fig. 4B, first insulating film 61; also see [0067]), “that are sequentially arranged on each of outer sidewalls of the plurality of gate electrodes” (Kiyotoshi Fig. 4B).
The three-part vertical insulation layer of Kiyotoshi can be incorporated into the combined apparatus of Hosotani, Kiyotoshi, and Kusai described in the discussion of claim 16 by extending the existing tunnel insulating film and charge storage layer of said combined apparatus to also cover the insulating layers as in Kiyotoshi.
It would have been obvious to one of ordinary skill in the art before the effective filing date to use the three-part vertical insulation layer of Kiyotoshi in the combined apparatus of Hosotani, Kiyotoshi, and Kusai described in the discussion of claim 16 because it can also serve the purpose that the insulating layer and (fragmentary) charge storage layer and tunnel insulator of said combined apparatus serves, and is a simple combination of elements of the three references.
Regarding claim 18, the combined apparatus of Hosotani and Kusai described in the discussion of claim 16 teaches “The semiconductor memory device as claimed in claim 16”, but does not teach “wherein each semiconductor layer of the plurality of semiconductor layers includes a first portion overlapping the plurality of insulation layers in the vertical direction and a second portion that does not overlap the plurality of insulation layers in the vertical direction.”
Kiyotoshi, on the other hand, does teach “wherein each semiconductor layer of the plurality of semiconductor layers includes a first portion overlapping the plurality of insulation layers in the vertical direction” (Kiyotoshi Fig. 4B, semiconductor layers 50, insulating layers 55) “and a second portion that does not overlap the plurality of insulation layers in the vertical direction” (Kiyotoshi Fig. 4B, semiconductor layers 50, insulating layers 55; also see paragraph [0069]).
The semiconductor and insulating layers of Kiyotoshi can be implemented as extensions of the semiconductor layers of the combined apparatus of Hosotani, Kiyotoshi, and Kusai described in the discussion of claim 16.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to substitute the semiconductor and insulating layers of Kiyotoshi into the combined apparatus of Hosotani, Kiyotoshi, and Kusai described in the discussion of claim 16 because the shapes of the gate electrodes of said combined apparatus would better accommodate semiconductor layers that are wider than the insulating layers and it would be a simple substitution of one set of semiconductor and insulating layers for another.
Regarding claim 19, the combined apparatus of Hosotani and Kusai described in the discussion of claim 16 teaches “The semiconductor memory device as claimed in claim 16”, but does not teach “wherein the second width decreases toward an upper surface of each semiconductor layer of the plurality of semiconductor layers from a lower surface of each semiconductor layer of the plurality of semiconductor layers, and then increases.”
Kiyotoshi, on the other hand, does teach “wherein the second width decreases toward an upper surface of each semiconductor layer of the plurality of semiconductor layers from a lower surface of each semiconductor layer of the plurality of semiconductor layers, and then increases” (Kiyotoshi Fig. 4B, gate electrode 70, second portion).
The shape of the gate electrodes of Kiyotoshi can be implemented as a substitute for that of the gate electrodes in the combined apparatus of Hosotani and Kusai described in the discussion of claim 16.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to substitute the shape of the gate electrodes of Kiyotoshi into the combined apparatus of Hosotani and Kusai described in the discussion of claim 16 because the shape disclosed by Kiyotoshi would result in a greater contact area between the gate and the semiconductor layers, thus reducing contact resistance, and it would be a simple substitution of one gate shape for another.
Conclusion
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/R.E.T./ Examiner, Art Unit 2818
/STEVEN H LOKE/ Supervisory Patent Examiner, Art Unit 2818