DETAILED ACTION
This Office Action is in response to the application filed on 04 January 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 10-11, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tomimatsu (US 2019/0088672 A1; hereinafter Tomimatsu).
In regards to claim 1, Tomimatsu teaches a semiconductor device (Title) comprising:
a substrate (20) [0052] including a connection region (AR2) [0052];
a stacked structure ([0022]: multi-layer wiring structure) including conductive patterns (21-38) stacked on the substrate;
an inner supporter (CC/HR/SP) that extends into the stacked structure in the connection region (fig. 6) [0059];
a contact plug (fig. 6: (HU)) [0047] that extends into the stacked structure and is electrically connected to one of the conductive patterns (26) [0059], wherein the contact plug at least partially extends around the inner supporter in plan view (fig 39: conductive features (CC) have portions of SP and HR between respective elements (CC));
an insulating spacer (SP) [0059] between the contact plug (HU) and the stacked structure, wherein the insulating spacer at least partially extends around the contact plug in the plan view (fig. 24); and
outer supporters (figs. 6 and 24: instances of (HR) outside of integral (HU/HR/SP) and (CC/HR/SP) structures) in the connection region, wherein the outer supporters are spaced apart from the contact plug and extend into the stacked structure (figs. 6 and 24).
In regards to claim 2, Tomimatsu teaches the limitations discussed above in addressing claim 1. Tomimatsu further teaches the limitations wherein the inner supporter (SP) includes a first insulating pillar [0059] and the outer supporters (HR) include respective second insulating pillars [0047].
In regards to claim 3, Tomimatsu teaches the limitations discussed above in addressing claim 1. Tomimatsu further teaches the limitations wherein the inner supporter (fig. 6: (CC/HR/SP)) includes a through conductive plug (figs. 6 and 46: e.g. (CC) touching down onto e.g. (26)) that extends into the stacked structure, and a through insulating spacer (SP) that at least partially extends around the through conductive plug in the plan view (fig. 24).
In regards to claim 4, Tomimatsu teaches the limitations discussed above in addressing claim 1. Tomimatsu further teaches the limitations wherein the contact plug (CC) and the insulating spacer (SP) are in contact with an upper surface of one of the conductive patterns (26) [0059].
In regards to claim 5, Tomimatsu teaches the limitations discussed above in addressing claim 1. Tomimatsu further teaches the limitations wherein the contact plug is between the inner supporter and an adjacent one of the outer supporters (fig. 25).
In regards to claim 10, Tomimatsu teaches the limitations discussed above in addressing claim 1. Tomimatsu further teaches the limitations wherein the substrate further comprises a cell array region (AR1) [0043], the semiconductor device further comprising:
vertical channels (fig. 6: channels in which (MH) are disposed) [0046] that penetrate the stacked structure ([0022]: multi-layer wiring structure) on the cell array region,
wherein upper surfaces of the vertical channels are at different distances from the substrate than upper surfaces of the inner supporter and the outer supporters (fig. 6: the tops of (MH) are at different heights above the substate surface compared to (HR)).
In regards to claim 11, Tomimatsu teaches the limitations discussed above in addressing claim 1. Tomimatsu further teaches the limitations wherein the stacked structure ([0022]: multi-layer wiring structure) at least partially extends around the inner supporter (fig. 25: (HR) integral to (CC/HR/SP)) and the outer supporters (HR) in the plan view (fig. 24).
In regards to claim 20, Tomimatsu teaches an electronic system comprising:
a semiconductor device (Title) including a substrate (20) [0052] comprising a connection region (AR2) [0052];
a stacked structure ([0022]: multi-layer wiring structure) including conductive patterns (21-38) stacked on the substrate;
an inner supporter (CC/HR/SP) that extends into the stacked structure in the connection region (fig. 6) [0059];
a contact plug (fig. 6: (HU)) [0047] that extends into a portion of the stacked structure and is electrically connected to one of the conductive patterns (38) [0058], wherein the contact plug at least partially extends around the inner supporter in plan view (fig. 24);
an insulating spacer (SP) [0059] between the contact plug and the stacked structure, wherein the insulating spacer at least partially extends around the contact plug in the plan view (fig. 24);
outer supporters (figs. 6 and 24: instances of (HR) outside of integral (HU/HR/SP) and (CC/HR/SP)) that extend into the stacked structure and are spaced apart from the contact plug (figs. 6 and 24);
an input/output pad electrically connected to peripheral circuits ([0034]: implicit in the transmitting and receiving of input/output signals); and
a controller electrically (2) [0034] connected to the semiconductor device through the input/output pad and configured to control the semiconductor device [0034].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tomimatsu as applied to claim 1 above.
In regards to claim 6, Tomimatsu teaches the limitations discussed above in addressing claim 1. Tomimatsu appears to be silent as to, but does not preclude, the limitations wherein a distance between the inner supporter and an adjacent one of the outer supporters is less than a maximum diameter of the contact plug. Tomimatsu teaches the limitations of having multiple arrangements and dimensions for inner/outer supports and contact plugs (figs. 6 and 23-25). Absent persuasive evidence, it would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to find that the configuration of an element is a matter of choice. In re Dailey, 357 F. 2d 669, 149 USPQ 47 (CCPA 1966).
In regards to claim 7, Tomimatsu teaches the limitations discussed above in addressing claim 1. Tomimatsu appears to be silent as to, but does not preclude, the limitations wherein a width of the inner supporter is greater than respective widths of the outer supporters. Tomimatsu teaches the limitations of having multiple arrangements and dimensions for inner/outer supports and contact plugs (figs. 6 and 23-25). Absent persuasive evidence, it would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to find that the configuration of an element is a matter of choice. In re Dailey, 357 F. 2d 669, 149 USPQ 47 (CCPA 1966).
In regards to claim 8, Tomimatsu teaches the limitations discussed above in addressing claim 1. Tomimatsu appears to be silent as to, but does not preclude, the limitations wherein a lower portion of the inner supporter has a width that is less than a width of an upper portion of the inner supporter. Tomimatsu teaches the limitations of having multiple arrangements and dimensions for inner/outer supports and contact plugs (figs. 6 and 23-25). Absent persuasive evidence, it would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to find that the configuration of an element is a matter of choice. In re Dailey, 357 F. 2d 669, 149 USPQ 47 (CCPA 1966).
In regards to claim 9, Tomimatsu teaches the limitations discussed above in addressing claim 1. Tomimatsu appears to be silent as to, but does not preclude, the limitations wherein the contact plug has a first thickness between a sidewall of the insulating spacer and a sidewall of the inner supporter, and wherein the first thickness is less than a diameter of the inner supporter. Tomimatsu teaches the limitations of having multiple arrangements and dimensions for inner/outer supports and contact plugs (figs. 6 and 23-25). Absent persuasive evidence, it would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to find that the configuration of an element is a matter of choice. In re Dailey, 357 F. 2d 669, 149 USPQ 47 (CCPA 1966).
Claim(s) 12-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tomimatsu.
In regards to claim 12, Tomimatsu teaches a semiconductor device comprising:
a substrate (20) [0052] including a cell array region (AR1) [0052] and a connection region (AR2) [0052];
a stacked structure ([0022]: multi-layer wiring structure) including conductive patterns (21-38) stacked on the substrate;
vertical channels (MH) [0046] that extend into the stacked structure on the cell array region;
a first contact plug (e.g. (HU)) [0047] that extends into the stacked structure on the connection region and is electrically connected to a first one of the conductive patterns (38) [0058];
a second contact plug (e.g. (CC)) that extends into the stacked structure on the connection region and is electrically connected to a second one of the conductive patterns (26) [0059];
a second inner supporter (fig. 25: (HR)) that extends into the second contact plug (figs. 6 and 35: an instance of a contact plug structure can have (HR) integral to (CC/HR/SP));
a first insulating spacer (SP) [0059] between the first contact plug (HU) and the stacked structure, wherein the first insulating spacer at least partially extends around the first contact plug in plan view (fig. 24);
a second insulating spacer (SP) [0059] between the second contact plug (CC) and the stacked structure, wherein the second insulating spacer at least partially extends around the second contact plug in the plan view (fig. 24); and
a plurality of outer supporters (figs. 6 and 24: instances of (HR) outside of integral (HU/HR/SP) and (CC/HR/SP)) that extend into the stacked structure and are spaced apart from the first and second contact plugs on the connection region (figs. 6 and 24).
Tomimatsu teaches in a separate embodiment, the limitations of a first inner supporter (figs. 6 and 25: (HR)) that extends into the first contact plug (figs. 6 and 35: an instance of a contact plug structure can have (HR) integral to (HU/HR/SP) similar to (CC/HR/SP)). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to combine the embodiments taught by Tomimatsu to teach the aforementioned limitation.
In regards to claim 13, Tomimatsu teaches the limitations discussed above in addressing claim 12. Tomimatsu further teaches the limitations wherein upper surfaces of the first (HU) and second contact (CC) plugs are substantially a same distance from the substrate (fig. 6).
In regards to claim 14, Tomimatsu teaches the limitations discussed above in addressing claim 12. Tomimatsu further teaches the limitations wherein upper surfaces of the first and second contact plugs and upper surfaces of the first and second inner supporters are substantially a same distance from the substrate (fig. 6).
In regards to claim 15, Tomimatsu teaches the limitations discussed above in addressing claim 12. Tomimatsu further teaches the limitations wherein the first and second inner supporters have substantially a same length in a direction perpendicular to an upper surface of the substrate (fig. 25: each of the integral supporters(HR) have a length that reaches from the top of a stack down to (22)).
In regards to claim 16, Tomimatsu teaches the limitations discussed above in addressing claim 12. Tomimatsu further teaches the limitations wherein each of the first and second inner supporters includes a through conductive plug (e.g. (HU) or (CC)) that extends into the stacked structure ([0022]: multi-layer wiring structure) and a through insulating spacer (SP) [0059] that at least partially extends around the through conductive plug in the plan view (fig. 24).
In regards to claim 17, Tomimatsu teaches the limitations discussed above in addressing claim 12. Tomimatsu further teaches the limitations wherein the first and second inner supporters (SP) include respective first insulating pillars [0059] and the outer supporters (HR) include respective second insulating pillars [0047].
In regards to claim 18, Tomimatsu teaches the limitations discussed above in addressing claim 12. Tomimatsu further teaches the limitations wherein a diameter of the first contact plug is different from a diameter of the second contact plug (fig. 46: (CC) and (HU) can have different cross-sectional widths/diameters).
In regards to claim 19, Tomimatsu teaches the limitations discussed above in addressing claim 12. Tomimatsu further teaches the limitations wherein each of the conductive patterns at least partially extends around the first and second inner supporters and the outer supporters in the plan view (fig 39: conductive features (CC) have portions of SP and HR between respective elements (CC)).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALVIN Y CHOI whose telephone number is (571)270-7882. The examiner can normally be reached M-F 8-4 (Pacific Time).
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CALVIN CHOI
Patent Examiner
Art Unit 2812
/CALVIN Y CHOI/Patent Examiner, Art Unit 2812