DETAILED ACTION
This office action is in response to communication filed on 02/26/2026. Claims 1, 14 and 20 have been amended. Claims 1-20 are pending on this application.
Response to Arguments
2. Applicant's arguments filed 02/26/2026 have been fully considered but they are not persuasive.
With respect to claim 20. Under remarks, applicant argued “Shutts fails to disclose: receiving an analog input voltage from a battery, wherein the analog input voltage comprises a voltage supplied by the battery generating a digital signal corresponding to the analog input voltage; generating a reference voltage control signal by applying a fixed voltage drop to the digital signal”. Examiner respectful disagrees from the following:
Col. 9 lines 12-18 of Shutts discloses: fixed voltage drop for Resistor 0.1 Ohm and 0.2 Ohm algorithms: 50 mv, 100 mv, and 200 mv and current limit for each algorithm for digital controller subsystem 380 to control current through sensor resistor 270 in Fig. 3.
Col. 10 lines 5- 12 of Shutts discloses: Controller sub-system 380 may compare voltage Vx or current 270 to a predetermined battery charge current and/or an over-current threshold signal or level, and then output or send a voltage level or signal to input IN1 and forcing the same voltage level at Vy. Thus, the controller 380 compares the measurement voltage of digital signal output of ADC 350 with a threshold signal level of each algorithm 50mv, 100mv, and 200mv to adjust or increase the signal to the DAC 370.
Accordingly, the fixed threshold voltage 50mv, or 100mv, or and 200 mv applying to digital output signal of ADC 350 for controller 380 to compare the level of digital output signal of ADC 350 to the fixed level of 50 mv, or 100 mv, or 200 mv algorithms to adjust or increase the signal to DAC 370.
From explained above, Fig. 3 of Shutts disclose receiving an analog input voltage (analog voltage Vx) from a battery (Battery 220), wherein the analog input voltage (Vx) comprises a voltage supplied by the battery (Vy Batter 220) generating a digital signal (digital output signal of analog-to-digital converter “ADC” 350) corresponding to the analog input voltage (Vx); generating a reference voltage control signal (digital output signal of 380) by applying a fixed voltage drop (the fixed threshold voltage 50mv, or 100mv, or and 200 mv applying to digital output signal of ADC 350 for controller 380 to compare the level of digital output signal of ADC 350 to the fixed level of 50 mv, or 100 mv, or 20 0mv algorithms to adjust or increase the signal to DAC 370) to the digital signal (digital output signal of ADC 350).
Accordingly, Shutt teach, or suggest each and every feature of amended independent claim 20 Therefore, examiner sustained 35 USC §103 rejection of claim 20 from above reasons.
With respect to claim 1 and 14. Under remarks, applicant argued “Shutts and Naffziger, whether taken alone or as a combination, fails to disclose, teach, or suggest inter alia: an analog-to-digital module configured to receive an analog input voltage from a battery, and generate a digital signal corresponding to the analog input voltage, wherein the analog input voltage comprises a voltage supplied by the battery; a voltage drop module coupled to the analog-to-digital module, the voltage drop module configured to receive one or more of a fixed voltage drop or a modulation voltage drop, and generate a reference voltage control signal based on the digital signal and one or more of the fixed voltage drop or the modulation voltage drop”.
Examiner respectful disagree from the following:
Fig. 3 of Shutts discloses an analog-to-digital module (analog-to-digital converter “ADC” 350) configured to receive an analog input voltage (analog signal Vx) from a battery (batter 220), and generate a digital signal (output digital signal of ADC 350) corresponding to the analog input voltage (analog signal Vx) , wherein the analog input voltage (analog signal Vx) comprises a voltage supplied by the battery (battery 220); a controller subsystem (380) coupled to the analog-to-digital module (ADC 350), the controller subsystem (380) configured to receive one or more of a fixed voltage drop (Col. 9 lines 12-18 of Shutts discloses” fixed voltage drop for Resistor 0.1 Ohm and 0.2 Ohm for algorithms: 50 mv, 100 mv, and 200 mv and current limit for each algorithm for digital controller subsystem 380 to control current through sensor resistor 270”) or a modulation voltage drop (Col. 9 lines 12-28 discloses “ fixed voltage drop of Resistor 0.1 Ohm and 0.2 Ohm algorithms: 50 mv, 100 mv, and 200 mv”), and generate a reference voltage control signal (digital output signal of 380 to control the DAC 370) based on the digital signal (output digital signal ADC 350) of and one or more of the fixed voltage drop (Col. 9 lines 12-28 discloses voltage drop 50 mv, 100 mv, and 200 mv for each algorithm for Resistor 0.1 Ohm and 0.2 Ohm) or the modulation voltage drop (Col. 9 lines 12-28 discloses voltage drop modulation 50 mv, 100 mv, and 200 mv algorithm).
Fig. 2 of Naffziger et al. discloses a digital voltage drop module (37) configured to received fixed voltage drop (digital Vfixed from ADC 34) or a modulation voltage drop (modulation of Fixed digital output signal of Vfixed), and generate a reference voltage control signal (VDIGDROP) based on one or more of the fixed voltage drop (VFixed) or the modulation voltage drop (Fixed digital output signal of 34).
Naffziger et al. cure the deficiencies “digital voltage drop” of Shutt for the purpose of “Adjustments are provided to compensate for the differences in the fixed reference voltage and the supply voltage” in paragraph 0010 of Naffziger et al.
Accordingly, Shutt and Naffziger in combination, teach, or suggest each and every feature of amended independent Claims 1 and 14. Therefore, examiner sustained §103 rejection of Claims 1 and 14 from above reasons.
The rejections of the independent claims 2, 5-13, 15, 18 and 19 are sustained in this office action.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claim 20 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shutt et al. U. S patent 7,656,127.
Fig. 3 of Shutt et al. discloses a method of controlling a voltage supply (Vy) for a sensor (230) , the method comprising: receiving an analog input voltage (analog input voltage Vx of ADC 350) from a battery (battery 220), wherein the analog input voltage (input voltage Vx of ADC 350) comprises a voltage supplied (Vy) by the battery (batter 220); generating a digital signal (output digital signal of ADC 350) corresponding to the analog input voltage (input voltage Vx of ADC 350), comprises a voltage supplied (Vy) by the battery (battery 220); generating a reference voltage control signal (output control voltage of digital controller subsystem 380) by applying a fixed voltage drop (Col. 9 lines 12-18 and Col. 10 lines 5- 12 disclose “the fixed threshold voltage 50mv, or 100mv, or and 200 mv algorithms for 0.1 Ohm or 0.2 Ohm resistor are applying to digital output signal of ADC 350 for controller 380 to compare the level of digital output signal of ADC 350 to the fixed level of 50 mv, or 100 mv, or 200 mv algorithms to adjust or increase the signal to DAC 370) to the digital signal (output of ADC 350); generating, using a digital-to-analog converter (DAC 370) and based on the reference voltage control signal (output voltage control signal of 380), a reference voltage signal (output reference voltage signal of DAC 370) ; and generating a control voltage (control voltage of gate transistor 314) based on comparing (comparing of E/A 316) the reference voltage signal (output reference voltage of DAC 370) to a sensed voltage (sensed of Vx by sense resistor 230), wherein the control voltage (control voltage of GATE 314) is configured to control supply voltage (Vy) for the sensor (sense resistor 230).
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 1, 2, 7-11, and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Shutt et al. U.S. patent No. 7,656,127 in view Naffziger Pub. No. 2005/0093619.
Regarding claim 1 , Fig. 3 of Shutt et al. discloses a digital control loop (301) for sensor supply (Resistor sensor supply 230) comprising: an analog-to-digital module (ADC 350) configured to receive an analog input voltage (analog input voltage Vx of ADC 350) from a battery (battery 220), and generate a digital signal (digital output of ADC 350) corresponding to the analog input voltage (analog input of 350), wherein the analog input voltage (analog input voltage Vx of ADC 350) comprises a voltage supplied (Vy) by the battery (battery 220); a digital controller subsystem module (380) coupled to the analog-to-digital module (350), the digital controller subsystem module (380) configured to receive one or more of a fixed voltage drop or a modulation voltage drop (Col. 9 lines 12-18 and Col. 10 lines 5- 12 disclose “the fixed threshold voltage 50mv, or 100mv, or and 200 mv algorithms for 0.1 Ohm or 0.2 Ohm resistor are applying to digital output signal of ADC 350 for controller 380 to compare the level of digital output signal of ADC 350 to the fixed level of 50 mv, or 100 mv, or 200 mv algorithms to adjust or increase the signal to DAC 370 ), and generate a reference voltage control signal (output control voltage of 380) based on one or more of the fixed voltage drop (Col. 9 lines 12-18 and Col. 10 lines 5- 12 disclose “the fixed threshold voltage 50mv, or 100mv, or and 200 mv algorithms for voltage drop of 0.1 Ohm or 0.2 Ohm resistor are applying to digital output signal of ADC 350 for controller 380 to compare the level of digital output signal of ADC 350 to the fixed level of 50 mv, or 100 mv, or 200 mv algorithms to adjust or increase the signal to DAC 370 ) or the modulation voltage drop (Col. 9 lines 12-18 and Col. 10 lines 5- 12 disclose “the fixed modulation voltage 50mv, or 100mv, or and 200 mv algorithms drop for 0.1 Ohm or 0.2 Ohm resistor are applying to digital output signal of ADC 350 for controller 380 to compare the level of digital output signal of ADC 350 to the fixed level of 50 mv, or 100 mv, or 200 mv algorithms to adjust or increase the signal to DAC 370 ); a digital-to-analog module (DAC 370) coupled to the digital controller subsystem module (380), the digital-to-analog module (DAC 370) configured to generate a reference voltage (reference voltage output of DAC 370) based on the reference voltage control signal (output control voltage of 380); and a voltage regulator module (E/A 316) coupled to the digital-to-analog module (DAC 370) and at least one sensor (sense resistor 230), the voltage regulator module (E/A 316) configured to compare the reference voltage (reference voltage output of DAC 370) to a sensed voltage (Vy) at an output node (TERM1 node) coupled to the at least one sensor (sense resistor 230) , and control a supply voltage (Vy) for the at least one sensor (sense 230) based on the comparison (E/A 316) of the reference voltage (output reference voltage of DAC 370) to the sensed voltage (sense voltage Vx).
However, Shutt et al. do not disclose digital controller subsystem module (380) is a digital voltage drop module as claimed.
Fig. 2 of Naffziger et al. disclose a method of controlling a voltage supply (Vx) for a sensor (Rx), the method comprising: receiving an analog input voltage (input voltage of ADC 35); generating a digital signal (digital output of ADC 35) corresponding to the analog input voltage (analog input of ADC 35); a voltage drop module (37) coupled to the analog-to-digital module (ADC 37), the voltage drop module (37) configured to receive one or more of a fixed voltage drop or a modulation voltage drop (Fixed digital output signal of 34) , and generate a reference voltage control signal (VDIGDROP) based on one or more of the fixed voltage drop or the modulation voltage drop (Fixed digital output signal of 34).
Shutt e al. and Naffziger et al. are common subject matter of digital control loop for voltage supply; therefore, it would have been obvious before the effective filing date of claimed invention to incorporate digital voltage drop process of Naffziger et al. into Shutt et al. for the purpose of provide adjustments to compensate for the differences in the fixed reference voltage and the supply voltage (paragraph 0010 of Naffziger et al. discloses “Adjustments are provided to compensate for the differences in the fixed reference voltage and the supply voltage”).
Regarding claim 2. Shutt e al. and Naffziger et al. applied to claim 1 above, Fig. 2 of Nafziger et al. further discloses wherein the voltage drop module (37) is configured to generate the reference voltage control signal (VDIGDROP ) by subtracting (subtraction of DIFF 37) the fixed voltage drop (Fixed digital output signal of 34) from the digital signal (digital output of ADC 35) corresponding to the analog input voltage (input of ADC 35), wherein the reference voltage control signal (VDIGDROP ) has a fixed value (fixed desired voltage DES).
Regarding claim 7. Shutt e al. and Naffziger et al. applied to claim 1 above, Fig.3 of Shutt e al. further discloses wherein the digital-to-analog module (DAC 370) comprises: a digital-to-analog converter (370) configured to process the reference voltage control signal (control voltage output of 380) to generate the reference voltage (reference voltage output of DAC 370).
Regarding claim 8. Shutt e al. and Naffziger et al. applied to claim 1 above, Fig. 3 of Shutt e al. further discloses wherein the voltage regulator module (E/A 316) comprises: a differential amplifier (E/A 316) having a first input terminal (IN1) configured to receive the reference voltage (output of DAC 370) and a second input terminal (IN2) configured to receive the sensed voltage (Vx, Vy); a power transistor (314) having a gate terminal (GATE 314) coupled to an output terminal of the differential amplifier (output of 316) ; and a voltage divider (220, 230) coupled to the power transistor (314) and the second input terminal (IN2) of the differential amplifier (316).
Regarding claim 9. Shutt e al. and Naffziger et al. applied to claim 8 above, Fig. 3 of Shutt e al. further discloses wherein the voltage divider (220, 230) is configured to generate the sensed voltage (Vx, Vy).
Regarding claim 10. Shutt e al. and Naffziger et al. applied to claim 8 above, Fig. 3 of Shutt e al. further discloses wherein a drain terminal (DRAIN 314) of the power transistor (314) is coupled to the output node (TERM1) and the voltage divider (220, 230).
Regarding claim 11. Shutt e al. and Naffziger et al. applied to claim 10 above, Fig. 3 of Shutt e al. further discloses wherein the voltage divider (220, 230) is configured to scale down (Vy scale down to Vx and Ground) a voltage at the output node (Voltage Vx and Vy at TERM2 and TERM2) to a level (level of Vx, Vy) equal to the reference voltage (level output of DAC 370).
Regarding claim 13. Shutt e al. and Naffziger et al. applied to claim 8 above, Fig. 3 of Shutt e al. further discloses wherein the fixed voltage drop is configurable (Col. 9 lines 12-18 discloses fixed voltage drop configurable of: 50mv, 100mv, and 200mv by digital controller subsystem module).
Regarding claim 14. Fig. 3 of Shutt et al. discloses a transceiver (The recitation that transceiver has not been given patentable weight because it has been held that a preample is denied the effect of a limitation where the claim is draw to a structure and the portion of the claim following the preample is a self-contained description of the structure not depending for completeness upon the introductory clause. Kropa v. Robie, 88 USPQ 478 (ccpa 1951) comprising: a digital control loop (301) for sensor supply (Resistor sensor supply 230) comprising: an analog-to-digital module (ADC 350) configured to receive an analog input voltage (analog input Vx of ADC 350) from a battery (batter 220), and generate a digital signal (output digital signal of 350) corresponding to the analog input voltage (analog input of ADC 350), wherein the analog input voltage (analog input voltage Vx) comprises a voltage supplied (Vy) by the battery (220); a digital controller subsystem module (380) coupled to the analog-to-digital module (ADC 350) , the digital controller subsystem module (380) configured to receive one or more of a fixed voltage drop or a modulation voltage drop (Col. 9 lines 12-18 discloses fixed voltage drop of : 50mv, 100mv, and 200mv for voltage drop of 01 Ohm and 0.2 Ohm resistor), and generate a reference voltage control signal (control voltage output of 380) based on one or more of the fixed voltage drop (Col. 9 lines 12-18 and Col. 10 lines 5- 12 disclose “the fixed threshold voltage 50mv, or 100mv, or and 200 mv algorithms for voltage drop of 0.1 Ohm or 0.2 Ohm resistor are applying to digital output signal of ADC 350 for controller 380 to compare the level of digital output signal of ADC 350 to the fixed level of 50 mv, or 100 mv, or 200 mv algorithms to adjust or increase the signal to DAC 370 ) or the modulation voltage drop (Col. 9 lines 12-18 and Col. 10 lines 5- 12 disclose “the fixed threshold voltage 50 mv, or 100 mv, or and 200 mv algorithms for 0.1 Ohm or 0.2 Ohm resistor voltage drop are applying to digital output signal of ADC 350 for controller 380 to compare the level of digital output signal of ADC 350 to the fixed level of 50 mv, or 100 mv, or 200 mv algorithms to adjust or increase the signal to DAC 370 ); a digital-to-analog module (DAC 370) coupled to the digital controller subsystem module (380), the digital-to- analog module (DAC 370) configured to generate a reference voltage (output reference voltage of 370) based on the reference voltage control signal (control voltage input signal of DAC 370); and a voltage regulator module (E/A 316) coupled to the digital-to-analog module (DAC 370) and at least one sensor (230), the voltage regulator module (E/A 316) configured to compare the reference voltage (reference voltage output of DAC 370) to a sensed voltage (Vx, Vy) at an output node (TERM1, TERM2) coupled to the at least one sensor (sense resistor 230) , and control a supply voltage (supply voltage Vy) for the at least one sensor (sense resistor 230) based on the comparison (E/A 316) of the reference voltage (output reference voltage of DAC 370) ) to the sensed voltage (Vx).
However, Shutt et al. do not disclose digital controller subsystem module (380) is a digital voltage drop module as claimed.
Fig. 2 of Naffziger et al. disclose a method of controlling a voltage supply (Vx) for a sensor (Rx), the method comprising: receiving an analog input voltage (input voltage of ADC 35); generating a digital signal (digital output of ADC 35) corresponding to the analog input voltage (analog input of ADC 35); a voltage drop module (37) coupled to the analog-to-digital module (ADC 37), the voltage drop module (37) configured to receive one or more of a fixed voltage drop or a modulation voltage drop (Fixed digital output signal of 34) , and generate a reference voltage control signal (VDIGDROP) based on one or more of the fixed voltage drop or the modulation voltage drop (Fixed digital output signal of 34).
Shutt e al. and Naffziger et al. are common subject matter of digital control loop for voltage supply; therefore, it would have been obvious before the effective filing date of claimed invention to incorporate digital voltage drop process of Naffziger et al. into Shutt et al. for the purpose of provide adjustments to compensate for the differences in the fixed reference voltage and the supply voltage (paragraph 0010 of Naffziger et al. discloses “Adjustments are provided to compensate for the differences in the fixed reference voltage and the supply voltage”).
Regarding claim 15. Shutt e al. and Naffziger et al. applied to claim 14 above, Fig. 2 of Nafziger et al. further discloses wherein the voltage drop module (37) is configured to generate the reference voltage control signal (VDIGDROP ) by subtracting (subtraction of DIFF 37) the fixed voltage drop (Fixed digital output signal of 34) from the digital signal (digital output of ADC 35) corresponding to the analog input voltage (input of ADC 35), wherein the reference voltage control signal (VDIGDROP ) has a fixed value (fixed desired voltage DES).
7. Claims 5-6 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Shutt et al. and Naffziger applied to claims 1 and 14 above, in further view of Straeussnigg et al. Pub. No. 2022/0306457.
Regarding claims 5-6 and 18-19. Shutt et al. and Naffziger applied to claims 1 and 14 above, respectively, do not disclose a digital filter configured to filter an output of the ADC to generate the digital signal corresponding to the analog input voltage; wherein the digital filter is a low pass filter.
Fig. 5 of Straeussnigg et al. discloses a digital control loop for sensor (302) (comprising: an analog-to-digital module (308) comprises: an analog-to-digital converter (308) configured to process the analog input voltage (306); and a digital filter (310) configured to filter an output of the ADC (output of 308) to generate filtered the digital signal (output of 310) corresponding to the analog input voltage (306); wherein the digital filter is a low pass filter (low pass filter of 310) .
Shutt e al./Naffziger et al. and Straeussnigg et al. are common subject matter of digital control loop for sensor; therefore, it would have been obvious before the effective filing date of claimed invention to incorporate Straeussnigg et al. into Shutt et al./Naffziger for the purpose provide a low pass digital filtered for a digital noise compensation (paragraph 0029 of Straeussnigg et al.).
8. Claims 12 is rejected under 35 U.S.C. 103 as being unpatentable over Shutt et al. and Naffziger applied to claim 1 above, in further view of Park et al. Pub. No. 2017/0083033.
Shutt et al. and Naffziger applied to claim 1 above does not discloses wherein the analog input voltage is received from a voltage source associated with a vehicle.
Fig. 1 of Park et al. discloses digital control loop (100) comprising an analog-to-digital converter (114; paragraph 0024), analog input voltage (Vout input of 114) is received from a voltage source (LOAD 115) associated with a vehicle (paragraph 0099 discloses apparatus 100 associate with vehicles) .
Shutt e al./Naffziger et al. and Park et al. are common subject matter of digital control loop; therefore, it would have been obvious before the effective filing date of claimed invention to incorporate Park et al. into Shutt et al./Naffziger for the purpose of implement an apparatuses within a variety of other apparatuses (e.g., electronic systems), such as televisions, cellular telephones, personal computers (e.g., laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radios, video players, audio players (e.g., MP3 (Motion Picture Experts Group, Audio Layer 5) players), vehicles, medical devices (e.g., heart monitor, blood pressure monitor, etc.), set top boxes, and others (paragraph 0099 of Park et al.).
Allowable Subject Matter
9. Claims 3 and 4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior arts do not teach: wherein the voltage drop module is configured to generate the reference voltage control signal by applying the modulation voltage drop to the digital signal during a forward communication configured to transmit a message to the at least one sensor.
10. Claims 16 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior arts do not teach: wherein the voltage drop module of the digital control loop is configured to generate the reference voltage control signal by applying the modulation voltage drop to the digital signal during a forward communication configured to transmit a message to the at least one sensor.
Conclusion
11. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 8:30 – 5:00 Monday-Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications.
04/22/2026
/LINH V NGUYEN/Primary Examiner, Art Unit 2845