DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
Notice of Claim Interpretation
Claims in this application are not interpreted under 35 U.S.C. 112(f) unless otherwise noted in an office action.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 22 December 2025 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5, 8, 10, 11, 17, 19-23, 26, and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Lien et al. (US 2016/0350183) in view of Chang (US 2012/0087183).
In regards to claims 1 and 20, Lien teaches a method, comprising:
programming, before performance of one or more manufacturing operations associated with assembly of a memory system (“The memory controller or refresh controller determines whether the indicator bit written to the second nonvolatile memory array is valid (630) and does so during various stages of memory system operation. … Accordingly, when the number of high-temperature events that the memory system will be subjected to is known, such as in a production or manufacturing test setting, the memory controller or refresh controller can be configured to determine whether the indicator bit is valid until the memory system is shipped from the production/manufacturing facility by limiting the determining to power ups after the known number of high-temperature events.”, paragraph 0056):
first data to a first set of blocks of the memory system (“In some embodiments, example method 600 includes reading data stored in a first nonvolatile memory array (610).”, paragraph 0052)
programming, after the performance of the one or more manufacturing operations, second data to a second set of blocks of the memory system (“In some embodiments, example method 600 includes writing the data read from the first nonvolatile memory array (610) and an indicator bit to a second nonvolatile memory array (620).”, paragraph 0054) based at least in part on identifying that at least a portion of the first data is associated with reduced data integrity (“The memory controller or refresh controller determines whether the indicator bit written to the second nonvolatile memory array is valid (630) and does so during various stages of memory system operation. … Accordingly, when the number of high-temperature events that the memory system will be subjected to is known, such as in a production or manufacturing test setting, the memory controller or refresh controller can be configured to determine whether the indicator bit is valid until the memory system is shipped from the production/manufacturing facility by limiting the determining to power ups after the known number of high-temperature events.”, paragraph 0056; “Data stored in the resistive nonvolatile memory is written to the transistor-based nonvolatile memory before the high-temperature event and written back to the resistive nonvolatile memory after the high-temperature event. Accordingly, the transistor-based nonvolatile memory is used as backup storage, and any data lost or corrupted in the resistive nonvolatile memory due to the high-temperature event is recovered from the transistor-based nonvolatile memory.”, paragraph 0020);
identifying, during a start-up procedure, an indication to perform a refresh operation for the first set of blocks (“For example, the memory controller or refresh controller determines whether the indicator bit is valid in response to power up of the memory system after a high-temperature event, a received command after a high-temperature event, after a predetermined number of power ups, in response to a received command after a predetermined number of temperature events, or in response to a power up after a predetermined number of temperature events.”, paragraph 0056); and
performing the refresh operation for the first set of blocks based at least in part on the second data in the second set of blocks (“Refreshing the data stored in the resistive nonvolatile memory array includes replacing the stored data with the backup data written to the second nonvolatile memory array (620).”, paragraph 0057).
Lien fails to teach programming, before performance of one or more manufacturing operations associated with assembly of a memory system:
metadata associated with the first data to a subset of the first set of blocks; and
identifying, using the metadata, that at least a portion of the first data is associated with reduced data integrity.
Chang teaches programming, before performance of one or more manufacturing operations associated with assembly of a memory system:
metadata associated with the first data to a subset of the first set of blocks (“As further appreciated by the present inventors, a reference cell associated with the data cells of S10 can be programmed to have an initial programmed resistance which is greater than a predetermined data threshold resistance (e.g., a logic "1) (S20).”, paragraph 0048); and
identifying, using the metadata, that at least a portion of the first data is associated with reduced data integrity (“When the time interval elapses, a read operation is performed on the reference cell along with the data cells associated with the reference cell (S30). If the data read from the reference cell is a logic ‘1’ (in the amorphous state) no error in the reference data is detected and operations continue at S25 after the time interval is reset. If, however, the data read from the reference cell is a logic ‘0’ (in the crystalline state) an error signal is generated indicating that the initial programmed resistance of the reference cell has been reduced to below a predetermined reference threshold resistance, which in the present embodiment according to the inventive concept, is equal to the predetermined data threshold resistance.”, paragraph 0050)
“to increase the likelihood that an error in the data can be avoided” (paragraph 0067).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Lien with Chang to include programming, before performance of one or more manufacturing operations associated with assembly of a memory system:
metadata associated with the first data to a subset of the first set of blocks; and
identifying, using the metadata, that at least a portion of the first data is associated with reduced data integrity
“to increase the likelihood that an error in the data can be avoided” (id.).
In regards to claims 3 and 21, Lien further teaches that the second data is associated with improving the reduced data integrity of the at least the portion of the first data (“Accordingly, the transistor-based nonvolatile memory is used as backup storage, and any data lost or corrupted in the resistive nonvolatile memory due to the high-temperature event is recovered from the transistor-based nonvolatile memory.”, paragraph 0020).
In regards to claims 4 and 22, Lien further teaches that the second data comprises a backup copy of the first data (“A write circuit of sense amplifier and write driver writes the data read from the data cells of first nonvolatile memory array to the corresponding backup data cells of the second nonvolatile memory array. Accordingly, the data written to the second nonvolatile memory array becomes backup data for the data stored in the first nonvolatile memory array.”, paragraph 0054).
In regards to claim 5, Lien further teaches that the second data comprises parity bits associated with the first data (“Refresh controller 515 determines whether the indicator bit(s) flip logic states or become corrupted using error detection techniques such as cyclic redundancy checks (CRCs), repetition codes, parity bits, checksums, or error correcting codes.”, paragraph 0045).
In regards to claims 8 and 17, Chang further teaches that the first data comprises user data (“It will be understood that a data cell is configured to store data specified by, for example, a user of a system in which the PRAM device is included.”, paragraph 0038).
In regards to claims 10 and 19, Chang further teaches that the at least the portion of the first data is associated with the reduced data integrity based at least in part on a temperature of at least a portion of the memory system during the programming of the first data, and the temperature is associated with causing a reduced data retention for a second subset of the first set of blocks storing the at least the portion of the first data (“In contrast, a reference cell is configured to store an initial programmed resistance that can be used to determine whether the data stored in the PRAM device is more likely to be in-error due to excessive temperatures.”, paragraph 0038).
In regards to claims 11 and 23, Lien teaches a method, comprising:
programming, before performance of one or more manufacturing operations associated with assembly of a memory system (“The memory controller or refresh controller determines whether the indicator bit written to the second nonvolatile memory array is valid (630) and does so during various stages of memory system operation. … Accordingly, when the number of high-temperature events that the memory system will be subjected to is known, such as in a production or manufacturing test setting, the memory controller or refresh controller can be configured to determine whether the indicator bit is valid until the memory system is shipped from the production/manufacturing facility by limiting the determining to power ups after the known number of high-temperature events.”, paragraph 0056):
data to a set of blocks of the memory system (“In some embodiments, example method 600 includes reading data stored in a first nonvolatile memory array (610).”, paragraph 0052);
identifying, after the performance of the one or more manufacturing operations, data characteristics associated with at least a portion of the data (“The memory controller or refresh controller determines whether the indicator bit written to the second nonvolatile memory array is valid (630) and does so during various stages of memory system operation.”, paragraph 0056) based at least in part on identifying that the at least the portion of the data is associated with reduced data integrity (“Accordingly, when the number of high-temperature events that the memory system will be subjected to is known, such as in a production or manufacturing test setting, the memory controller or refresh controller can be configured to determine whether the indicator bit is valid until the memory system is shipped from the production/manufacturing facility by limiting the determining to power ups after the known number of high-temperature events.”, paragraph 0056; “Data stored in the resistive nonvolatile memory is written to the transistor-based nonvolatile memory before the high-temperature event and written back to the resistive nonvolatile memory after the high-temperature event. Accordingly, the transistor-based nonvolatile memory is used as backup storage, and any data lost or corrupted in the resistive nonvolatile memory due to the high-temperature event is recovered from the transistor-based nonvolatile memory.”, paragraph 0020);
performing an operation to adjust the data characteristics to improve the data integrity of the at least the portion of the data based at least in part on identifying the data characteristics (“When it is determined that the indicator bit is valid (630—yes), example method 600 includes refreshing the data stored in the resistive memory array (640). Refreshing the data stored in the resistive nonvolatile memory array includes replacing the stored data with the backup data written to the second nonvolatile memory array (620).”, paragraph 0057);
identifying, during a start-up procedure, an indication to perform a refresh operation for the set of blocks (“For example, the memory controller or refresh controller determines whether the indicator bit is valid in response to power up of the memory system after a high-temperature event, a received command after a high-temperature event, after a predetermined number of power ups, in response to a received command after a predetermined number of temperature events, or in response to a power up after a predetermined number of temperature events.”, paragraph 0056); and
performing the refresh operation for the set of blocks using the adjusted data characteristics (“Refreshing the data stored in the resistive nonvolatile memory array includes replacing the stored data with the backup data written to the second nonvolatile memory array (620).”, paragraph 0057).
Lien fails to teach programming, before performance of one or more manufacturing operations associated with assembly of a memory system:
metadata associated with the data to a subset of the set of blocks; and
identifying, using the metadata, that the at least the portion of the data is associated with reduced data integrity.
Chang teaches programming, before performance of one or more manufacturing operations associated with assembly of a memory system:
metadata associated with the data to a subset of the set of blocks (“As further appreciated by the present inventors, a reference cell associated with the data cells of S10 can be programmed to have an initial programmed resistance which is greater than a predetermined data threshold resistance (e.g., a logic "1) (S20).”, paragraph 0048); and
identifying, using the metadata, that the at least the portion of the data is associated with reduced data integrity (“When the time interval elapses, a read operation is performed on the reference cell along with the data cells associated with the reference cell (S30). If the data read from the reference cell is a logic ‘1’ (in the amorphous state) no error in the reference data is detected and operations continue at S25 after the time interval is reset. If, however, the data read from the reference cell is a logic ‘0’ (in the crystalline state) an error signal is generated indicating that the initial programmed resistance of the reference cell has been reduced to below a predetermined reference threshold resistance, which in the present embodiment according to the inventive concept, is equal to the predetermined data threshold resistance.”, paragraph 0050)
“to increase the likelihood that an error in the data can be avoided” (paragraph 0067).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Lien with Chang to include programming, before performance of one or more manufacturing operations associated with assembly of a memory system:
metadata associated with the data to a subset of the set of blocks; and
identifying, using the metadata, that the at least the portion of the data is associated with reduced data integrity
“to increase the likelihood that an error in the data can be avoided” (id.).
In regards to claim 26, Chang further teaches that the metadata indicates one or more conditions associated with the one or more manufacturing operations (“The reference cell RC is used to indicate temperature information, such as thermal energy and temperature change, related to the PRAM device 200, which may indicated that a rewrite may be needed.”, paragraph 0053).
In regards to claim 27, Chang further teaches that the metadata indicates one or more temperatures at the memory system, and wherein the metadata is used to identify the second set of blocks as being affected by the one or more temperatures (“The reference cell RC is used to indicate temperature information, such as thermal energy and temperature change, related to the PRAM device 200, which may indicated that a rewrite may be needed.”, paragraph 0053).
Claims 6, 7, 15, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Lien et al. (US 2016/0350183) in view of Chang (US 2012/0087183) and Shur et al. (US 10,008,278).
In regards to claims 6 and 15, Lien in view of Chang teaches claims 1 and 11. Lien in view of Chang fails to teach that the at least the portion of the first data is associated with the reduced data integrity based at least in part on word lines associated with accessing a second subset of the first set of blocks, the second subset of the first set of blocks associated with storing the at least the portion of the first data. Shur teaches that the at least the portion of the first data is associated with the reduced data integrity based at least in part on word lines associated with accessing a second subset of the first set of blocks, the second subset of the first set of blocks associated with storing the at least the portion of the first data (“memory blocks that are close to the edge of the memory array would typically exhibit low storage reliability and low endurance levels compared to memory blocks that are located farther away from the edge of the memory array”, Col. 3, lines 47-50) in order that “the probability of a memory block becoming unusable reduces considerably” (Col. 4, lines 57-58). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Lien with Chang and Shur such that the at least the portion of the first data is associated with the reduced data integrity based at least in part on word lines associated with accessing a second subset of the first set of blocks, the second subset of the first set of blocks associated with storing the at least the portion of the first data in order that “the probability of a memory block becoming unusable reduces considerably” (id.).
In regards to claims 7 and 16, Shur further teaches that the word lines are associated with the reduced data integrity based at least in part on a location or a geometric layout of the word lines in the memory system (“memory blocks that are close to the edge of the memory array would typically exhibit low storage reliability and low endurance levels compared to memory blocks that are located farther away from the edge of the memory array”, Col. 3, lines 47-50).
Claims 9 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Lien et al. (US 2016/0350183) in view of Chang (US 2012/0087183) and Crawford et al. (US 2014/0192605).
In regards to claims 9 and 18, Lien in view of Chang teaches claims 1 and 11. Lien in view of Chang fails to teach that identifying that the at least the portion of the first data is associated with the reduced data integrity comprises:
determining that the at the least portion of the first data is associated with a weakest data integrity of the first data.
Crawford teaches that identifying that the at least the portion of the first data is associated with the reduced data integrity comprises:
determining that the at least the portion of the first data is associated with a weakest data integrity of the first data (“Since the refreshes are done on a per row basis (typically 8K bits per row), the weakest cell in a row will determine the refresh requirements of any given row”, paragraph 0002).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Lien with Chang and Crawford such that identifying that the at least the portion of the first data is associated with the reduced data integrity comprises:
determining that the at least the portion of the first data is associated a weakest data integrity of the first data
in order to maximize performance while maintaining reliability.
Claims 13, 14, 24, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Lien et al. (US 2016/0350183) in view of Chang (US 2012/0087183) and Lee (US 2015/0113322).
In regards to claims 13 and 24, Lien in view of Chang teaches claims 11 and 23. Lien in view of Chang fails to teach that the data characteristics comprise read thresholds associated with the data, and wherein performing the operation to adjust the data characteristics comprises:
identifying adjusted read thresholds to improve the data integrity of the at least the portion of the data; and
storing the adjusted read thresholds.
Lee teaches that the data characteristics comprise read thresholds associated with the data (“In the operating method of the data storing system, a read operation is performed with the first read voltage in the read retry table (S310). A direction of the change of the first read voltage is the first direction. The first read voltage may be a read voltage when the read operation on a previous page is passed.”, paragraph 0068), and wherein performing the operation to adjust the data characteristics comprises:
identifying adjusted read thresholds to improve the data integrity of the at least the portion of the data (“Referring to FIG. 9, when the read operation is failed, a read operation is performed again by changing a read voltage level as described below.”, paragraph 0067); and
storing the adjusted read thresholds (“When the read operation is passed in step S320, the read voltage and the direction during the performance of the corresponding read operation are stored (S390).”, paragraph 0080)
in order to correctly read data without degrading performance (paragraphs 0036-0037).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Lien with Chang and Lee such that the data characteristics comprise read thresholds associated with the data, and wherein performing the operation to adjust the data characteristics comprises:
identifying adjusted read thresholds to improve the data integrity of the at least the portion of the data; and
storing the adjusted read thresholds
in order to correctly read data without degrading performance (id.).
In regards to claims 14 and 25, Lien in view of Chang teaches claims 11 and 23. Lien in view of Chang fails to teach that the data characteristics comprise voltage levels associated with the data, and wherein performing the operation to adjust the data characteristics comprises:
performing a programming operation to adjust the voltage levels associated with the at least the portion of the data to improve the data integrity of the at least the portion of the data.
Lee teaches that the data characteristics comprise voltage levels associated with the data (“In the operating method of the data storing system, a read operation is performed with the first read voltage in the read retry table (S310). A direction of the change of the first read voltage is the first direction. The first read voltage may be a read voltage when the read operation on a previous page is passed.”, paragraph 0068), and wherein performing the operation to adjust the data characteristics comprises:
performing a programming operation to adjust the voltage levels associated with the at least the portion of the data to improve the data integrity of the at least the portion of the data (“When the read operation is passed in step S320, the read voltage and the direction during the performance of the corresponding read operation are stored (S390).”, paragraph 0080)
in order to correctly read data without degrading performance (paragraphs 0036-0037).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Lien with Chang and Lee such that the data characteristics comprise voltage levels associated with the data, and wherein performing the operation to adjust the data characteristics comprises:
performing a programming operation to adjust the voltage levels associated with the at least the portion of the data to improve the data integrity of the at least the portion of the data
in order to correctly read data without degrading performance (id.).
Response to Arguments
Applicant’s arguments with respect to the claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Or-Bach (US 2015/0340316) teaches using a reference cell to determine temperature history. The other art made of record and not relied upon is considered pertinent to applicant's disclosure. Bueb (US 12,456,507) is a related patent to this application.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN SADLER whose telephone number is (571)270-7699. The examiner can normally be reached Monday - Friday 8am - 5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Nathan Sadler/Primary Examiner, Art Unit 2139 3 April 2026