CTNF 18/404,610 CTNF 81461 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 101 07-04-01 AIA 07-04 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. Step 1: Yes. Claim 1 recites “a method, comprising: receiving…temperature” which is a process. Step 2, Prong One: The claim recites an abstract idea as follows: Claim 1 recites the step “determining that the first temperature indicated by the one or more first bits is within a first temperature range of a plurality of temperature ranges, the plurality of temperature ranges each spanning a respective portion of a total temperature range measurable by the temperature sensor; applying, based at least in part on the first temperature being within the first temperature range, a first-order operation corresponding to the first temperature range to the one or more first bits to determine one or more second bits indicating a second temperature associated with the semiconductor device; and outputting, from the circuit of the temperature sensor, the one or more second bits indicating the second temperature” which falls within both mental processes and mathematical calculation. The steps may be carried out as a mental process if the algorithm is simple enough, and as a mathematical process if the algorithm is more complicated. Therefore, the claimed invention recites an abstract idea. Claim 1 recites mental processes that may be carried out in the human mind or with the aid of pencil and paper in simple situations, or by hardware processors, for more complicated situations. The claimed invention thus recited as an abstract idea. Claim 1 recites mathematical concepts and/or mental processes, that may be carried out in human mind or with the aid of pencil and paper in simple situations. The claim does not recite a particular equation or algorithm for making the recited combining and performing steps, this just means that the abstract idea is being recited broadly enough to monopolize all possible equations or algorithms that might be used (Please also see MPEP 2106.04(a)(2)(III)(A), (B), (C), and (D). The broadest reasonable interpretation of the steps is that those steps fall within the mental process groupings of abstract ideas because they cover concepts performed in the human mind, including observation, evaluation, judgment, and opinion. See MPEP 2106.04(a)(2), subsection III. The recited “circuit” and “temperature sensor” are not particular devices. They are recited as tools used to perform the abstract idea. Step 2, Prong Two: Practical application? No. The recited steps in claim 1 are not performed by any particular device. Steps “receiving…, determining…, applying…” are merely data gathering. Step “outputting” does not provide any information as how the output are accomplished. As such, there are no meaningful constraints on the outputting step such that the particular service would apply because it is not limited to any particular manner. This limitation is at most an instruction to “apply” the judicial exception. Further, the step “outputting…” represents extra solution activity because it is a mere nomial or tangential addition to the claim. See MPEP 2106.05(I) for more information on this point, including explanations from judicial decisions including Alice Corp. Pty. Ltd. v. CLS Bank Int'l, 573 U.S. 208, 224-26 (2014). This limitation represents extra-solution activity because it is a mere nominal or tangential addition to the claim. See MPEP 2106.05(g), discussing limitations that the Federal Circuit has considered to be insignificant extra-solution activity, for instance the step of printing a menu that was generated through an abstract process in Apple, Inc. v. Ameranth, Inc., 842 F.3d 1229, 1241-42 (Fed. Cir. 2016) and the mere generic presentation of collected and analyzed data in Electric Power Group, LLC v. Alstom S.A., 830 F.3d 1350, 1354 (Fed. Cir. 2016). Therefore, claim 1 when viewed as a whole does not integrate the judicial exception into a practical application. Claim 1 when viewed as a whole does not provide meaningful limitations beyond generally linking the use of the judicial exception to a particular environment to transform the judicial exception into patent-eligible subject matter (see MPEP 2106.05(e)). Per MPEP 2106.04(d)(1) and 2106.05(a), the claim when viewed as a whole or in ordered combination does not provide an improvement to other technology or technical field. The claim limitations as recited when viewed as a whole or in ordered combination do not include the components or steps of the invention that provide the improvement described in the specification. The step “outputting…” when viewed as a whole is generally linking the use of the judicial exception to a particular technological environment or field of use (see MPEP 2106.05(h)). At Step 2B, the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception, for reasons that are analogous to the discussion of additional elements at Prong 2. Claim 15 recites an apparatus which does not offer a meaningful limitation beyond generally linking the apparatus to a particular technological environment, that is, implementation via first and second circuits and a semiconductor device. In other words, the apparatus claim is no different from the method claim 1 in substance; the method claim recites the abstract idea while the apparatus claim recites generic components configured to implement the same abstract idea. The claims do not amount to significantly more than the underlying abstract idea. Dependent claims 2 and 15 add limitations which are data and data gathering merely extending the abstract idea without adding any additional elements. The limitation “outputting…” represents extra solution activity because it is a mere nomial or tangential addition to the claim. See MPEP 2106.05(I) for more information on this point, including explanations from judicial decisions including Alice Corp. Pty. Ltd. v. CLS Bank Int'l, 573 U.S. 208, 224-26 (2014). This limitation represents extra-solution activity because it is a mere nominal or tangential addition to the claim. See MPEP 2106.05(g), discussing limitations that the Federal Circuit has considered to be insignificant extra-solution activity, for instance the step of printing a menu that was generated through an abstract process in Apple, Inc. v. Ameranth, Inc., 842 F.3d 1229, 1241-42 (Fed. Cir. 2016) and the mere generic presentation of collected and analyzed data in Electric Power Group, LLC v. Alstom S.A., 830 F.3d 1350, 1354 (Fed. Cir. 2016). Dependent claim 3 adds data and data gathering merely extending the abstract idea without adding any additional elements. Dependent claim 4 adds limitations which are merely data gathering and insignificant merely extending the abstract idea without adding any additional elements. without adding any additional elements. The steps “generating… and outputting…” represent extra solution activity because it is a mere nomial or tangential addition to the claim. Dependent claim 5 adds limitation which is merely data gathering without adding any additional elements. Dependent claim 6 adds a limitation which is data merely extending the abstract idea without adding any additional elements. Dependent claim 7 adds a limitation which is data gathering merely extending the abstract idea without adding any additional elements. Dependent claims 8-13 add limitations which is data gathering merely extending the abstract idea without adding any additional elements. Dependent claims 13 and 14 add limitations which are considered tools used to perform the abstract idea when viewed as a whole do not integrate the abstract idea into a practical application. Dependent claim 17 adds limitations which are data merely extending the abstract idea without adding any additional elements. The recited circuits as recited in the claim are tools which are not particular devices. The recited circuits when viewed as a whole do not integrate the abstract idea into a practical application. The recited limitations “output…” represent extra solution activity because it is a mere nomial or tangential addition to the claim. Dependent claim 18 adds limitations which are data merely extending the abstract idea without adding any additional elements. The recited “third circuit”, “bandgap circuit”, and “oscillator” as recited in the claim are tools which are not particular devices. The recited circuits and oscillator when viewed as a whole do not integrate the abstract idea into a practical application. The recited limitations “(outputted) first and second signal” represent extra solution activity because it is a mere nomial or tangential addition to the claim. Dependent claim 19 recites limitations which are data gathering and insignificant extra solution. The recited “second circuit” as recited in the claim is tool, not a particular device, when viewed as a whole does not integrate the abstract idea into a practical application. The recited limitation “(outputted) one or more second bits” represents extra solution activity because it is a mere nomial or tangential addition to the claim. The limitation “applying…” is merely data gathering. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim s 1, 4-6, 9-13, 15, and 20 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Micro Technology, Inc., “A Temperature Sensor with Linearization Technique Achieving an Accuracy of + 1C (3d) from -40 C to 120 C for GDDR6/GDDR7”, 5 Pages” (hereinafter “Micron”)(Submitted by Applicants) . Regarding claims 1, 15, and 20, Micron discloses a method, comprising: receiving, at a circuit of a temperature sensor (see temperature sensor at Introduction, Page 1, column 1) associated with a semiconductor device, one or more first bits indicating a first temperature associated with the semiconductor device (see Fig. 1b, code output from Linearization circuit, see Pages 1 and 2, Circuit implementation for description of Fig. 1b. Digital logic in Fig. 1B utilizes two counters to generate the JEDEC compliant code which is indicative of temperature); determining that the first temperature indicated by the one or more first bits is within a first temperature range of a plurality of temperature ranges, the plurality of temperature ranges each spanning a respective portion of a total temperature range measurable by the temperature sensor (Page 2 and Figs. 3 and 4: dividing temperature sensing range into four small regions as shown in Fig. 4 which are performed with four individual linearization equations); applying, based at least in part on the first temperature being within the first temperature range, a first-order operation (see formula at table 1) corresponding to the first temperature range to the one or more first bits to determine one or more second bits indicating a second temperature associated with the semiconductor device (Page 2 and Figs. 3 and 4: dividing temperature sensing range into four small regions as shown in Fig. 4 which are performed with four individual linearization equations which are first order equations to save chip area and power consumption. See Page 3: the temperature regions in Fig. 5 and the digital code has 10 bits associating with temperature such as the one shown in Fig. 5 and Table 1); and outputting, from the circuit of the temperature sensor, the one or more second bits indicating the second temperature (Page 3: The four linearization equations are shown in Table 1. A linear equation is built for calculating the code shift based on the raw value, so that the code error Fig. 5b is compensated in this temperature region). Regarding claim 4, Micron discloses generating, at a second circuit of the temperature sensor, the one or more first bits based at least in part on a first current and a second current (see Fig. 1b, current signals I PTAT and I OTC), wherein the first current is based at least in part on measuring an actual temperature of the semiconductor device and the second current corresponds to a reference current (Fig. 1b; current signal IPTAT and IOTC; code output from Linearization circuit, see Pages 1 and 2, Circuit implementation for description of Fig. 1b. Digital logic in Fig. 1B utilizes two counters to generate the JEDEC compliant code which is indicative of temperature); and outputting the one or more first bits from the second circuit of the temperature sensor to the circuit of the temperature sensor based at least in part on the generating (Fig. 1b, code output from Linearization circuit, see Pages 1 and 2, Circuit implementation for description of Fig. 1b. Digital logic in Fig. 1B utilizes two counters to generate the JEDEC compliant code which is indicative of temperature). Regarding claim 5, Micron discloses determining the first-order operation based at least in part on a second-order error associated with the first temperature range, wherein applying the first-order operation to the one or more first bits is based at least in part on the determining (Page 2, col. 2: The error at two temperature points is 0. The entire curve at Fig. 4b is an approximately parabolic curve assuming that the high order error is negligible. The temperature sensing range is divided into four small regions which are performed with four individual linearization equations. Instead of highly complex second-order equations, the four linearization equations are only first order equations). Regarding claim 6, Micron discloses wherein the second-order error is based at least in part on one or more characteristics of a substrate associated with the semiconductor device (Abstract). Regarding claim 9, Micron discloses wherein each respective portion of the total temperature range span a respective quantity of temperatures (see Fig. 4 for respective range of temperature). Regarding claim 10, Micron discloses wherein one or more of the respective quantities of temperatures are different (Page 3, col. 1, quantities such as 7 bits and 10 bits). Regarding claim 11, Micron discloses wherein each respective quantity of temperatures comprises a same quantity ((Page 3, col. 1, quantities such as 7 bits). Regarding claim 12, Micron discloses wherein the semiconductor device comprises a memory device comprising one or more memory cells (Page 1, col. 1). Regarding claim 13, Micron discloses wherein the semiconductor device comprises a complementary metal-oxide semiconductor (CMOS) device (see References section) . Conclusion Claims 2, 7, 8, and 16-19 are patentably distinguishable over the prior art of record. Holloway (US 6183131) discloses A temperature sensor corrects the parabolic curvature error in the output signal without attempting to linearize the reference voltage itself. A temperature sensor produces a temperature output signal that is a function of the ratio of a temperature dependent voltage to a reference voltage. The temperature sensor uses a nonlinear reference voltage, e.g., the reference voltage conforms to a curve with an approximately hyperbolic shape over a temperature range, so that the ratio of the temperature dependent voltage to the hyperbolic reference voltage will be linear. The hyperbolic reference voltage is generated by summing a reference voltage with an appropriate temperature dependent voltage. The "gain" or slope of the ratio is altered by adjusting a scaling factor. Finally, the offset of the ratio is adjusted so that the temperature sensor produces the appropriate output signal at ambient temperature. Thus, despite the present of curvature in the reference voltage of the temperature sensor, a highly linear and accurate temperature sensor may be constructed using the hyperbolic linearization technique without requiring complex or expensive reference voltage correction circuits (cols. 8-10). However, Holloway does not disclose “receiving, at the circuit of the temperature sensor after outputting the one or more second bits, one or more third bits indicating a third temperature associated with the semiconductor device; determining that the third temperature indicated by the one or more third bits is within a second temperature range of the plurality of temperature ranges, wherein the second temperature range is different from the first temperature range; applying, based at least in part on the third temperature being within the second temperature range, a second first-order operation corresponding to the second temperature range to the one or more third bits to determine one or more fourth bits indicating a fourth temperature associated with the semiconductor device; and outputting, from the circuit of the temperature sensor, the one or more fourth bits indicating the fourth temperature”. Regarding claims 2 and 16, the closest prior art of record either alone or in combination fails to anticipate or render obvious the combination wherein “receiving, at the circuit of the temperature sensor after outputting the one or more second bits, one or more third bits indicating a third temperature associated with the semiconductor device; determining that the third temperature indicated by the one or more third bits is within a second temperature range of the plurality of temperature ranges, wherein the second temperature range is different from the first temperature range; applying, based at least in part on the third temperature being within the second temperature range, a second first-order operation corresponding to the second temperature range to the one or more third bits to determine one or more fourth bits indicating a fourth temperature associated with the semiconductor device; and outputting, from the circuit of the temperature sensor, the one or more fourth bits indicating the fourth temperature” in combination with other limitations in the claims as defined by Applicants. Claim 3 depends on claim 2 and therefore is also patentably distinguishable over the prior art of record. Regarding claim 7, the closest prior art of record either alone or in combination fails to anticipate or render obvious the combination wherein “determining a respective first-order operation...determining” in combination with other limitations in the claims as defined by Applicants. Regarding claim 8, the closest prior art of record either alone or in combination fails to anticipate or render obvious the combination wherein “wherein a difference between the first temperature and an actual temperature of the semiconductor device is greater than a difference between the second temperature and the actual temperature based at least in part on applying the first-order operation to the one or more first bits” in combination with other limitations in the claims as defined by Applicants. Regarding claim 17, the closest prior art of record either alone or in combination fails to anticipate or render obvious the combination wherein “wherein the apparatus further comprises: a third circuit of the temperature sensor configured to output a first current and a second current, wherein the first current is based at least in part on an actual temperature of the semiconductor device the second current corresponds to a reference current; and a fourth circuit of the temperature sensor configured to output a first signal associated with a first frequency that is based at least in part on the first current and a second signal associated with a second frequency that is based at least in part on the second current, wherein generating the one or more first bits is based at least in part on comparing the first signal to the second signal” in combination with other limitations in the claims as defined by Applicants. Claim 18 depends from claim 17 and therefore is also patentably distinguishable over the prior art of record. Regarding claim 19, the closest prior art of record either alone or in combination fails to anticipate or render obvious the combination wherein “wherein each segment of a plurality of segments of the second circuit is associated with a respective temperature range and a respective first-order operation, wherein the second circuit is configured to: apply the first-order operation corresponding to the first temperature range to the one or more first bits by routing the one or more first bits through a first segment of the plurality of segments of the second circuit associated with the first temperature range, wherein the one or more second bits are output based at least in part on routing the one or more first bits through the first segment.” in combination with other limitations in the claims as defined by Applicants. 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. JP 2024503359 (Published date is after Application’s effective filing date) discloses the linearity of a magnetoresistive sensor without reducing sensitivity. The present disclosure relates to a correction method for correcting an output signal provided by a magnetoresistive sensor in the presence of an external magnetic field, which corrects the output signal from a linear response due to the amplitude of a higher order component signal of the output voltage. determining a corrected output signal by determining the deviation of the signal and compensating the output signal of the higher-order component signal such that the corrected output signal changes proportionally to changes in the external magnetic field within a range of variation; Equipped with. The present disclosure further relates to an integrated circuit (IC) configured to perform a method for deriving a common variable used in performing a correction method and a characterization method for a plurality of magnetoresistive sensors (Abstract). CN 114878028 (Publication date is 04-17-2026 which is after the effective filing date of the instant Application) discloses a temperature error detection method, device, equipment and storage medium of temperature sensor based on band gap reference circuit. The temperature error detection method comprises: obtaining the temperature sensing circuit model parameter; obtaining a temperature coefficient simulation curve based on the temperature sensing circuit model parameter; obtaining a first parameter and a second parameter by the temperature coefficient simulation curve; obtaining a first-order standard curve based on the first parameter and the second parameter; The temperature error is obtained based on the temperature coefficient simulation curve and the first-order standard curve. The temperature error detection method obtains a first-order standard curve based on the temperature coefficient simulation curve obtained by simulating the temperature sensing circuit without complex multi-order calculation, thereby reducing the calculation complexity, saving the calculation cost and improving the calculation efficiency (Abstract). Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHUONG HUYNH whose telephone number is (571)272-2718. The examiner can normally be reached M-F: 9:00AM-5:30PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew M Schechter can be reached at 571-272-2302. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PHUONG HUYNH/Primary Examiner, Art Unit 2857 May 9, 2026 Application/Control Number: 18/404,610 Page 2 Art Unit: 2857 Application/Control Number: 18/404,610 Page 3 Art Unit: 2857 Application/Control Number: 18/404,610 Page 4 Art Unit: 2857 Application/Control Number: 18/404,610 Page 5 Art Unit: 2857 Application/Control Number: 18/404,610 Page 6 Art Unit: 2857 Application/Control Number: 18/404,610 Page 7 Art Unit: 2857 Application/Control Number: 18/404,610 Page 8 Art Unit: 2857 Application/Control Number: 18/404,610 Page 9 Art Unit: 2857 Application/Control Number: 18/404,610 Page 10 Art Unit: 2857 Application/Control Number: 18/404,610 Page 11 Art Unit: 2857 Application/Control Number: 18/404,610 Page 12 Art Unit: 2857 Application/Control Number: 18/404,610 Page 13 Art Unit: 2857 Application/Control Number: 18/404,610 Page 14 Art Unit: 2857 Application/Control Number: 18/404,610 Page 15 Art Unit: 2857
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