CTNF 18/404,837 CTNF 84617 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 1. Claims 1-10 and 16-20 are currently pending in this application. Claims 11-15 are withdrawn from consideration per the applications election of Group I (with traverse) on 04/03/2026. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA Claim (s) 1, 8-10, and 16-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Wiegert et al. (Pre-Grant Publication No. US 2022/0413994 A1), hereinafter Wiegert . 2. With respect to claim 1, Wiegert taught an apparatus, comprising: a computer system embodied on one or more co-packaged integrated circuits (0050, where the SoC contains a plurality of chiplets in accordance with 0349), wherein the computer system includes: a plurality of networks that includes a first network and a second, independent network (0351, where each chiplet is a network via the NoC connection); and a plurality of agent circuits configured to send and/or receive transactions over one or more of the plurality of networks (0240, where the agent core is managing the peripheral and various processing components, which are the agents in accordance with the applicant’s specification: 0032), wherein the plurality of agent circuits includes: a plurality of processor circuits connected to the first network but not the second network (0349, where the different chiplets are connected via circuitry and contain difference processors); a plurality of memory controllers configured to couple to system memory that includes dynamic random-access memories (0178. See also: 0230-0231); a non-system-memory gateway circuit coupled to the first network and the second network and configured to perform routing of non-DRAM transactions between ones of the plurality of agent circuits (0375, where, at least, the LLC is not DRAM.), including between: a first pair of agent circuits both coupled to the first network but not the second network (0372 & 0375, where between CPU cores can be seen); a second pair of agent circuits both coupled to the second network but not the first network (0372 & 0375, where between CPU cores can be seen and the system can have a plurality of processors); and a third pair of agent circuits, one of which is coupled to the first network but not the second network, and another of which is coupled to the second network but not the first network (0372 & 0375, where between CPU cores and other devices/chiplets can be seen). 3. As for claim 8, it is rejected on the same basis as claim 1. In addition, Wiegert taught wherein the NSM GW circuit acts as a termination point for non-DRAM transactions, such that network credit is returned to a particular agent circuit that has initiated a request message for a particular non-DRAM transaction prior to the request message being delivered to a different agent circuit specified in the request message (0375, where the message terminates at a gateway and is routed/forwarded under broadest reasonable interpretation). 4. As for claim 9, it is rejected on the same basis as claim 1. In addition, Wiegert taught wherein the non-DRAM transactions are performed via a specific virtual channel dedicated to non-DRAM transactions, wherein the NSM GW circuit includes input buffers for the first and second networks for each possible source agent circuit, and wherein the NSM GW circuit further includes output buffers for the first and second networks for each possible destination agent circuit (0063). 5. As for claim 10, it is rejected on the same basis as claim 1. In addition, Wiegert taught wherein the plurality of agent circuits further includes: a plurality of SoC agents coupled to the second network but not the first network; and one or more graphics processing units coupled to a third network that is independent from the first and second networks, the first, second, and third networks all having different ordering properties (0375, where the channel order can be seen in 0306. See also: 0393); wherein the computer system has a unified memory architecture in which a given one of the plurality of memory controllers is configured to receive DRAM transactions from ones of the plurality of processor circuits coupled to the first network, from ones of the plurality of SoC agents coupled to the second network, and from ones of the one or more GPUs coupled to the third network (0375, the shared memory). 6. With respect to claim 16, Wiegert taught an apparatus, comprising: a computer system situated on one or more co-packaged integrated circuits (0050, where the SoC contains a plurality of chiplets in accordance with 0349), wherein the computer system includes: a plurality of networks that includes a first network and a second, independent network (0351, where each chiplet is a network via the NoC connection); and a plurality of agent circuits configured to send and/or receive transactions over one or more of the plurality of networks, wherein the plurality of agent circuits includes: a plurality of processor circuits connected to the first network but not the second network (0349, where the different chiplets are connected via circuitry and contain difference processors); a plurality of input/output devices connected to the second network but not the first network (0233); one or more memory controllers connected to both the first and second networks, wherein the one or more memory controllers are configured to couple to system memory that includes dynamic random-access memories (0178. See also: 0230-0231); and a non-system-memory gateway circuit coupled to the first network and the second network and configured to perform centralized routing for non-DRAM transactions between ones of the plurality agent circuits, including routing for one-to-one and one-to-many transactions (0372 & 0375). 7. As for claim 17, it is rejected on the same basis as claim 16. In addition, Wiegert taught wherein the NSM GW circuit is configured to perform centralized routing for one-to-one non-DRAM transactions (0375), including from: a first of the plurality of processor circuits to a second of the plurality of processor circuits (0372 & 0375, where between cores can be seen); a first of the plurality of I/O devices to a second of the plurality of I/O devices (0372 & 0375, where between cores can be seen and the system can have a plurality of processors. Further, the cores include peripheral devices in accordance with 0359); one of the plurality of processor circuits to one of the plurality of I/O devices; and one of the plurality of I/O devices to one of the plurality of processor circuits (0372 & 0375, where between CPU cores and other devices/chiplets can be seen). 8. As for claim 18, it is rejected on the same basis as claim 16. In addition, Wiegert taught wherein the NSM GW circuit is configured to perform centralized routing for one-to-many transactions, including from a first processor circuit to at least two memory controllers (0375). 9. As for claim 19, it is rejected on the same basis as claim 16. In addition, Wiegert taught wherein the NSM GW circuit is configured to perform centralized routing for non-DRAM transactions between a first processor circuit and a network switch element within either the first or second network (0375, where the switch can be seen in 0267). 10. As for claim 20, it is rejected on the same basis as claim 16. In addition, Wiegert taught wherein the computer system is embodied on a plurality of integrated circuits arranged according to a chiplet architecture (0265) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Wiegert, in view of Official Notice . 11. As for claim 5, it is rejected on the same basis as claim 1. While Wiegert taught the details of a gateway connected between different SoC circuits that routes data between different networks (0375), Wiegert did not explicitly state wherein the one or more co-packaged ICs include at least a first IC and a second IC, wherein the NSM GW circuit is a first instance of a plurality of NSM GW circuits located on the first IC, and wherein the NSM GW circuit is configured to route non-DRAM transactions originating from an origin agent circuit on the first IC to a target agent circuit on the second IC. On the other hand, the examiner gives Official Notice that containing a plurality of instances of a network component for initial routing was well known and therefore, it would have been obvious to a person having ordinary skill in the art, at the time of the effective filing of the invention to modify the teachings of Wiegert, to utilize the aforementioned routing techniques, in order to generate an efficiently operating system chip that contains enough components to appropriate hand a given load based on the system’s architecture. 12. As for claim 6, it is rejected on the same basis as claim 5. In addition, Wiegert taught wherein the first IC and the second IC each have a system-on-a-chip architecture (0375). 13. As for claim 7, it is rejected on the same basis as claim 1. While Wiegert taught the details of a gateway connected between different SoC circuits that routes data between different networks (0375), Wiegert did not explicitly state wherein the NSM GW circuit includes a first NSM GW sub-circuit and a second NSM GW sub-circuit, the first NSM GW sub-circuit being configured to handle initial routing of non-DRAM transactions originating from a first subset of the plurality of agent circuits, and the second NSM GW sub-circuit being configured to handle initial routing of non-DRAM transactions originating from a second, non-overlapping subset of the plurality of agent circuits. On the other hand, the examiner gives Official Notice that containing a plurality of instances of a network component for initial routing was well known and therefore, it would have been obvious to a person having ordinary skill in the art, at the time of the effective filing of the invention to modify the teachings of Wiegert, to utilize the aforementioned routing techniques, in order to generate an efficiently operating system chip that contains enough components to appropriate hand a given load based on the system’s architecture . Allowable Subject Matter Claims 2-4 are allowed over the prior-art. Response to Arguments 07-37 AIA Applicant's arguments filed 04/03/2026 have been fully considered but they are not persuasive. 14. The applicant argues on page 8 that “ The Examiner categorized Group I and Group II as subcombinations usable together. OA at 2. There are multiple fatal problems with this assertion. First, Groups I and II are not subcombinations usable within a combination. Examples of subcombinations usable together include a transmitter and a receiver in a communications system ”. However, Group I appears to be directed towards an entire System-on-a-Chip architecture that contains a plurality of components that work together while Group II is directed, specifically, to a method for operating a gateway that could usable together when applied to the NSM GW component of Group I’s SoC architecture . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. (a) Pflederer (Pre-Grant Publication No. US 2024/0320140 A1), 0034-0035. (b) Ray et al. (Pre-Grant Publication No. US 2022/0413854 A1), 0033 & 0346. (c) Kumar et al. (Pre-Grant Publication No. US 2021/0318965 A1), 0084 & 0055. (d) Kondapalli et al. (Pre-Grant Publication No. US 2019/0380171 A1), 0013. (e) Ganguli et al. (Pre-Grant Publication No. US 2019/0044849 A1), 0078. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH L GREENE whose telephone number is (571)270-3730. The examiner can normally be reached Monday - Thursday, 10:00am - 4:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nicholas R. Taylor can be reached at 571 272-3889. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JOSEPH L GREENE/Primary Examiner, Art Unit 2443 Application/Control Number: 18/404,837 Page 2 Art Unit: 2443 Application/Control Number: 18/404,837 Page 3 Art Unit: 2443 Application/Control Number: 18/404,837 Page 4 Art Unit: 2443 Application/Control Number: 18/404,837 Page 5 Art Unit: 2443 Application/Control Number: 18/404,837 Page 6 Art Unit: 2443 Application/Control Number: 18/404,837 Page 7 Art Unit: 2443 Application/Control Number: 18/404,837 Page 8 Art Unit: 2443 Application/Control Number: 18/404,837 Page 9 Art Unit: 2443
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