DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-9, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Morita (US 2015/0155100).
Regarding claim 1, Morita discloses a multilayer ceramic electronic component (Fig. 1-3) comprising: a multilayer body (Fig. 1, 1) including a plurality of insulator layers (Fig. 1, 12) including ceramic ([0017]), and a plurality of inner electrode layers (Fig. 1, 13); wherein an aspect ratio of a metal particle in the inner electrode layers is about 1.8 or greater and less than 5 ( 2.09-5.04 [0024] and Table 1).
Regarding claim 3, Morita further discloses that the multilayer ceramic electronic component is a multilayer ceramic capacitor (Fig. 1).
Regarding claim 4, Morita further discloses a plurality of outer electrodes (Fig. 1, 20) on an outer surface of the multilayer body (Fig. 1).
Regarding claim 5, Morita further discloses that the multilayer body has a rectangular or substantially rectangular parallelepiped shape (Fig. 1).
Regarding claim 6, Morita further discloses that the multilayer body includes rounded corners and ridges (Fig. 1).
Regarding claim 7, Morita further discloses that each of the plurality of insulator layers includes barium titanate ([0026]), calcium titanate, strontium titanate, barium calcium titanate, or calcium zirconate as a main component.
Regarding claim 8, Morita further discloses that each of the plurality of insulator layers includes Mg compounds, Mn compounds ([0026]), Si compounds, Al compounds, V compounds, or Ni compounds as a subcomponent.
Regarding claim 9, Morita further discloses that an average thickness of each of the plurality of insulator layers is about 0.2 µm or greater and about 2 µm or less ([0027]).
Regarding claim 20, Morita further discloses a method for producing the multilayer ceramic electronic component according to Claim 1, comprising: sintering the plurality of insulator layers including the ceramic, and the plurality of inner electrode layers (Fig. 1, [0028-29]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Morita (US 2015/0155100) in view of KIM et al (US 2021/0183572).
Regarding claim 2, Morita fails to teach the claim limitations.
KIM teaches that a thickness T (µm) of the plurality of inner electrode layers and a volume V (mm3) of the multilayer body satisfy a following relational expression (1):T≤0.0552xlnV+0.5239 (1)
([0028 and 0039] boy has a volume of (0.8*0.8*1.5= 0.96mm3 and internal electrodes thickness is 0.4 µm therefore 0.0552*ln(0.96)+0.5239 = 0.523 which means 0.4 ≤ 0.523 is true and teaches the claim limitations).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to combine the teachings of KIM to the invention of Morita, in order to improve the high temp reliability of the capacitor (KIM [0006]).
Claim(s) 10-13 and 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Morita (US 2015/0155100) in view of SASABAYASHI (US 2016/0093438).
Regarding claim 10, Morita fails to teach the claim limitations.
SASABAYASHI teaches that each of the plurality of outer electrodes includes an underlying electrode layer and a plating layer on the underlying electrode layer ([0008]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to combine the teachings of SASABAYASHI to the invention of Morita, in order to tight adhesion of the capacitor to a board (SASABAYASHI [0007]).
Regarding claim 11, Morita, as modified by SASABAYASHI, further teaches that the underlying electrode layer is a baked electrode layer including a glass and a metal (SASABAYASHI [0054]).
Regarding claim 12, Morita, as modified by SASABAYASHI, further teaches that the glass includes a BaO-SrO-B203-SiO2 glass frit ([0054]).
Regarding claim 13, Morita, as modified by SASABAYASHI, further teaches that the a thickness of the baked electrode layer is about 5 µm or greater and about 150 µm or less ([0047]).
Regarding claim 15, Morita, as modified by SASABAYASHI, further teaches that the underlying electrode layer is a thin film layer having a thickness of about 1 µm or less (can be 1 µm [0047]).
Regarding claim 16, Morita, as modified by SASABAYASHI, further teaches that the plating layer includes at least one of Cu ([0048]), Ni, Ag, Pd, Ag-Pd alloy, Au, or Sn.
Claim(s) 14 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Morita (US 2015/0155100) in view of SASABAYASHI (US 2021/0020380) “SASABAYASHI 380”.
Regarding claim 14, Morita fails to teach the claim limitations.
SASABAYASHI 380 teaches that each of the plurality of outer electrodes includes an underlying electrode layer and a plating layer on the underlying electrode layer ([0029]) and the underlying electrode layer is a resin electrode layer including conductive particles and a thermosetting resin ([0031]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to combine the teachings of SASABAYASHI 380 to the invention of Morita, in order to reduce or prevent generation of structural defects in a multilayer body (SASABAYASHI 380 [0007]).
Regarding claim 17, Morita fails to teach the claim limitations.
SASABAYASHI 380 teaches that each of the plurality of outer electrodes includes an underlying electrode layer and a plating layer on the underlying electrode layer ([0029]) and the plating layer includes a Ni plating layer and an Sn plating layer ([0033]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to combine the teachings of SASABAYASHI 380 to the invention of Morita, in order to reduce or prevent generation of structural defects in a multilayer body (SASABAYASHI 380 [0007]).
Claim(s) 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Morita (US 2015/0155100) in view of KANBE et al (US 2019/0355522).
Regarding claim 18, Morita fails to teach the claim limitations.
KANBE teaches that each of the plurality of outer electrodes includes an underlying electrode layer and a plating layer on the underlying electrode layer ([0009]), the plating layer includes a Ni plating layer and an Sn plating layer ([0065]), and the Ni plating layer has an average thickness of about 1 µm or greater and about 15 µm or less ([0130]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to combine the teachings of KANBE to the invention of Morita, in order to improve the capacitors strength against stress (KANBE [0010]).
Regarding claim 19, Morita fails to teach the claim limitations.
KANBE teaches that each of the plurality of outer electrodes includes an underlying electrode layer and a plating layer on the underlying electrode layer ([0009]), the plating layer includes a Ni plating layer and an Sn plating layer ([0065]), and the Sn plating layer has an average thickness of about 1 µm or greater and about 15 µm or less ([0130]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to combine the teachings of KANBE to the invention of Morita, in order to improve the capacitors strength against stress (KANBE [0010]).
Additional Relevant Prior Art:
ITO et al (US 2018/0090276) teaches relevant art in Fig. 2.
TERASHITA (US 2019/0304683) teaches relevant art in Fig. 1-5.
SASABAYASHI et al (US 2021/0020380) teaches relevant art in Fig. 1-4.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on only the reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL P MCFADDEN whose telephone number is (571)270-5649. The examiner can normally be reached M-Thur 8am-9pm PST.
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/MICHAEL P MCFADDEN/Primary Examiner, Art Unit 2848
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