Detail Office Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Status: Please all the replies and correspondence should be addressed to Examiner’s art unit 2629. Receipt is acknowledged of papers submitted on 01-05-2024 under new application; which have been placed of record in the file. Claims 1-20 are pending.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. Applicant has complied with one or more conditions for receiving the benefit of an earlier filing date under 35 U.S.C. . 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c).
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 9-10 and 18 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The applicant disclosure .does not have any written description in specification as well as in the drawing about what does limitation “content” represent or related to.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsuda; Toyohisa (US-20090148059-A1) hereinafter referenced as Matsuda in view of MATSUSHIRO NOBUHITO (JP H10-117287 A) hereinafter referenced as MATSUSHIRO. (Further, foreign document with English translation are provided in combination. Please Note that paragraph references refer to English translation and figure references refer to figures provided in foreign document).
Regarding Claim 1, Matsuda disclosing A method for compressing image data (para. 61, 66, disclosing compressing image data) in a display panel (para. 161 disclosing display panel displaying image data)) having a plurality of pixels (para. 14), comprising: grouping the plurality of pixels into a plurality of continuous blocks (paras. 14, 22, 23, plurality of pixels groups in continuous blocks compressed with encoding stored in memory in continuous blocks pattern such that when read back form memory and decoded displaying images paras. 20, 152,160), each block comprising a pixel array with M rows and N columns (please see fig. 3, para. 65), where M and N are positive integers; selecting a pixel pattern for a current block from a plurality of pixel patterns, a plurality of indexes being assigned to the plurality of pixel patterns one-by-one, each pixel pattern comprising a pixel array of M rows and N columns, and part of pixels in the pixel array of each pixel pattern are compressed (paras. 14, 22-23, 61, fig. 3, disclosing the vector quantization encoding circuit encodes the image. With the vector quantization technique, the image is encoded on a block-by-block basis. The vector quantization encoding circuit looks at the storage section and searches for a pixel pattern having the highest correlation (similarity) with a pixel pattern appearing on the image. The vector quantization encoding circuit reduces the amount of data by replacing the pixel pattern appearing on the received image with the index value of the searched pixel pattern, and thereby compresses the image data. When the codec circuit receives an index image, the vector quantization decoding circuit decodes the image. The vector quantization decoding circuit looks at the storage section, specifies a pixel pattern based on the index value representing the index image , and replaces the index value with the specified pixel pattern on a block-by-block basis to decode the image); wherein the first coding mode comprises an index of a pixel pattern assigned to the current block; the second coding mode comprises the index of the pixel pattern assigned to the current block plus a first number of contents (paras. 14, 22-23, 61, fig. 3, disclosing the vector quantization encoding circuit encodes the image. With the vector quantization technique, the image is encoded on a block-by-block basis. The vector quantization encoding circuit looks at the storage section and searches for a pixel pattern having the highest correlation (similarity) with a pixel pattern appearing on the image. The vector quantization encoding circuit reduces the amount of data by replacing the pixel pattern appearing on the received image with the index value of the searched pixel pattern, and thereby compresses the image data. When the codec circuit receives an index image, the vector quantization decoding circuit decodes the image (disclosing mode 1, and a bit width of the first coding mode is shorter than a bit width of the second coding mode.). The vector quantization decoding circuit looks at the storage section , specifies a pixel pattern based on the index value representing the index image, and replaces the index value with the specified pixel pattern on a block-by-block basis to decode the image). Further Matsuda discloses index of the pixel pattern assigned to the current block plus a first number of contents (para. 61 The vector quantization encoding circuit 11 reduces the amount of data (first mode) by replacing the pixel pattern appearing on the received image with the index value of the searched pixel pattern, and thereby compresses the image data). The image data encoded by the replacement with the index value will be hereinafter referred to as the index image; para. 64 discloses the contents of pixel patterns of blocks and the contents of a code book stored in the storage section; para. 65, disclosing the vector quantization decoding circuit 10 performs a vector quantization decoding process in which it refers to the code book in the storage section 13 for a pixel pattern corresponding to the index value representing the index image, and reconstructs a block consisting of 4.times.4 pixels of the referred pixel pattern).
However, Matsuda does not explicitly teach obtaining a similarity between a current block and a previous block; and coding the current block through a first coding mode in response to the similarity between the current block and the previous block complying with a preset similarity; coding the current block through a second coding mode in response to the similarity between the current block and the previous block not complying with the preset similarity.
However, prior art of MATSUSHIRO discloses a similarity between a current block and a previous block; and coding the current block through a first coding mode in response to the similarity between the current block and the previous block complying with a preset similarity; coding the current block through a second coding mode in response to the similarity between the current block and the previous block not complying with the preset similarity(please see paras. 25, 26 disclosing a plurality of combination pattern reference blocks 6 each consisting of four pixels are set. Then, the similarity between the set reference (preset pixel patterns value) block 6 and the target block 4 is compared. Here, when a reference block 6 similar to the target block 4 is detected, compression coding is performed using the combination pattern 8 of the detected reference block 6 (mode1). On the other hand, when the reference block 6 similar to the target block 4 is not detected (mode 2), the pixel value of each pixel in the target block 4 is encoded as it is. In this case, the information amount of the block of interest 4 is not compressed (mode 2).
Further Matsuda discloses index of the pixel pattern assigned to the current block plus a first number of contents (para. 61 The vector quantization encoding circuit 11 reduces the amount of data (first mode) by replacing the pixel pattern appearing on the received image with the index value of the searched pixel pattern, and thereby compresses the image data (This obviously suggests the compressed data (First mode) a bit width of the first coding mode is shorter than a bit width of the second coding mode 2 (uncompressed per MATSUSHIRO).
Matsuda teaches. A method for compressing image data in a display panel having a plurality of pixels, comprising: grouping the plurality of pixels into a plurality of continuous blocks, each block comprising a pixel array with M rows and N columns, where M and N are positive integers; selecting a pixel pattern for a current block from a plurality of pixel patterns, a plurality of indexes being assigned to the plurality of pixel patterns one-by-one, each pixel pattern comprising a pixel array of M rows and N columns, and part of pixels in the pixel array of each pixel pattern are compressed.
Matsuda teaches index of the pixel pattern assigned to the current block plus a first number of contents.
MATSUSHIRO teaches obtaining a similarity between a current block and a previous block; and coding the current block through a first coding mode in response to the similarity between the current block and the previous block complying with a preset similarity; coding the current block through a second coding mode in response to the similarity between the current block and the previous block not complying with the preset similarity.
Matsuda does not teach obtaining a similarity between a current block and a previous block; and coding the current block through a first coding mode in response to the similarity between the current block and the previous block complying with a preset similarity; coding the current block through a second coding mode in response to the similarity between the current block and the previous block not complying with the preset similarity.
Hence the prior art includes each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
In combination, Matsuda performs the same function as it does separately of managing process of A method for compressing image data in a display panel and index of the pixel pattern assigned to the current block.
MATSUSHIRO performs the same function as it does separately of obtaining a similarity between a current block and a previous block; and coding the current block through a first coding mode in response to the similarity between the current block and the previous block complying with a preset similarity; coding the current block through a second coding mode in response to the similarity between the current block and the previous block not complying with the preset similarity.
Therefore one of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately.
The results of the combination would have been predictable and resulted in modifying the invention of Matsuda to include obtaining a similarity between a current block and a previous block; and coding the current block through a first coding mode in response to the similarity between the current block and the previous block complying with a preset similarity; coding the current block through a second coding mode in response to the similarity between the current block and the previous block not complying with the preset similarity, as disclosed by MATSUSHIRO thereby able to convert an input image into a high-resolution image having a larger number of pixels than the input image as MATSUSHIRO discusses at para. 2.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art before the effective filing of the claimed invention.
Regarding Claim 2, Matsuda discloses selecting a pixel pattern for the current block comprising: selecting a first group of pixels and a second group of pixels from the current block based on each pixel pattern of the plurality of pixels patterns; calculating a first average value of the first group of pixels and a second average value of the second group of pixels; and assigning a pixel pattern to the current block in response to the first average value corresponding to the pixel pattern being larger than a minimum average threshold and the second average value corresponding to the pixel pattern beings smaller than a maximum average threshold, wherein the first group of pixels are located at a same positions as the pixels not being compressed from the corresponding pixel pattern; and the second group of pixels are located at same positions as the pixels being compressed from the pixel pattern (please see paras. 114-117 please notice average pixel values are positive (maximum) and average pixel values are negative (minimum).
MATSUSHIRO discloses a similarity between a current block and a previous block; and coding the current block through a first coding mode in response to the similarity between the current block and the previous block complying with a preset similarity; coding the current block through a second coding mode in response to the similarity between the current block and the previous block not complying with the preset similarity(please see paras. 25, 26 disclosing a plurality of combination pattern reference blocks 6 each consisting of four pixels are set. Then, the similarity between the set reference (preset pixel patterns value) block 6 and the target block 4 is compared. Here, when a reference block 6 similar to the target block 4 is detected, compression coding is performed using the combination pattern 8 of the detected reference block 6 (mode1). On the other hand, when the reference block 6 similar to the target block 4 is not detected (mode 2), the pixel value of each pixel in the target block 4 is encoded as it is. In this case, the information amount of the block of interest 4 is not compressed (mode 2).
Regarding Claim 3, Matsuda disclosing the current block is assigned with more than one pixel pattern, selecting a pixel pattern from the more than one pixel pattern by: comparing more than one first average value corresponding to the more than one pixel pattern; and assigning the pixel pattern with a largest first average value to the current block (para. 7)
Regarding Claim 4, Matsuda disclosing selecting a pixel pattern for the current block comprising: selecting a third group of pixels from the current block based on each pixel pattern of the plurality of pixels patterns; calculating a sum value of the third group of pixels for each pixel pattern; and assigning a pixel pattern corresponding to a largest sum value to the current block, wherein the third group of pixels are located at a same positions as the pixels not being compressed from the pixel pattern (paras. 112, 116, 118, label third are very arbitrary).
Regarding Claim 5, Matsuda disclosing a number of the compressed pixels in the pixel array of each pixel pattern is different from the other pixels patterns; and locations of the compressed pixels in the pixel array of each pixel pattern are different from the other pixels patterns (please see fig. 3, paras, 65-67)
Regarding Claim 18, Matsuda disclosing A method for compressing image data (para. 61, 66, disclosing compressing image data) in a display panel (para. 161 disclosing display panel displaying image data)) having a plurality of pixels (para. 14), comprising: grouping the plurality of pixels into a plurality of continuous blocks (paras. 14, 22, 23, plurality of pixels groups in continuous blocks compressed with encoding stored in memory in continuous blocks pattern such that when read back form memory and decoded displaying images paras. 20, 152,160), each block comprising a pixel array with M rows and N columns (please see fig. 3, para. 65), where M and N are positive integers; selecting a pixel pattern for a current block from a plurality of pixel patterns, a plurality of indexes being assigned to the plurality of pixel patterns one-by-one, each pixel pattern comprising a pixel array of M rows and N columns, and part of pixels in the pixel array of each pixel pattern are compressed (paras. 14, 22-23, 61, fig. 3, disclosing the vector quantization encoding circuit encodes the image. With the vector quantization technique, the image is encoded on a block-by-block basis. The vector quantization encoding circuit looks at the storage section and searches for a pixel pattern having the highest correlation (similarity) with a pixel pattern appearing on the image. The vector quantization encoding circuit reduces the amount of data by replacing the pixel pattern appearing on the received image with the index value of the searched pixel pattern, and thereby compresses the image data. When the codec circuit receives an index image, the vector quantization decoding circuit decodes the image. The vector quantization decoding circuit looks at the storage section, specifies a pixel pattern based on the index value representing the index image , and replaces the index value with the specified pixel pattern on a block-by-block basis to decode the image); wherein the first coding mode comprises an index of a pixel pattern assigned to the current block; the second coding mode comprises the index of the pixel pattern assigned to the current block plus a first number of contents (paras. 14, 22-23, 61, fig. 3, disclosing the vector quantization encoding circuit encodes the image. With the vector quantization technique, the image is encoded on a block-by-block basis. The vector quantization encoding circuit looks at the storage section and searches for a pixel pattern having the highest correlation (similarity) with a pixel pattern appearing on the image. The vector quantization encoding circuit reduces the amount of data by replacing the pixel pattern appearing on the received image with the index value of the searched pixel pattern, and thereby compresses the image data. When the codec circuit receives an index image, the vector quantization decoding circuit decodes the image (disclosing mode 1, and a bit width of the first coding mode is shorter than a bit width of the second coding mode.). The vector quantization decoding circuit looks at the storage section , specifies a pixel pattern based on the index value representing the index image, and replaces the index value with the specified pixel pattern on a block-by-block basis to decode the image). Further Matsuda discloses index of the pixel pattern assigned to the current block plus a first number of contents (para. 61 The vector quantization encoding circuit 11 reduces the amount of data (first mode) by replacing the pixel pattern appearing on the received image with the index value of the searched pixel pattern, and thereby compresses the image data). The image data encoded by the replacement with the index value will be hereinafter referred to as the index image; para. 64 discloses the contents of pixel patterns of blocks and the contents of a code book stored in the storage section; para. 65, disclosing the vector quantization decoding circuit 10 performs a vector quantization decoding process in which it refers to the code book in the storage section 13 for a pixel pattern corresponding to the index value representing the index image, and reconstructs a block consisting of 4.times.4 pixels of the referred pixel pattern).
Matsuda does not explicitly teach obtaining a similarity between a current block and a previous block; and coding the current block through a first coding mode in response to the similarity between the current block and the previous block complying with a preset similarity; coding the current block through a second coding mode in response to the similarity between the current block and the previous block not complying with the preset similarity.
However, prior art of MATSUSHIRO discloses a similarity between a current block and a previous block; and coding the current block through a first coding mode in response to the similarity between the current block and the previous block complying with a preset similarity; coding the current block through a second coding mode in response to the similarity between the current block and the previous block not complying with the preset similarity(please see paras. 25, 26 disclosing a plurality of combination pattern reference blocks 6 each consisting of four pixels are set. Then, the similarity between the set reference (preset pixel patterns value) block 6 and the target block 4 is compared. Here, when a reference block 6 similar to the target block 4 is detected, compression coding is performed using the combination pattern 8 of the detected reference block 6 (mode1). On the other hand, when the reference block 6 similar to the target block 4 is not detected (mode 2), the pixel value of each pixel in the target block 4 is encoded as it is. In this case, the information amount of the block of interest 4 is not compressed (mode 2).
Further Matsuda discloses index of the pixel pattern assigned to the current block plus a first number of contents (para. 61 The vector quantization encoding circuit 11 reduces the amount of data (first mode) by replacing the pixel pattern appearing on the received image with the index value of the searched pixel pattern, and thereby compresses the image data (This obviously suggests the compressed data (First mode) a bit width of the first coding mode is shorter than a bit width of the second coding mode 2 (uncompressed pixel data per MATSUSHIRO).
Matsuda teaches. A method for compressing image data in a display panel having a plurality of pixels, comprising: grouping the plurality of pixels into a plurality of continuous blocks, each block comprising a pixel array with M rows and N columns, where M and N are positive integers; selecting a pixel pattern for a current block from a plurality of pixel patterns, a plurality of indexes being assigned to the plurality of pixel patterns one-by-one, each pixel pattern comprising a pixel array of M rows and N columns, and part of pixels in the pixel array of each pixel pattern are compressed.
Matsuda teaches index of the pixel pattern assigned to the current block plus a first number of contents.
MATSUSHIRO teaches obtaining a similarity between a current block and a previous block; and coding the current block through a first coding mode in response to the similarity between the current block and the previous block complying with a preset similarity; coding the current block through a second coding mode in response to the similarity between the current block and the previous block not complying with the preset similarity.
Matsuda does not teach obtaining a similarity between a current block and a previous block; and coding the current block through a first coding mode in response to the similarity between the current block and the previous block complying with a preset similarity; coding the current block through a second coding mode in response to the similarity between the current block and the previous block not complying with the preset similarity.
Hence the prior art includes each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
In combination, Matsuda performs the same function as it does separately of managing process of A method for compressing image data in a display panel and index of the pixel pattern assigned to the current block.
MATSUSHIRO performs the same function as it does separately of obtaining a similarity between a current block and a previous block; and coding the current block through a first coding mode in response to the similarity between the current block and the previous block complying with a preset similarity; coding the current block through a second coding mode in response to the similarity between the current block and the previous block not complying with the preset similarity.
Therefore one of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately.
The results of the combination would have been predictable and resulted in modifying the invention of Matsuda to include obtaining a similarity between a current block and a previous block; and coding the current block through a first coding mode in response to the similarity between the current block and the previous block complying with a preset similarity; coding the current block through a second coding mode in response to the similarity between the current block and the previous block not complying with the preset similarity, as disclosed by MATSUSHIRO thereby able to convert an input image into a high-resolution image having a larger number of pixels than the input image as MATSUSHIRO discusses at para. 2.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art before the effective filing of the claimed invention.
Regarding Claim 19, Matsuda discloses selecting a pixel pattern for the current block comprising: selecting a first group of pixels and a second group of pixels from the current block based on each pixel pattern of the plurality of pixels patterns; calculating a first average value of the first group of pixels and a second average value of the second group of pixels; and assigning a pixel pattern to the current block in response to the first average value corresponding to the pixel pattern being larger than a minimum average threshold and the second average value corresponding to the pixel pattern beings smaller than a maximum average threshold, wherein the first group of pixels are located at a same positions as the pixels not being compressed from the corresponding pixel pattern; and the second group of pixels are located at same positions as the pixels being compressed from the pixel pattern (please see paras. 114-117 please notice average pixel values are positive (maximum) and average pixel values are negative (minimum).
MATSUSHIRO discloses a similarity between a current block and a previous block; and coding the current block through a first coding mode in response to the similarity between the current block and the previous block complying with a preset similarity; coding the current block through a second coding mode in response to the similarity between the current block and the previous block not complying with the preset similarity(please see paras. 25, 26 disclosing a plurality of combination pattern reference blocks 6 each consisting of four pixels are set. Then, the similarity between the set reference (preset pixel patterns value) block 6 and the target block 4 is compared. Here, when a reference block 6 similar to the target block 4 is detected, compression coding is performed using the combination pattern 8 of the detected reference block 6 (mode1). On the other hand, when the reference block 6 similar to the target block 4 is not detected (mode 2), the pixel value of each pixel in the target block 4 is encoded as it is. In this case, the information amount of the block of interest 4 is not compressed (mode 2).
Regarding Claim 20, Matsuda the processor is configured to select a pixel pattern for the current block by: selecting a third group of pixels from the current block based on each pixel pattern of the plurality of pixels patterns; calculating a sum value of the third group of pixels for each pixel pattern; and assigning a pixel pattern corresponding to a largest sum value to the current block, wherein the third group of pixels are located at same positions as the pixels not being compressed from the pixel pattern (para. 112, 116, 118, label third are very arbitrary).
Allowable Subject Matter
Claims 6-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
The prior art of MATSUSHIRO ADJ NOBUHITO et al. (JP 2001101407 A) disclosure, paras. 10-61, disclosing, provide a similar image retrieving device capable of performing highly accurate similarity retrieval even when the illumination conditions of a key image and a search image are different. SOLUTION: The histograms of the key image and a search image 100 are inputted to a similarity calculating part 8. On the basis of limit conditions set by a limit condition setting part 9, an appearance parameter calculating part 10 calculates the model parameter of a color appearance model. On the basis of the parameter calculated by the appearance parameter calculating part 10, a normalizing part 8a of the similarity calculating part 8 normalizes the histogram of the search image. The similarity calculating part 8 calculates the similarity between the normalized histogram of the search image and the histogram of the key image. On the basis of the similarity calculated by the similarity calculating part 8, a searched result discriminating part 11 discriminates whether that search image is the candidate image of retrieval or not. A similar image retrieval apparatus including: an appearance parameter calculation unit that calculates a model parameter of a color Apia model; and a similarity calculation unit that normalizes color information of one of a key image and a search image using the model parameter of the appearance parameter calculation unit, and calculates a similarity of the color information between the normalized one image and the other image. There is provided the similar image retrieval apparatus according to the first aspect, further comprising: a constraint condition setting unit that sets a condition representing preservation of a white point of the search image as a constraint condition; and an appearance parameter calculation unit that calculates a model parameter of the color Apia model satisfying the constraint condition set by the constraint condition setting unit.
The prior art of Kim Hayoon et al. (US 20110176608 A1) disclosure; paras. 32-133, discloses, an apparatus for determining an intra prediction mode comprising a variation calculator for calculating a variation of adjacent pixels relative to a current block; a threshold setter for setting a threshold to evaluate the pixel variation; a comparator for comparing between the variation and the threshold; a first prediction mode determination unit for determining a single predetermined prediction mode to be an optimal prediction mode if the variation is below the threshold; and a second prediction mode determination unit for determining a particular prediction mode from a plurality of prediction modes to be the optimal prediction mode through a rate-distortion optimization by performing intra predictions in the plurality of prediction modes if the variation is greater than or equal to the threshold. Comparing between the variation and a preset threshold; determining a single predetermined prediction mode to be an optimal prediction mode if the variation is below the threshold; and determining the optimal prediction mode from a plurality of prediction modes to be the optimal prediction mode through a rate-distortion optimization by performing intra predictions in the plurality of prediction modes if the variation is greater than or equal to the threshold. An intra predictor for calculating a variation of adjacent pixels relative to a current block to compare the variation with a preset threshold, determining a single predetermined prediction mode to be an optimal prediction mode if the variation is below the threshold, determining a particular prediction mode from a plurality of prediction modes to be the optimal prediction mode through a rate-distortion optimization by performing intra predictions in the plurality of prediction modes if the variation is greater than or equal to the threshold, and generating intra predicted values through performing the intra prediction using the determined optimal prediction mode; a subtractor for generating residual signals by subtracting the intra predicted value from actual current pixels within the current block; a transformer for performing discrete cosine transform with respect to the generated residual signals; a quantizer for performing quantization with respect to the discrete cosine transformed residual signals; and an encoder for encoding the quantized residual signals into a bitstream. Calculating a variation of adjacent pixels to a current block to compare the variation with a preset threshold; determining a single predetermined prediction mode to be an optimal prediction mode if the variation is below the threshold, and determining a particular prediction mode from a plurality of prediction modes to be the optimal prediction mode through a rate-distortion optimization by performing intra predictions in the plurality of prediction modes if the variation is greater than or equal to the threshold; generating intra predicted values through performing the intra prediction using the determined optimal prediction mode; generating residual signals by subtracting the intra predicted values from actual current pixels within the current block; performing discrete cosine transform with respect to the generated residual signals; performing quantization with respect to the discrete cosine transformed residual signals; and encoding the quantized residual signals into a bitstream. A video decoding apparatus comprising: a decoder for decoding a received bitstream to extract residual signals; an inverse quantizer for performing inverse quantization with respect to the extracted residual signals; an inverse transformer for performing inverse discrete cosine transform with respect to the inversely quantized residual signals; an intra predictor for selecting either a first prediction mode that does not encode intra prediction mode information or a second prediction mode that encodes the intra prediction mode information based on a variation of adjacent pixels to a current block, and generating intra predicted values by performing an intra prediction in the selected mode; and an adder for adding the inversely discrete cosine transformed residual signals to the intra predicted values in order to reconstruct actual current pixels within the current block. A video decoding method comprising: decoding a received bitstream; extracting residual signals and prediction mode information from the decoded bitstream; performing inverse quantization with respect to the extracted residual signals; performing inverse discrete cosine transform with respect to the inversely quantized residual signals; performing intra prediction to select either a first prediction mode that does not encode intra prediction mode information or a second prediction mode that encodes the intra prediction mode information based on a variation of adjacent pixels to a current block, and generating intra predicted values by performing an intra prediction in the selected mode; and reconstructing actual current pixels within the current block using the intra predicted values and the inversely discrete cosine transformed residual signals.
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/Prabodh M Dharia/
Primary Examiner
Art Unit 2629
02-18-2026